ATMEL AT76C713

Features
• Advanced RISC Architecture, 130 Powerful Instructions, Most Single Clock Cycle
Execution
• Clock Generator Provides CPU Rates up to 48 MHz
• Only One External Clock Crystal of 12 MHz Can Generate All the Required System
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Clocks:
– Internal Clock for Standard UART Rates
– A 48 MHz and 96 MHz Clock for USB Data Recovery
– AVR Processor and System Clock
Full-speed USB Interface (12 Mbit/s) 2.0 Compliant
Two On-chip 16550 UARTs Supporting Baud Rates up to 921 Kbaud
– Both UARTs Incorporate Individual Transmit and Receive FIFOs of 16 Bytes
– UART0 Supports Modem Control Signals
Programmable SPI Interface
On-chip Bootstrap ROM Provides a Variety of Firmware Upgrade Modes
– Device Firmware Upgrade Through USB for the Internal Program SRAM
(No External Non-volatile SPI Memory Required)
– Device Firmware Upgrade Through USB for both the Internal Program SRAM and
the External SPI DataFlash® or EEPROM
– SPI Program Mode from the External DataFlash or EEPROM
External Memory Interface Supporting up to 32 Kbytes of External RAM in Address
Multiplexed Mode, 2 Banks of 256 Bytes in Non-multiplexed Mode, FIFO, or with an
Extra 20 GPIOs
DMA Channels Allow Fast Data Transfers between Endpoint Buffers and Internal or
External SRAM (The DMA Transfer Rate is 12 MHz for All Channels)
8K x 16 bits (up to 11K x 16 bits), In-System SRAM for Program Code (Program
Memory)
On-chip 8 Kbytes SRAM for Data and Variables (Two, Four, and Eight Kbytes can be ReMapped for Program Storage in the Address Area Above the Program Memory)
Two 8-bit Timer/Counters
One 16-bit Timer/Counter
Four External Interrupts Through GPIOs
Programmable Watchdog Timer
Low Voltage Operation:
– 1.8V for the Core
– 1.8V or 3.3V for the Periphery
– 3.3V for the USB
100-pin TQFP Package
High-speed
(48 MHz) AVR
Microcontroller
with USB
Interface
AT76C713
Summary
5665AS–USB–10/04
Overview
2
The AT76C713 is a low-power, high performing USB 2.0 full-speed microcontroller providing advanced features for USB peripherals. It combines a number of functions
required in such a device, including the following:
•
The device is based on the AVR-enhanced RISC architecture core, which combines
an advanced instruction set with 32 general-purpose working registers. By
executing powerful instructions in a single clock cycle, the AT76C713 achieves
throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize
the power consumption versus the processing speed.
•
The clock generation circuit requires a clock input of 12 MHz and provides standard
clock rates for the USB module and the on-chip UARTs, as well as several AVR
CPU rates varying from 16 MHz up to 48 MHz.
•
Internal DMA channels allow fast data transfers between the USB buffers and the
external or the on-chip memory without processor interruption. USB DMA transfers
use devoted data paths with 12 Mbytes/s transfer rate.
•
An on-chip flexible memory controller allows dynamic memory mapping and
provides the required timing for interfacing with slow or fast external memory
devices, like SRAM or FIFOs.
•
Five multipurpose I/O ports, PORT(A-E), provide the signals for all the serial and
parallel interfaces. Programmable strobe signals are provided for external FIFO
access. In addition, the AT76C713 supports various power-down modes and offers
four external interrupts, a programmable watchdog timer, and flexible timer/counters
with compare modes.
•
On power-up, the bootstrap code is executed from the boot ROM. The purpose of
the bootstrap code is to load the application code into the program memory. The
application code is executed from the on-chip SRAM program memory, contributing
to the low-power consumption. Different programming modes are supported,
depending on the application (that is, the mode is selected externally by the
PMODE0 and PMODE1 pins).
•
In the slave programming mode, an external system (that is, the Host), operating as
SPI master, can transfer the program image in a raw format to the program memory
of the device. In this case, the AT76C713 operates as an SPI slave and starts
running from the internal boot ROM code, which switches to the start of program
memory when it detects the end of a valid program transfer from the host to the
AT76C713.
•
In the master programming mode, the AT76C713 reads the whole program image
from an external serial EEPROM or DataFlash and switches to the start of the
program memory when it completes this reading. Alternatively, the AT76C713 reads
only configuration parameters from a small serial non-volatile memory (EEPROM or
DataFlash), enables the USB Controller, and executes the USB Device Firmware
Upgrade (DFU) code stored in the boot ROM.
•
The USB Controller consists of a Serial Interface Engine (SIE), a Function Interface
Unit (FIU), and a System Interface (SI). The SIE performs bit processing, line
coding, packet generation, packet type recognition, serial-parallel data conversion,
and packet delineation. The FIU consists of a protocol engine and a USB device
with one Control Endpoint (EP0) and seven programmable Endpoints with up to 512
bytes maximum total size. All Endpoints support double buffering in order to provide
the maximum performance specified for the USB.
•
The AT76C713 supports two 16550 UART modules with 16 bytes FIFOs in each
direction. UART0 serial interface provides full modem control functionality with the
RTS/CTS, DTR/DSR, RI, and CD signals. These signals are provided by the
general-purpose I/O pins of PORTD.
AT76C713
5665AS–USB–10/04
AT76C713
•
The AT76C713 AVR is supported with a full suite of program and system
development tools, including: C compiler, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
3
5665AS–USB–10/04
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5665AS–USB–10/04