Atmel AVR4920: ASF - USB Device Stack

Atmel AVR4920: ASF - USB Device Stack Compliance and Performance Figures
Features
• Compliance to USB 2.0
- Chapters 8 and 9
- Classes: HID, MSC, CDC, PHDC
• Interoperability: OS, classes, self- and bus-powered
• Performance figures
- Interrupt latency measurement
- Code and RAM footprint
- Low, full, and high speed
- USB power consumption
Atmel
Microcontrollers
Application Note
1 Introduction
Atmel® has always provided a USB device stack that supports AVR® products with
a USB hardware interface. The Atmel AVR UC3 A and B series microcontrollers
are supported with a specific USB device stack in the Atmel AVR Software
Framework (ASF). Since ASF version 2, a new USB device stack is delivered to
support all AVR products. This document describes the validation tests used to
check USB 2.0 compliance for this new USB device stack and the performance
tests used to provide information about stack capabilities.
Rev. 8410A-AVR-08/11
2 Abbreviations
2
ASF
AVR Software Framework
CDC
Communication device class
FS
USB full speed
HID
Human interface device
HS
USB high speed
LS
USB low speed
MSC
Mass storage class
OS
Operating system
PHDC
Peripheral health device class
UDC
USB device controller
UDD
USB device descriptor
UDI
USB device interface
USB
Universal serial bus
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3 Overview
This application note relies on the AVR4900: ASF - USB Device Stack application
note, which should be read first to get information on the USB device stack
implementation.
This document includes results concerning validation and performance:
• The validation tests used to check USB 2.0 compliance
• The performance tests used to give information about USB device stack
capabilities
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4 USB Compliance
4.1 USB compliance tests
The chapter 8 tests validate the UDD module of the USB device stack.
The chapter 9 tests validate the UDD and UDC modules of the USB device stack.
The chapter 9 class tests validate the UDI modules of the USB device stack.
4.1.1 Chapter 8 tests
USB chapter 8 compliance of USB device drivers (UDD) is performed using the
Ch8ck v2.00 tool from Testronic Laboratories.
4.1.2 Chapter 9 tests
4.1.2.1 Chapter 9 compliance
USB chapter 9 compliance is performed using the USB 2.0 Command Verifier tool
from the USB Implementers Forum (usb.org).
All LS/FS/HS modes are exercised on a “USB golden tree” given as reference.
4.1.2.2 Chapter 9 classes
The aim of the class compliance tests is to verify the class implementation (UDI
modules).
USB class compliance of HID, PHDC in FS mode, and MSC in FS/HS modes is
performed using the USB 2.0 Command Verifier tool from the USB Implementers
Forum (usb.org).
4.1.3 High speed test feature
High speed test feature implementation (Test J, Test K, Test SE0_NAK, and Test
PACKET) is performed using the High Speed Electrical Test Tool from the USB
Implementers Forum (usb.org).
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5 USB interoperability
The interoperability tests validate the compliance and robustness of the USB device
stack for various types of USB host operating systems in both bus- and self-powered
modes. These tests are performed using the most common USB device classes.
5.1 Operating systems
•
•
•
•
•
Microsoft® Windows® XP SP3, Windows Vista®, Windows 7 (32-bit)
Apple® Mac OS® X 10.5.8
Ubuntu® 8.04 and Ubuntu 9
OpenSUSE® 11.1
Fedora® 9 and Fedora 10
5.2 Power modes and wake up
• Plug/unplug robustness test in USB self-powered mode
• Plug/unplug robustness test in USB bus-powered mode
• Remote wake up feature in high, full and low speed modes
5.3 USB classes
•
•
•
•
HID mouse
HID keyboard
MSC
CDC
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6 Performance figures
USB device stack performance is evaluated on various parameters:
• The footprint; that is, the total size of code and RAM memory used to run the USB
device stack
• Timing performance
• Transfer rate on various USB device classes
• Power consumption
6.1 Footprint
The USB device stack footprint depends on:
• The AVR core (XMEGA®, megaAVR®, UC3)
• The USB hardware version
• The USB class
• The compiler and the optimization level
These parameters may result in many values for the footprint, but on average the
USB device stack does not exceed 10KB of flash and 1KB of RAM when using a high
level of compiler optimization.
All the examples shown in Table 6-1 have been performed using:
• IAR Embedded Workbench® for 32-bit AVR 3.30 and 8-bit AVR 6.10, with high
size-optimization level
• ASF with the following modules: sleep management service, interrupt
management, startup, external flash memory control, and others
Table 6-1. USB device example code and RAM size.
USB device stack
Part
Code size
(KB)
RAM size
(KB)
Code size
(KB)
RAM size
(KB)
ATxmega256A3BU
5.5
0.6
6
0.6
Example
HID device mouse full speed
CDC device full speed
MSC device high speed
Full example
AT32UC3A0
5
0.3
8
0.4
AT32UC3C0
5
0.4
8
0.6
ATxmega256A3BU
6
1
8
1.5
AT32UC3C0
6
1
9.5
1.5
ATxmega256A3BU
6.5
0.9
9.5
1.5
AT32UC3A0
6.5
0.4
11.5
1
AT32UC3C0
6.5
0.7
11.5
1.5
AT32UC3A3
7
0.4
15.5
2
6.2 Interrupt timing
All USB events are managed by one or two USB interrupt vectors. Each USB event
performs an interrupt, and only one event is decoded by the interrupt process. Thus,
there is no waiting loop in the USB interrupt routine.
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The timing to process an interrupt depends on the compilation level and the USB
interrupt source (USB reset, suspend, end of transfer, etc.). However, this timing does
not exceed 100µs with a high optimization level and a 12MHz CPU frequency.
For more information about USB interrupt behavior and configuration, see the section
entitled “Behavior” in the AVR4900: ASF – USB Device Stack application note.
6.3 Transfer rate
Atmel AVR device USB interfaces support all USB transfer types. The interfaces are
able to support the maximum rate allowed using USB DMA. The speed limit for each
transfer type is given by the USB specification in Table 6-2.
Table 6-2. USB transfer type and limits.
Maximum bandwidth (MB/s)
LS
FS
HS
0.02
0.79
15.14
0.01
0.06
0.49
Bulk
-
1.16
50.78
Isochronous
-
1.22
54.69
Control
Interrupt
Note:
(1)
1. One transaction per start of frame.
However, the final speed performance of a class depends on:
• Class protocol overhead
• Source/destination speed
• USB host performance
The MSC and CDC classes use the USB bulk transfer type, which allows the high
performance of USB device hardware and the associated USB firmware stack to be
easily measured. All the tests are done with a USB host with no latency in order to
measure the full performance limit of the USB device.
6.3.1 MSC
The mass storage class (MSC) uses the USB bulk transfer.
The MSC specification includes a protocol overhead, which reduces the useful data
transfer rate. This reduction is fully dependent on the useful data size requested by a
MSC read/write command. The useful data transfer rate limitation is shown by the
“MSC possibility” patterns in Figure 6-1 and Figure 6-2.
The MSC protocol is managed by software on AVR products, thus speed
performance is dependent on CPU frequency. This is shown by the patterns for the
speeds measured with different CPU frequencies in Figure 6-1 and Figure 6-2. A
memory based on internal RAM gives the real limit of the MSC USB device by
removing the programming latency inherent in mass storage devices.
However, the speed is mainly reduced by memory interface limitations and memory
performance. The SD High Speed card and MMC Plus card, which use a memory
card interface (MCI), show the dependency of the interface and the memory (Figure
6-1, Figure 6-2).
NOTE
The firmware used for the following measurements is compiled using the GCC or
IAR® compiler with a high optimization level.
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Figure 6-1. MSC speed limits for full speed.
1400
1200
Speed (KB/s)
1000
800
600
400
200
0
0
10
20
30
40
50
60
70
Useful data / com m and (KB)
MSC possibility
AT32UC3A0, CPU 12MHz on RAM
AT32UC3A3, CPU 66MHz on SD card High Speed
ATxmega256A3BU, CPU 24MHz on RAM
NOTE
Read and write speed limits are the same.
Figure 6-2. MSC speed limits for high speed.
60
50
Speed (MB/s)
40
30
20
10
0
0
10
20
30
MSC possibility
AT32UC3A3, CPU 66MHz
AT32UC3A3, CPU 48MHz
AT32UC3A3, CPU 12MHz
AT32UC3A3, CPU 66MHz
AT32UC3A3, CPU 66MHz
NOTE
8
40
50
60
70
Useful data / command (KB)
on RAM
on RAM
on RAM
on MCI - MMC Plus card
on MCI - SD High Speed card
Read and write speed limits are the same.
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6.3.2 CDC
The communication class device uses the USB bulk transfer, and does not include a
protocol to transfer data. Thus, the CDC limitation is the bulk limitation shown by the
“CDC possibility” patterns in Figure 6-3.
However, the CDC implementation in the USB device stack requires control of the
data flow between two different flow behaviors (for example, USB and UART) and
can limit the actual speed.
The ASF CDC implementation provides two interfaces to send or receive data on a
USB line. The first is a byte access with the putc and getc functions, and the second
is a data array access with the ReadBuf and WriteBuf functions to target the
maximum of full speed. The maximum speed performance of these accesses is
shown in Figure 6-3, Figure 6-4 and Figure 6-5.
The CDC class can be used as a bridge between UART and USB connections. In this
case, the speed limitation is the UART baud rate.
NOTE
The firmware used for the following measures is compiled using the GCC or IAR
compiler with a high optimization level.
Figure 6-3. CDC speed limits for full speed on an Atmel AT32UC3A0.
1400
ReadBuf
WriteBuf
(CDC possibility) 1200
Speed (KB/s)
1000
800
Putc
600
400
Getc
200
0
0
10
20
30
40
50
60
70
CPU Freq. (MHz)
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Figure 6-4. CDC speed limits for full speed on an Atmel ATxmega256A3BU.
1400
CDC possibility
1200
WriteBuf
1000
Speed (KB/s)
ReadBuf
800
600
400
200
Putc
Getc
0
12
14
16
18
20
22
24
CPU Freq. (MHz)
Figure 6-5. CDC speed limits for high speed on Atmel AT32UC3A3.
7
ReadBuf
6
WriteBuf
Speed (MB/s)
5
4
3
2
1
Putc
Getc
0
0
10
10
20
30
40
50
60
70
CPU Freq. (MHz)
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6.4 Power consumption
Atmel AVR products have been designed to support a USB device application in bus
power mode. In suspend mode, the bus-powered application needs to reduce its
power consumption to be less than 2.5mA at 5V.
All Atmel UC3 products support the static sleep mode in USB suspend mode, which
has a current consumption of less than 1mA at 3.3V.
All Atmel XMEGA products support the power down sleep mode in USB suspend
mode, which has a current consumption of less than 0.5mA at 3.3V.
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7 Table of contents
Features ............................................................................................... 1
1 Introduction ...................................................................................... 1
2 Abbreviations ................................................................................... 2
3 Overview ........................................................................................... 3
4 USB Compliance .............................................................................. 4
4.1 USB compliance tests ......................................................................................... 4
4.1.1 Chapter 8 tests .......................................................................................................... 4
4.1.2 Chapter 9 tests .......................................................................................................... 4
4.1.3 High speed test feature ............................................................................................. 4
5 USB interoperability ........................................................................ 5
5.1 Operating systems .............................................................................................. 5
5.2 Power modes and wake up ................................................................................. 5
5.3 USB classes ........................................................................................................ 5
6 Performance figures ........................................................................ 6
6.1 Footprint .............................................................................................................. 6
6.2 Interrupt timing..................................................................................................... 6
6.3 Transfer rate ........................................................................................................ 7
6.3.1 MSC .......................................................................................................................... 7
6.3.2 CDC........................................................................................................................... 9
6.4 Power consumption........................................................................................... 11
7 Table of contents ........................................................................... 12
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