Si9750 Vishay Siliconix Hot Swap Si9750 In-Rush Current Limit MOSFET Driver FEATURES • 2.9- to 13-V Input Operating Range • Microprocessor RESET • Integrated High-Side Driver for N-Channel MOSFET • Programmable di/dt Current DESCRIPTION The Si9750 current limit MOSFET interface IC is designed to operate between a power source and a load using a low onresistance power MOSFET with a sense terminal or in conjunction with a low ohmic sense resistor. The Si9750 current limiter prevents source and load transients during hot swap and power-on with programmable dv/dt and di/dt. Both turn-on and steady-state current limits can be individually programmed, providing protection against short circuits. Power on RESET and logic controls allow complete microprocessor interfacing. The RESET function of the Si9750 is industry-standard with full programmability. The Si9750 is available in a 16-pin SOIC package and is rated over the commercial temperature range (0 to 70°C). FUNCTIONAL BLOCK DIAGRAM FaxBack 408-970-5600, request 70028 www.siliconix.com S-60752—Rev. C, 05-Apr-99 1 Si9750 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Voltages Referenced to Ground Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 125°C VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Boost Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 V Power Dissipation (package)a 16-Pin SOICb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Inputs/Outputs (except Gate, Boost and VRST) . . . . . . . . . . . . . . . -0.3 to VDD + 0.3 V Thermal Impedance (ΘJA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 140°C/W VRST Input Current (0 < VRST < 15 V) . . . . . . . . . . . . . . . . . . . .20 mA Notes Inputs/Outputs Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA a. Device mounted with all leads soldered or welded to PC board. RESET Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 mA b. Derate 7.2 mW/°C above 25°C. STATUS Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 mA * Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time SPECIFICATIONS Limits Test Conditions Unless Otherwise Specified Parameter Symbol 2.9 V ≤ VDD ≤ 13.2 V HI/LO = GND, RBIAS = 12.5 kΩ LBOOST = 100 µH, CBOOST = 100 nF IQ ENABLE = Logic Low 0 to 70°C Mina Typb Maxa Unit 4 8 mA Supply Quiescent Current Logic Enable Turn-On Voltage VEN(on) Enable Turn-Off Voltage VEN(off) Enable Source Current IENSRC Turn-On Time tON Turn-Off Time tOFF 0.3 x VDD 0.7 x VDD VENABLE = 0V 40 120 5 tON(BST) See Figure 4. 600 tOFF Initial Short Circuit tOFF(ISC) CGATE = 33 nF, See Figure 6. 10 tOFF Short Circuit tOFF(SC) CGATE = 33 nF, See Figure 7. 2 VSTAT ISINK = 200 µA 0.4 tSTDLY See Figure 8. Status Output Delay Time µA 5 See Figure 3. Turn-On Boost Status Output Voltage V µs V µs Status Threshold VSTATTHR 0.85 x VDD HI/LO Turn-On Voltage VHILO(on) 0.7 x VDD HI/LO Turn-Off Voltage VHILO(off) 0.95 x VDD V 0.3 x VDD Gate Drive Enhancement Voltage (VGATE - VSENSE) Source Current Sink Current S-60752—Rev. C, 05-Apr-99 2 VGS ISOURCE ISINK VCBOOST = 9 V 8.5 10.5 15 1.06 1.30 1.54 1.6 2.6 3.7 V mA FaxBack 408-970-5600, request 70028 www.siliconix.com Si9750 Vishay Siliconix SPECIFICATIONS Limits Test Conditions Unless Otherwise Specified Parameter Symbol 2.9 V ≤ VDD ≤ 13.2 V HI/LO = GND, RBIAS = 12.5 kΩ LBOOST = 100 µH, CBOOST = 100 nF 0 to 70°C Mina Typb Maxa Unit Current Sense Circuit Current Sense Amplifier Common Mode Range VCMR 0 VDD + 0.3 V Current Sense Amplifier Voltage Offset VOS -3 3 mV Current Sense Amplifier Bias Current ISOS RLIMSET Reference Current Normal Operation IRLIMSET -0.2 18 Current Sense Amplifier Hysteresis VHYST Current Sense Amplifier Series Offset VSOS HI/LO = VDD, VCMR > 0.5 V VOP(rst) IOUT = 1 mA, VDD > 2 V µA 19.5 21 12 mV 20 Power On Reset RESET Output Voltage RESET Output Hysteresisc 0.4 VHYST 2 See Note c V mV RESET Comparator Input Threshold VRST RESET Comparator Offset Voltaged VRBIAS 0.5 mV RESET Comparator Input Bias Current IBIAS -0.2 µA RESET Timer Delay tRSTD CRST = 15 nF, See Figure 8. 110 150 190 µs RETRY tRETRY CRETRY = 100 nF 70 130 200 ms 1.223 1.250 1.277 V Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production test. c. In a practical situation, VHYST is multiplied by ratio of a resistor divider chain. For VDD = 13.2 V, VHYST = 20 mV. d. The RESET comparator input threshold specification (VRST) includes the RESET comparator offset voltage. FaxBack 408-970-5600, request 70028 www.siliconix.com S-60752—Rev. C, 05-Apr-99 3 Si9750 Vishay Siliconix PIN CONFIGURATION PIN DESCRIPTION Pin Number Function Description 1 BOOST Output of on-chip Boost converter. A 100-nF capacitor should be connected between BOOST and GND 2 VDD Positive supply pin. 3 GATE Connection to external power MOSFET gate. 4 LOAD Connection to positive supply side of LOAD. 5 SENSE Connects external sense resistor of a sensefet sense pin to SENSE input of overcurrent trip comparator. A standard MOSFET may also be used in conjunction with a low ohmic value shunt resistor. 6 LIMSET Connects overcurrent limit set resistor RLIMSET to the reference input of overcurrent trip comparator. 7 HI/LO CMOS logic input to control the overcurrent trip comparator sensitivity at power-on. HI/LO should be connected to GND for low Capacitive loads and to VDD for high capacitive loads. 8 ENABLE 9 RBIAS A resistor connected from this pin to GND programs the reference bias current for the overcurrent trip comparator resistor RLIMSET and the GATE(on) charge current. See Functional Description for equations. 10 VRST Input to voltage monitor comparator. 11 STATUS Open drain NMOS output. This pin is driven low when the current limiter is enabled and the LOAD voltage is greater than 90% of VDD. 12 RESET Open drain NMOS output. This pin is driven low during power on reset or when VRST is lower than the internal 1.25-V reference. 13 CRETRY A capacitor connected from this pin to GND programs the retry timer. 14 CRST A capacitor connected from this pin to GND programs the reset timer. 15 GND Negative supply pin. 16 COIL Connection to Boost converter inductor. S-60752—Rev. C, 05-Apr-99 4 CMOS logic input to turn IC on or off. GATE voltage remains low when ENABLE is high. FaxBack 408-970-5600, request 70028 www.siliconix.com Si9750 Vishay Siliconix FUNCTIONAL DESCRIPTION The Si9750 together with an n-channel MOSFET provides the following functions: • limits di/dt current for hot insertion applications • provides complete short circuit protection • high-side drive allows n-channel MOSFET to be used, for lower power dissipation • industry-standard microprocessor reset function • logic control input and outputs Setting the Current Limit (SENSE, HI/LO pins, RLIMSET, RSENSE) The steady state current is set by the equation: (1) Due to the highly capacitive nature of some loads, the Si9750 has an option to increase the current limit point to a much higher level at turn-on. In this case, turn-on is defined as VGATE < VDD + 7.8 V. This function is implemented with the HI/ LO pin. If the HI/LO pin is tied low the current limit is 20% higher during turn-on than the steady state current limit point. I LOAD × R SENSE > 1.2 × I BIAS × R LIMSET ( with pin HI/LO=Low ) I LOAD × R SENSE > 1.2 × I BIAS × R LIMSET + I BIAS ( 1kΩ + R HI ) (3) ( HI/LO=High ) Notice that any current limit can be set at turn-on using an optional resistor, RHI. Relaxation Mode Current Limit (CRETRY pin) The current limit point is determined by the voltage across RSENSE, the value of RLIMSET, and the bias current. The current limit circuit is shown in Figure 1. I LOAD × R SENSE > I BIAS × R LIMSET If a higher current limit is needed at start-up, the HI/LO pin can be tied high. The equation becomes: In an overload condition, the Si9750 will go into a relaxation mode current limit operation that not only protects the source and load, but also reduces the power dissipated in the MOSFET. When an overload is detected, the circuit quickly turns off, then goes into a retry mode whereby the current is ramped up slowly. If the fault still exists, the current will ramp down again. This sequence will repeat indefinitely at a period defined by 106 x CRETRY until the fault is removed. Typically, capacitors in the range of 1 nF to 1 µF can be used on CRETRY, but the period should be >50 ms. (2) FIGURE 1. FaxBack 408-970-5600, request 70028 www.siliconix.com S-60752—Rev. C, 05-Apr-99 5 Si9750 Vishay Siliconix di/dt Limiting On Hot and Cold Insertion (GATE pin) The GATE pin provides a constant current source that is used to control the rate of rise of the gate of the MOSFET, and hence to control the di/dt of the load and source current. The equation that governs the gate current is: 12 I SOURCE = 1.25V × --------------- = 12mA R BIAS (4) ( for R BIAS = 12.5kΩ ) Typically, a 33-nF capacitor should be connected from the GATE pin to ground. If a large ISOURCE is needed for high di/ dt, a 330-Ω resistor in series with CGATE may be necessary to prevent oscillation. In the case that VDD > 6 V, a resistor of approximately 330 Ω is also recommended in series with the gate (Figure 1). Reference Bias Current (RBIAS pin) This pin sets the internal current used by RLIMSET to determine all the current limit points. Typically RBIAS = 12.5 kΩ which sets a 20-µA bias current. The equation which relates RBIAS to IBIAS is: 1.25V I BIAS = -----------------------= 20µA 5 × R BIAS Logic Control (STATUS, ENABLE, RESET, VRST and CRST pins) STATUS. The status monitor detects when the load voltage is 90% of input voltage, VLOAD > 0.9 x VDD. This pin is an opendrain NMOS output, capable of sinking 200 µA at VOL = 0.4 V. If this pin is used in conjunction with the ENABLE of another unit, power supply sequencing (or daisy-chaining) is easily implemented. ENABLE. This CMOS logic compatible input serves as the on/off control pin. This pin has 40-µA minimum pull-up to VDD. RESET (VRST, CRST, RESET pins). This is a standard implementation of the microprocessor reset function. A comparator looks at the voltage on VRST pin and compares it with 1.25 V. This function is programmable by using an external voltage divider. When VRST is higher than 1.25 V, the reset signal is delayed by the CRST pin, defined by Equation (6) and then goes high (Figure 8). 4 Reset delay t RSTD ≈ 10 × C RST (6) (5) ( for R BIAS = 12.5kΩ ) Power on Reset (POR) (VDD pin) This function monitors the voltage on the VDD pin and signals the system if all input voltage requirements have been met. At turn-on when VDD > 2.7 V " 200 mV, a POR signal is generated for a duration of 100 µs. After this point the system is released into operation. If VDD falls below 2.7 V " 200 mV, a second POR signal will be generated. If two POR signals are detected, this indicates that the source for VDD is not capable of supplying the load current. The IC then turns off the MOSFET and initiates its retry period, hence fully protecting the MOSFET from an over-power condition. Boost Converter (COIL, BOOST pins) FIGURE 2. Typical Operation Under Start-up Condition with an Overcurrent Fault Applied to the Output The boost converter generates the gate drive for the external n-channel MOSFET. This is limited to typically VDD + 11 V. The boost inductor should typically be 100 µH, <3.5 Ω, >180 mA dc, and the boost capacitor should be 100 nF. S-60752—Rev. C, 05-Apr-99 6 FaxBack 408-970-5600, request 70028 www.siliconix.com Si9750 Vishay Siliconix TYPICAL CHARACTERISTICS (25°C UNLESS NOTED) FaxBack 408-970-5600, request 70028 www.siliconix.com S-60752—Rev. C, 05-Apr-99 7 Si9750 Vishay Siliconix SWITCHING TIME TEST CIRCUITS FIGURE 3. Normal-Mode Operation FIGURE 4. Timing Definition with ENABLE Already On FIGURE 5. Start of Boost Converter S-60752—Rev. C, 05-Apr-99 8 FaxBack 408-970-5600, request 70028 www.siliconix.com Si9750 Vishay Siliconix FIGURE 6. First Short Circuit FIGURE 7. Relaxation-Mode Current Limit SWITCHING TIME TEST CIRCUITS FIGURE 8. STATUS and RESET FaxBack 408-970-5600, request 70028 www.siliconix.com S-60752—Rev. C, 05-Apr-99 9