FAIRCHILD 74ACT520

Revised November 1999
74AC520 • 74ACT520
8-Bit Identity Comparator
General Description
Features
The AC/ACT520 are expandable 8-bit comparators. They
compare two words of up to eight bits each and provide a
LOW output when the two words match bit for bit. The
expansion input IA = B also serves as an active LOW enable
input.
■ Compares two 8-bit words in 6.5 ns typ
■ Expandable to any word length
■ 20-pin package
■ Outputs source/sink 24 mA
■ ACT520 has TTL-compatible inputs
Ordering Code:
Order Number
Package Number
74AC520SC
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC520PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT520SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT520SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT520PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
A0–A7
Word A Inputs
B0–B7
Word B Inputs
TA = B
Expansion or Enable Input
OA = B
Identity Output
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010194
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74AC520 • 74ACT520 8-Bit Identity Comparator
February 1989
74AC520 • 74ACT520
Truth Table
Logic Diagram
Inputs
IA = B
A, B
Outputs
OA = B
L
A = B (Note 1)
L
L
A≠Β
H
H
A = B (Note 1)
H
H
A≠Β
H
H = HIGH Voltage Level
L = LOW Voltage Level
Note 1: *A0 = B0, A1 = B1, A2 = B 2, etc.
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Applications
Ripple Expansion
Parallel Expansion
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2
Recommended Operating
Conditions
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
−20 mA
VI = VCC + 0.5V
+20 mA
Supply Voltage (VCC)
−0.5V to VCC + 0.5V
DC Input Voltage (VI)
VO = VCC + 0.5V
+20 mA
0V to VCC
−40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
AC Devices
DC Output Source
VIN from 30% to 70% of VCC
±50 mA
VCC @ 3.3V, 4.5V, 5.5V
DC VCC or Ground Current
125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
±50 mA
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
0V to VCC
Operating Temperature (TA)
−0.5V to VCC + 0.5V
or Sink Current (IO)
4.5V to 5.5V
Output Voltage (VO)
−20 mA
DC Output Voltage (VO)
2.0V to 6.0V
ACT
Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
AC
ACT Devices
−65°C to +150°C
VIN from 0.8V to 2.0V
Junction Temperature (TJ)
VCC @ 4.5V, 5.5V
PDIP
140°C
125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
VIH
VIL
VOH
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
(V)
Typ
Guaranteed Limits
Minimum HIGH Level
3.0
1.5
Input Voltage
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
2.1
Units
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
Conditions
VOUT = 0.1V
2.1
V
or VCC − 0.1V
VOUT = 0.1V
V
or VCC − 0.1V
V
IOUT = −50 µA
VIN = VIL or VIH
VOL
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
0.36
0.44
IOH = −12 mA
V
IOH = −24 mA
IOH = −24 mA (Note 3)
V
IOUT = 50 µA
VIN = VIL or VIH
3.0
4.5
0.36
0.44
5.5
0.36
0.44
IOL = 12 mA
V
IOL = 24 mA
IOL = 24 mA (Note 3)
IIN (Note 5)
Maximum Input Leakage Current
5.5
±0.1
±1.0
µA
VI = VCC, GND, A Inputs Only
IIH
Maximum Input HIGH Leakage Current
5.5
10.0
10.0
µA
VI = VCC, B Inputs Only
IIL
Maximum Input LOW Leakage Current
5.5
−0.6
−1.0
mA
VI = VCC, B Inputs Only
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 4)
5.5
ICC
Maximum Quiescent Supply Current
5.5
ICC (Note 5) Maximum Quiescent Supply Current
5.5
−0.3
2.3
−75
mA
VOHD = 3.85V Min
4.0
40.0
µA
VIN = VCC
4.8
8.0
mA
VIN = GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
3
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74AC520 • 74ACT520
Absolute Maximum Ratings(Note 2)
74AC520 • 74ACT520
DC Electrical Characteristics for ACT
Symbol
VIH
VIL
VOH
Parameter
Minimum HIGH Level
TA = +25°C
VCC
(V)
Typ
4.5
1.5
TA = −40°C to +85°C
Guaranteed Limits
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
3.86
3.76
Units
V
V
Conditions
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
V
IOUT = −50 µA
V
IOH = −24 mA
VIN = VIL or VIH
4.5
5.5
VOL
IOH = −24 mA (Note 6)
4.86
4.76
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
5.5
±0.1
±1.0
µA
5.5
10.0
10.0
µA
V
IOUT = 50 µA
V
IOL = 24 mA
VIN = VIL or VIH
IIN
Maximum Input
Leakage Current
IIH
Maximum Input
HIGH Leakage Current
IIL
Maximum Input
LOW Leakage Current
ICCT
Maximum
5.5
−0.3
5.5
0.6
−0.6
−1.0
IOL = 24 mA (Note 6)
mA
VI = VCC, GND
VI = VCC
B Inputs Only
VI = VCC
B Inputs Only
1.5
mA
VI = VCC − 2.1V
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 7)
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent
4.0
40.0
µA
4.8
8.0
mA
ICC/Input
Supply Current
ICC
Maximum Quiescent
Supply Current
5.5
5.5
2.3
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
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VIN = VCC
or GND
VIN = GND
Symbol
Parameter
tPLH
tPHL
tPLH
tPHL
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Units
(Note 8)
Min
Typ
Max
Min
Max
Propagation Delay
3.3
4.0
7.5
11.5
3.0
13.0
An or Bn to O A = B
5.0
2.5
5.5
8.5
2.0
9.5
Propagation Delay
3.3
4.5
8.0
12.0
3.5
13.5
An or Bn to OA = B
5.0
3.0
5.5
9.0
2.5
10.0
Propagation Delay
3.3
3.5
5.5
8.5
2.5
9.5
IA = B to OA = B
5.0
2.5
4.5
6.5
2.0
7.0
Propagation Delay
3.3
3.5
5.5
8.5
2.5
9.5
IA = B to OA = B
5.0
2.5
4.5
6.5
2.0
7.0
ns
ns
ns
ns
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
Symbol
Parameter
Propagation Delay
tPLH
An or Bn to OA = B
tPHL
Propagation Delay
An or Bn to OA = B
tPLH
Propagation Delay
IA = B to OA = B
tPHL
Propagation Delay
IA = B to OA = B
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Units
(Note 9)
Min
Typ
Max
Min
Max
5.0
3.0
5.5
8.5
2.5
9.5
ns
5.0
3.0
6.0
10.0
2.5
11.5
ns
5.0
2.0
4.0
6.0
2.0
6.5
ns
5.0
2.5
5.0
7.5
2.0
8.5
ns
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC = OPEN
CPD
Power Dissipation Capacitance
40
pF
VCC = 5.0V
5
Conditions
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74AC520 • 74ACT520
AC Electrical Characteristics for AC
74AC520 • 74ACT520
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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6
74AC520 • 74ACT520
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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74AC520 • 74ACT520 8-Bit Identity Comparator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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