Revised August 2000 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. ■ ICC reduced by 50% ■ Outputs source/sink 24 mA ■ ACT109 has TTL-compatible inputs Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Order Number Package Number 74AC109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC109SJ 74AC109MTC 74AC109PC MTC16 N16E 74ACT109SC M16A 74AC109MTC MTC16 74ACT109PC N16E Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description J1, J2, K1, K2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q2, Q1, Q2 Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS009923 www.fairchildsemi.com 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop November 1988 74AC109 • 74ACT109 Logic Symbols IEEE/IEC Truth Table (each half) Inputs Outputs SD CD CP J K Q Q L H X X X H L H L X X X L H L L X X X H H H H L L L H H H L H H H H H H L H Toggle L H Q0 Q0 H H H L X X Q0 Q0 H = HIGH Voltage Level L = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Q0(Q0) = Previous Q0(Q0) before LOW-to-HIGH Transition of Clock Logic Diagram (one half shown) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V VO = VCC + 0.5V +20 mA 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) AC Devices DC Output Source VIN from 30% to 70% of VCC ± 50 mA VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate (∆V/∆t) DC VCC or Ground Current ± 50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) −0.5V to VCC + 0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V AC ACT Devices −65°C to +150 °C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V 140°C PDIP 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables.Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH VCC TA = +25°C (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 0.002 0.1 0.1 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) Maximum LOW Level 3.0 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.1 ± 1.0 µA V IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA V IOL = 24 mA (Note 2) IIN Maximum Input (Note 4) Leakage Current IOLD Minimum Dynamic 5.5 75 mA IOHD Output Current (Note 3) 5.5 −75 mA ICC Maximum Quiescent (Note 4) Supply Current 5.5 2.0 20.0 IOL = 24 mA µA VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC109 • 74ACT109 Absolute Maximum Ratings(Note 1) 74AC109 • 74ACT109 DC Electrical Characteristics for ACT Symbol Parameter (V) Typ 4.5 1.5 Input Voltage 5.5 Maximum LOW Level 4.5 Input Voltage Minimum HIGH Level VIH VIL VOH TA = +25°C VCC TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 1.5 2.0 2.0 1.5 0.8 0.8 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 0.36 0.44 IOH = −24 mA (Note 5) V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH 4.5 IOL = 24 mA (Note 5) 5.5 0.36 0.44 IIN Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µA FVI = VCC, GND ICCT Maximum ICC/Input 5.5 1.5 mA VI = VCC − 2.1V 0.6 IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 20.0 µA VIN = VCC or GND Supply Current 5.5 2.0 Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol fMAX tPLH tPHL tPLH tPHL Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 7) Min Typ Maximum Clock 3.3 125 150 100 Frequency 5.0 150 175 125 Propagation Delay 3.3 4.0 8.0 13.5 3.5 16.0 CPn to Qn or Qn 5.0 2.5 6.0 10.0 2.0 10.5 Propagation Delay 3.3 3.0 8.0 14.0 3.0 14.5 CPn to Qn or Qn 5.0 2.0 6.0 10.0 1.5 10.5 Propagation Delay 3.3 3.0 8.0 12.0 2.5 13.0 CDn or SDn to Qn or Qn 5.0 2.5 6.0 9.0 2.0 10.0 Propagation Delay 3.3 3.0 10.0 12.0 3.0 13.5 CDn or SDn to Qn or Qn 5.0 2.0 7.5 9.5 2.0 10.5 Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 4 Max Min Units Max MHz ns ns ns ns Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 8) tS tH tW tREC TA = −40°C to +85°C CL = 50 pF Typ Units Guaranteed Minimum Setup Time, HIGH or LOW 3.3 3.5 6.5 7.5 Jn or Kn to CPn 5.0 2.0 4.5 5.0 Hold Time, HIGH or LOW 3.3 −1.5 0 0 Jn or Kn to CPn 5.0 −0.5 0.5 0.5 Pulse Width 3.3 2.0 7.0 7.5 CDn or SDn 5.0 2.0 4.5 5.0 Recovery Time 3.3 −2.5 0 0 CDn or SDn to CPn 5.0 −1.5 0 0 ns ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics for ACT Symbol Parameter fMAX Maximum Clock Frequency tPLH Propagation Delay CPn to Qn or Qn tPHL Propagation Delay CPn to Qn or Qn tPLH Propagation Delay CDn or SDn to Qn or Qn tPHL Propagation Delay CDn or SDn to Qn or Qn VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Max Min Units (Note 9) Min Typ Max 5.0 145 210 5.0 4.0 7.0 11.0 3.5 13.0 ns 5.0 3.0 6.0 10.0 2.5 11.5 ns 5.0 2.5 5.5 9.5 2.0 10.5 ns 5.0 2.5 6.0 10.0 2.0 11.5 ns 125 MHz Note 9: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements for ACT Symbol tS Parameter Setup Time, HIGH or LOW Jn or Kn to CPn tH Hold Time, HIGH or LOW Jn or Kn to CPn tW Pulse Width CPn or CDn or SDn trec Recovery Time CDn or SDn to CPn VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 10) Typ Guaranteed Minimum 5.0 0.5 2.0 2.5 ns 5.0 0 2.0 2.0 ns 5.0 3.0 5.0 6.0 ns 5.0 −2.5 0 0 ns Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 35.0 pF VCC = 5.0V 5 Conditions www.fairchildsemi.com 74AC109 • 74ACT109 AC Operating Requirements for AC 74AC109 • 74ACT109 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 6 74AC109 • 74ACT109 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com 74AC109 • 74ACT109 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 8 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com