FUJITSU SEMICONDUCTOR DATA SHEET DS04-13501-2E LINEAR IC R-2R TYPE 8-BIT D/A CONVERTER WITH OPERATIONAL AMPLIFIER OUTPUT BUFFERS MB88346B ■ DESCRIPTION The Fujitsu MB88346B is an R-2R type 8-bit resolution digital-to-analog converter (DAC), designed for interface with a wide range of general 4bit and 8-bit microcontrollers including Fujitsu’s MB88200 family, MB8850 family, and MB88500 family 4-bit single-chip microcontrollers. MB88346B-P The MB88346B has an 8-bit x 12-channel D/A converter with operational amplifier output buffers. Digital data are input serially by individual channel units. The loaded digital data are converted into analog DC voltages by the D/A converter in 20 µs settling time. Also, the MB88346B has operational amplifier output buffers. These operational amplifier output buffers are connected to each channel of the D/A converter, and provide high current drive capability. The MB88346B is suitable for electronic volumes and replacement for potentiometers for adjustment, in addition to normal D/A converter applications. ■ PLASTIC DIP (DIP-20P-M02) MB88346B-PF FEATURES • Conversion method : R-2R resistor ladder • 8-bit x 12-channel D/A converter with operational amplifier output buffers • Max. 2.5MHz Serial data input • Serial data output for cascade connection • Max. 20 µs DAC output settling time • Max. +1.0/-1.0 mA analog output sink/source current • Two separate power supply/ground lines for MCU interface block/ operational amplifier output buffer block and D/A converter block • Pin compatible with MB88341 • Single +5V power supply • Wide operating temperature range: -20°C to +85°C • Silicon-gate CMOS process • Three package options : 20-pin plastic DIP (Suffix : -P), 20-pin plastic SOP (Suffix : -PF), 20-pin plastic SSOP(Suffix : -PFV) PLASTIC SOP (FPT-20P-M01) MB88346B-PFV PLASTIC SSOP (FPT-20P-M03) This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. 1 MB88346B ■ PIN ASSIGNMENT MB88346B-PF MB88346B-P MB88346B-PFV Vss 1 20 GND Vss 1 20 GND Vss 1 20 GND AO3 2 19 AO2 AO3 2 19 AO2 AO3 2 19 AO2 AO4 3 18 AO1 AO4 3 18 AO1 AO4 3 18 AO1 AO5 4 17 DI AO5 4 17 DI AO5 4 17 DI AO6 5 16 CLK AO6 5 16 CLK AO6 5 16 CLK 15 LD (Top View) (Top View) (Top View) AO7 6 15 LD AO7 6 15 LD AO7 6 AO8 7 14 DO AO8 7 14 DO AO8 7 14 DO AO9 8 13 AO12 AO9 8 13 AO12 AO9 8 13 AO12 AO10 9 12 AO11 AO10 9 12 AO11 AO10 9 12 AO11 VDD 10 11 Vcc VDD 10 11 Vcc VDD 10 11 Vcc Figure 1 Logic Symbol +5V Shift Clock Input CLK Data Input DI Load Strobe Input LD Vcc +5V VDD AO1 - AO12 DAC Output DO Data Output MB88346B GND Vss 2 12 MB88346B ■ BLOCK DIAGRAM Vcc GND Digital Block (MCU Interface) 12-bit Shift Register CLK DI DO D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 LD 4-bit Address Decoder 8 12 D0 D1 D6 D7 10 11 12 D6 D7 D0 D1 8-bit Data Latch #1 8-bit Data Latch #12 R-2R Type 8-bit D/A Converter #1 R-2R Type 8-bit D/A Converter #12 Analog Block (D/A Converter with operational amplifier output buffers) + - VDD* 1 2 3 4 + - AO1 AO12 Vss* * : Only for D/A converter block except operational amplifier block 3 MB88346B ■ PIN DESCRIPTION PIN ASSIGNMENT and Tableshow the pin assignment and pin description of the MB88346B. Table 1 Pin Description Symbol Pin No. Type Name & Function Power Supply VCC 11 - +5V DC power supply pin for the digital block (MCU interface) and operational amplifier output buffers. GND 20 - Ground pin for the digital block (MCU interface) and operational amplifier output buffers. VDD 10 - DC power supply pin for the analog block (D/A converter) except operational amplifier output buffers. VSS 1 - Ground pin for the analog block (D/A converter) except operational amplifier output buffers. 16 I Shift clock input to the internal 12-bit shift register: At the rising edge of CLK data on the DI pin is shifted into the LSB of the shift register and contents of the shift register are shifted right (to the MSB). I Load strobe input for a 12-bit address/data : A high level on the LD pin latches a 4-bit address (upper 4 bits: D11 to D8) of the internal 12-bit shift register into the internal address decoder, and writes 8-bit data (lower 8 bits: D7 to D0) of the shift register into an internal data latch selected by the latched address. Control Input CLK LD 15 Data Input/Output DI 17 I Serial address/data input to the internal 12-bit shift register: The address/ data format is that upper 4 bits (D11 to D8) indicate an address and lower 8 bits (D7 to D0) indicate data. The D11 (MSB) is the first-in bit and D0 (LSB) is the last-in bit. DO 14 O Serial address/data output from the internal 12-bit shift register: This is an output pin of the MSB bit data of the 12-bit shift register. This pin allows a cascade connection of the device. DAC Output AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12 4 18 19 2 3 4 5 6 7 8 9 12 13 8-bit resolution D/A converter outputs : 12 channels of DAC outputs (AO1 to AO12) are provided. O Each output channel has an operational amplifier output buffer for analog output data. MB88346B ■ FUNCTIONAL DESCRIPTION OVERVIEW The MB88346B is an R-2R resistor ladder type, 8-bit resolution digital-to-analog converter (DAC) device. The MB88346B has 12 channels of D/A converters with operational amplifier output buffers. 8-bit digital data are loaded into internal data latches by individual DAC channel units. The loaded digital data are converted into analog DC voltages through the internal D/A converter in max. 20 µs settling time. And the analog DC voltages source/sink the output current through the operational amplifier output buffers. For cascade connection, a serial data output is provided. DEVICE CONFIGURATION As illustrated in BLOCK DIAGRAM, the MB88346B device is composed by the digital block (MCU interface) and analog block (D/A converter with operational amplifier output buffers). The digital block consists of a 12-bit shift register, a 4-bit address decoder, and 12-channels of 8-bit data latches. The analog block includes 12 channels of 8-bit D/A converters with operational amplifier output buffers connecting to the data latches. For electrically stable operation the power supply and ground lines are separate between the digital block (MCU interface) and operational amplifier output buffers, and analog block except operational amplifier output buffers. DEVICE OPERATION Figure 2 shows the input/output timing. A 12-bit address/data is serially input into the shift register through the DI pin synchronously with the rising edge of CLK. The format of the shift register is shown in Figure 3. The lower 8 bits (D7 to D0) are data bits to be converted, and the upper 4 bits are address bits (D11 to D8) to select a data latch to be written. A high level on the LD pin loads the address decoder with the 4bit address to select a data latch, and writes the 8-bit data into a selected data latch. Figure 4 shows the data latch address map, and Table, address decoding. 8-bit data written into individual data latches are converted into analog DC voltages, dividing the supply voltage |VDD-Vss| through R-2R resistor ladders of D/A converters. The operational amplifier output buffers at individual D/A converter outputs can source up to 1.0 mA of the output current. Figure 5 shows a configuration of the R-2R resistor ladder D/A converter with operational amplifier, and Table 3analog DC voltages corresponding to each digital data. Figure 2 Input/Output Timing CLK MSB DI D11 D10 LSB D9 D8 D2 D1 D0 LD AOx Previous Data New Data 5 MB88346B Figure 3 Shift Register Format (Last-In) (First-In) LSB MSB DO DI D0 D1 D2 D3 D4 D5 D6 D7 D8 8-bit Data D9 D10 D11 4-bit Address To Data Latch To Address Decoder Figure 4 Data Latch Address Map Address 6 1H Data Latch #1 D/A Converter #1 Op-Amp. #1 AO1 2H Data Latch #2 D/A Converter #2 Op-Amp. #2 AO2 3H Data Latch #3 D/A Converter #3 Op-Amp. #3 AO3 4H Data Latch #4 D/A Converter #4 Op-Amp. #4 AO4 5H Data Latch #5 D/A Converter #5 Op-Amp. #5 AO5 6H Data Latch #6 D/A Converter #6 Op-Amp. #6 AO6 7H Data Latch #7 D/A Converter #7 Op-Amp. #7 AO7 8H Data Latch #8 D/A Converter #8 Op-Amp. #8 AO8 9H Data Latch #9 D/A Converter #9 Op-Amp. #9 AO9 AH Data Latch #10 D/A Converter #10 Op-Amp. #10 AO10 BH Data Latch #11 D/A Converter #11 Op-Amp. #11 AO11 CH Data Latch #12 D/A Converter #12 Op-Amp. #12 AO12 MB88346B Figure 5 Configuration of R-2R Resistor Ladder D/A Converter VDD SW VDD VSS 2R 2R D0 2R R D1 2R R Data Latch D2 2R R D3 2R R 2R R 2R R D4 D5 Internal Bias Generator * (Common to ch. #1-ch. #12) D6 2R D7 R + - AOx Operational Amplifier Output Buffer* * : Powered/grounded by the VCC and GND pins. 7 MB88346B Table 2 Address Decoding Address Data Latch Selected D8 D9 D10 D11 MB88346B 0 0 0 0 Deselected 0 0 0 1 Data Latch #1 0 0 1 0 Data Latch #2 0 0 1 1 Data Latch #3 0 1 0 0 Data Latch #4 0 1 0 1 Data Latch #5 0 1 1 0 Data Latch #6 0 1 1 1 Data Latch #7 1 0 0 0 Data Latch #8 1 0 0 1 Data Latch #9 1 0 1 0 Data Latch #10 1 0 1 1 Data Latch #11 1 1 0 0 Data Latch #12 1 1 0 1 Deselected 1 1 1 0 Deselected 1 1 1 1 Deselected Table 3 Data Conversion Data 8 DAC Output Level D7 D6 D5 D4 D3 D2 D1 D0 AOx 0 0 0 0 0 0 0 0 ≈ VSS 0 0 0 0 0 0 0 1 ≈ (VDD-VSS) x 1/255 + VSS 0 0 0 0 0 0 1 0 ≈ (VDD-VSS) x 2/255 + VSS 0 0 0 0 0 0 1 1 ≈ (VDD-VSS) x 3/255 + VSS 1 1 1 1 1 1 1 0 ≈ (VDD-VSS) x 254/255 + VSS 1 1 1 1 1 1 1 1 ≈ VDD MB88346B Figure 6 Cascade Connection Example +5V VDD VDD VDD Vcc MB88346B MB88341* MB88346B DATA (SO) Microcontroller CLOCK (SC/TO) Strobe DI DO CLK LD DI DO DI CLK CLK LD LD DO GND GND Vss GND Vss GND Vss * : MB88346B can be used mixed with MB88341. 9 MB88346B ■ APPLICATION DESCRIPTION The MB88346B is suitable for electronic volumes and replacement for adjustment potentiometers, in addition to normal D/A converter applications. Figure 7 illustrates application example for a gain control. Figure 7 Application Example - Gain Control +5V Input Vcc Vcc VDD I/O port DI I/O port CLK I/O port LD MB88346B I/O port DO Low reference voltage Vss Microcontroller GND GND 10 AOX Output MB88346B ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (See NOTE) ■ Parameter Symbol Rating Unit Condition 7.0 V - 7.0 V Ta = +25°C GND = 0 V VDD ≤ Vcc, -0.3 - Vcc+0.3 V VOUT -0.3 - Vcc+0.3 V Power Dissipation PD - - 250 mW Operating Ambient Temperature Ta -20 - +85 °C TSTG -55 - +150 °C Supply Voltage Input Voltage Output Voltage Storage Temperature Min Typ Max Vcc -0.3 - VDD -0.3 VIN Ta = +25°C GND = 0 V NOTE : Permanent device damage may occur if the above ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min Typ Max VCC 4.5 5.0 5.5 V GND - 0 - V VCC 2.0 - VCC V VSS GND - VCC-2.0 V Analog Output Source Current IAL - - +1.0 mA Analog Output Sink Current IAH - - +1.0 mA Analog Output Load Capacitance for oscillation limit CAL - - 1.0 µF Operating Ambient Temperature Ta -20 - +85 °C Supply Voltage (for MCU Interface/Op.-Amp. Block) Supply Voltage (for Analog Block*) Condition VCC≥VDD VDD-VSS≥2.0V * : Except operational amplifier output buffer block 11 MB88346B ■ DC CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Digital Block (MCU Interface) Parameter Value Symbol Min Typ Max Unit Condition Active Supply Current (VCC) * ICC - 2.5 4.5 mA CLK = 1MHz, Unloaded Input Leakage Current (CLK, DI, and LD) IILK -10 - +10 µA VIN = 0 to Vcc Input Low Voltage (CLK, DI, and LD) VIL - - 0.2•Vcc V Input High Voltage (CLK, DI, and LD) VIH 0.5•Vcc - - V Output Low Voltage (DO) VOL - - 0.4 V IOL = 2.5 mA Output High Voltage (DO) VOH Vcc-0.4 - - V IOH = -400 µA * : Including the supply current to the operational amplifier block Analog Block (D/A Converters with Operational Amplifier Output Buffers) Parameter Symbol Value Unit Typ Max IDD - 0.2 0.5 mA Min. Analog Output Voltage 1 (AOX) VAOL1 VSS - VSS+0.1 V VDD=VCC, VSS=GND=0V Unloaded, Didital Data=#00 Min. Analog Output Voltage 2 (AOX) VAOL2 VSS-0.2 VSS VSS+0.2 V VDD=VCC=5.0V, VSS=GND=0V IAL=+500µA, Digital Data=#00 Min. Analog Output Voltage 3 (AOX) VAOL3 VSS - VSS+0.2 V VDD=VCC=5.0V, VSS=GND=0V IAH=+500µA, Digital Data=#00 Min. Analog Output Voltage 4 (AOX) VAOL4 VSS-0.3 VSS VSS+0.3 V VDD=VCC=5.0V, VSS=GND=0V IAL=+1.0mA, Digital Data=#00 Min. Analog Output Voltage 5 (AOX) VAOL5 VSS - VSS+0.3 V VDD=VCC=5.0V, VSS=GND=0V IAH=+1.0mA, Digital Data=#00 Max. Analog Output Voltage 1 (AOX) VAOH1 VDD-0.1 - VDD V VDD=VCC, VSS=GND=0V Unloaded, Digital Data=#FF Max. Analog Output Voltage 2 (AOX) VAOH2 VDD-0.2 - VDD V VDD=VCC=5.0V, VSS=GND=0V IAL=+500µA, Digital Data=#FF Max. Analog Output Voltage 3 (AOX) VAOH3 VDD-0.2 VDD VDD+0.2 V VDD=VCC=5.0V, VSS=GND=0V IAH=+500µA, Digital Data=#FF Supply Current (VDD) ** ** : Excluding the supply current to the operational amplifier block 12 Condition Min Unloaded MB88346B Analog Block (D/A Converters with Operational Amplifier Output Buffers) - Continued Parameter Symbol Max. Analog Output Voltage 4 (AOX) Max. Analog Output Voltage 5 (AOX) Value Unit Condition Min Typ Max VAOH4 VDD-0.3 - VDD V VDD=VCC=5V, VSS=GND=0V, IAL=+1.0mA, Digital Data=#FF VAOH5 VDD-0.3 VDD VDD+0.3 V VDD=VCC=5V, VSS=GND=0V, IAH=+1.0mA, Digital Data=#FF Resolution (AOX) Res - 8 - bit Monotonicity Differential Error* (AOX) DE -1.0 0 +1.0 LSB Unloaded, VDD≤VCC-0.1V, VSS≥0.1V Nonlinearity Error** (AOX) LE -1.5 0 +1.5 LSB Unloaded, VDD≤VCC-0.1V, VSS≥0.1V, See Figure 8. * : The difference from the ideal increment value when the digital data is increased by 1 bit. ** : The difference between the input-output curve for the straight line (ideal line) that connects the output voltage of the channel when #00 is set, and the output voltage when #FF is set. Figure 8 Definition of Nonlinearity Error Analog output voltage End point line VAOH* Nonlinearity error VAOL** Digita data #00 * : VAOH is not always equal to V DD. ** : VAOL is not always equal to VSS. #FF 13 MB88346B ■ AC CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Value Symbol Min Max Unit Condition Clock Low Time tCLK 200 - ns Clock High Time tCKH 200 - ns Clock Rise Time tCr - 200 ns Clock Fall Time tCf - 200 ns Data Setup Time tDCH 30 - ns Data Hold Time tCHD 60 - ns Load Strobe High Time tLDH 100 - ns Load Strobe Setup Time tCHL 200 - ns Load Strobe Hold Time tLDC 100 - ns DAC Output Settling Time tLDD - 20 µs *RAL = 10 kΩ , CAL = 50 pF Data Output Delay Time tDO 70 350 ns **CL = 20 pF (Min.), 100 pF (Max.) Figure 9 AC Test Conditions • DAC Output Settling Time Device Under Test Test Point RAL * 14 • Data Output Delay Time CAL * Device Under Test Test Point CL ** MB88346B Figure 10 Input/Output Timing tCKH tcr 0.8VCC 0.2VCC 0.8VCC CLK 0.2VCC tcf 0.2VCC 0.2VCC tCKL DI 0.8VCC 0.2VCC tLDC 0.8VCC 0.2VCC tDCH tCHD tLDH tCHL 0.8VCC 0.2VCC 0.8VCC 0.2VCC LD tLDD AOx 0.9VCC 0.1VCC Previous Data New Data Valid tDO DO Previous Data 0.8VCC 0.2VCC New Data Valid 15 MB88346B Figure 11 Analog Output Voltage Range R-2R Ladder Output (D/A Converter Output) VDD Operational Amplifier Output (Buffer Output) VCC VAOH = VCC AOX Output Range (Linear Range) VSS Notes: 16 VDD=VCC VSS=GND GND VAOL = GND MB88346B PACKAGE DIMENSIONS MB88346B-P ■ 20 pin, Plastic DIP (DIP-20P-M02) +0.20 24.64 –0.30 .970 +.008 –.012 INDEX-1 6.20±0.25 (.244±.010) INDEX-2 0.51(.020)MIN 4.36(.172)MAX 0.25±0.05 (.010±.002) 3.00(.118)MIN 0.46±0.08 (.018±.003) +0.30 0.86 –0 +.012 .034 –0 1.27(.050) MAX C 1994 FUJITSU LIMITED D20003S-3C-4 +0.30 1.27 –0 +.012 .050 –0 2.54(.100) TYP 7.62(.300) TYP 15˚MAX Dimensions in mm(inches). 17 MB88346B MB88346B-PF 20 pin, Plastic SOP (FPT 20P-M01) 2.25(.089)MAX +0.25 +.010 12.70 –0.20 .500 –.008 0.05(.002)MIN (STAND OFF) 5.30±0.30 (.209±.012) INDEX 1.27(.050) TYP 0.45±0.10 (.018±.004) +0.40 6.80 –0.20 +.016 .268 –.008 7.80±0.40 (.307±.016) +0.05 Ø0.13(.005) M 0.15 –0.02 +.002 .006 –.001 0.50±0.20 (.020±.008) Details of "A" part 0.20(.008) "A" 0.10(.004) 11.43(.450)REF 0.50(.020) 0.18(.007)MAX 0.68(.027)MAX C 18 1994 FUJITSU LIMITED F20003S-5C-4 Dimensions in mm(inches). MB88346B MB88346B-PFV 20 pin, Plastic SSOP (FPT-20P-M03) +0.20 * 6.50±0.10(.256±.004) 1.25 –0.10 +.008 .049 –.004 0.10(.004) INDEX *4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) 0.65±0.12 (.0256±.0047) 5.85(.230)REF C 1994 FUJITSU LIMITED F20012S-2C-4 +0.10 0.22 –0.05 +.004 .009 –.002 "A" 5.40(.213) NOM +0.05 0.15 –0.02 +.002 .006 –.001 Details of "A" part 0.10±0.10(.004±.004) (STAND OFF) 0 10˚ 0.50±0.20 (.020±.008) Dimensions in mm(inches). 19 MB88346B FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9803 FUJITSU LIMITED Printed in Japan 20 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. 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