FUJITSU MB90T673

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13602-5E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90670/675 Series
MB90671/672/673/T673/P673 (MB90670 Series)
MB90676/677/678/T678/P678 (MB90675 Series)
■ DESCRIPTION
The MB90670/675 series is a member of 16-bit proprietary single-chip microcontroller F2MC*1-16L family designed
to be combined with an ASIC (Application Specific IC) core. The MB90670/675 series is a high-performance
general-purpose 16-bit microcontroller for high-speed real-time processing in various industrial equipment, OA
equipment, and process control.
The instruction set of F2MC-16L CPU core inherits AT architecture of F2MC-8 family with additional instruction
sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data
(32-bit).
The MB90670/675 series has peripheral resources of UART0, UART1(SCI), an 8/10-bit A/D converter, an
8/16-bit PPG timer, a 16-bit reload timer, a 24-bit free run timer, an output compare (OCU), an input capture (ICU),
DTP/external interrupt circuit, an I2C*2 interface (in MB90675 series only). Embedded peripheral resources
performs data transmission with an intelligent I/O service function without the intervention of the CPU, enabling
real-time control in various applications.
*1: F2MC stands for FUJITSU Flexible Microcontroller.
*2: Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as
defined by Philips.
■ PACKAGES
80-pin Plastic LQFP
80-pin Plastic QFP
100-pin Plastic LQFP
100-pin Plastic QFP
(FPT-80P-M05)
(FPT-80P-M06)
(FPT-100P-M05)
(FPT-100P-M06)
MB90670/675 Series
■ FEATURES
• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at
Vcc of 5.0 V)
• CPU addressing space of 16 Mbytes
Internal addressing of 24-bit
External accessing can be performed by selecting 8/16-bit bus width (external bus mode)
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
High code efficiency
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Enhanced execution speed
4-byte instruction queue
• Enhanced interrupt function
8 levels, 32 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS)
• Low-power consumption (standby) mode
Sleep mode (mode in which CPU operating clock is stopped)
Timebase timer mode (mode in which other than oscillation and timebase timer are stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware standby mode
• Process
CMOS technology
• I/O port
MB90670 series: Maximum of 65 ports
MB90675 series: Maximum of 84 ports
• Timer
Timebase timer/watchdog timer: 1 channel
8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel
16-bit reload timer: 2 channels
24-bit free run timer: 1 channel
• Input capture (ICU)
Generates an interrupt request by latching a 24-bit free run timer counter value upon detection of an edge
input to the pin.
• Output compare (OCU)
Generates an interrupt request and reverse the output level upon detection of a match between the 24-bit free
run timer counter value and the compare setting value.
• I2C interface (in MB90675 series only)
• Serial I/O port for supporting Inter IC BUS
(Continued)
2
MB90670/675 Series
(Continued)
• UART0
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used.
• UART1 (SCI)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized serial transmission (I/O extended serial) can be selectively used.
• DTP/external interrupt circuit (4 channels)
A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered
by an external input.
• Wake-up interrupt
Receives external interrupt requests and generates an interrupt request upon an “L” level input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8-bit or 10-bit resolution can be selectively used.
Starting by an external trigger input.
3
MB90670/675 Series
■ PRODUCT LINEUP
• MB90670 series
Part number
Item
MB90671
Classification
MB90672
16 Kbytes
32 Kbytes
RAM size
640 bytes
1.64 Kbytes
Ports
MB90T673
External ROM
product
Mask ROM products
ROM size
CPU functions
MB90673
48 Kbytes
External ROM
MB90P673
One-time
PROM
product
48 Kbytes
2 Kbytes
Number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock of 16 MHz)
Interrupt processing time: 1.5 µs (at machine clock of 16 MHz, minimum value)
General-purpose I/O ports (CMOS output): 57
General-purpose I/O ports (N-ch open-drain output): 8
Total: 65
UART0
Clock synchronized transmission (500 Kbps to 2 Mbps)
Clock asynchronized transmission (4800 Kbps to 500 Kbps)
Transmission can be performed by bi-directional serial transmission or by master/slave
connection.
UART1 (SCI)
Clock synchronized transmission (500 Kbps to 2 Mbps)
Clock asynchronized transmission (2400 Kbps to 62500 bps)
Transmission can be performed by bi-directional serial transmission or by master/slave
connection.
8/10-bit A/D converter
Conversion precision: 10-bit or 8-bit selectable
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timer
Number of channels: 2
8-bit or 16-bit PPG operation
A Pulse wave of given intervals and given duty ratios can be output.
Pulse cycle: 125 ns to 16.78 s (at oscillation of 4 MHz, machine clock of 16 MHz)
16-bit reload timer
Number of channels: 2
16-bit reload timer operation
Interval: 125 ns to 131 ms (at machine clock of 16 MHz)
External event count can be performed.
24-bit free run timer
Number of channel :1
Overflow interrupts or intermediate bit interrupts may be generated.
Output compare unit
(OCU)
Number of channels: 8
Pin input factor: A match signal of compare register
(Continued)
4
MB90670/675 Series
(Continued)
Part number
Item
Input capture unit (ICU)
DTP/external interrupt circuit
Wake-up interrupt
MB90671
MB90672
MB90673
MB90T673
MB90P673
Number of channels: 4
Rewriting a register value upon a pin input (rising, falling, or both edges)
Number of inputs: 4
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
Number of inputs: 8
Started by an “L” level input.
Delayed interrupt generation An interrupt generation module for switching tasks used in real-time operating sysmodule
tems.
I2C interface
None
Timebase timer
18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(at oscillation of 4 MHz)
Watchdog timer
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Low-power consumption
(standby) mode
Process
Operating voltage*
Sleep/stop/CPU intermittent operation/timebase timer/hardware stand-by
CMOS
2.7 V to 5.5 V
*: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
5
MB90670/675 Series
• MB90675 series
Part number
Item
MB90676
Classification
MB90677
32 Kbytes
48 Kbytes
RAM size
1.64 Kbytes
2 Kbytes
Ports
The number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
MB90T678
MB90P678
One-time
External ROM
PROM
product
product
Mask ROM products
ROM size
CPU functions
MB90678
64 Kbytes
None
MB90V670
Evaluation
product
64 Kbytes
3 Kbytes
—
4 Kbytes
340
8 bits, 16 bits
1 byte to 7 bytes
1 bit, 8 bits, 16 bits
62.5 ns (at machine clock of 16 MHz)
1.5 µs (at machine clock of 16 MHz, minimum value)
General-purpose I/O ports (CMOS output): 74
General-purpose I/O ports (N-ch open-drain output): 10
Total: 84
UART0
Clock synchronized transmission (500 Kbps to 2 Mbps)
Clock asynchronized transmission (4800 Kbps to 500 Kbps)
Transmission can be performed by bi-directional serial transmission or by master/slave
connection.
UART1 (SCI)
Clock synchronized transmission (500 Kbps to 2 Mbps)
Clock asynchronized transmission (2400 Kbps to 62500 bps)
Transmission can be performed by bi-directional serial transmission or by master/slave
connection.
8/10-bit A/D converter
Conversion precision: 10-bit or 8-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timer
Number of channels: 2
PPG operation of 8-bit or 16-bit
Pulse of given intervals and given duty ratios can be output
Pulse interval 125 ns to 16.78 s (at oscillation of 4 MHz, machine clock of 16 MHz)
16-bit reload timer
Number of channels: 2
16-bit reload timer operation
Interval: 125 ns to 131 ms (at machine clock of 16 MHz)
External event count can be performed.
24-bit free run timer
Output compare
(OCU)
Number of channel :1
Overflow interrupts or intermediate bit interrupts may be generated.
Number of channels: 8
Pin input factor: a match signal of compare register
(Continued)
6
MB90670/675 Series
(Continued)
Part number
Item
MB90676
MB90677
MB90678
MB90T678
MB90P678
MB90V670
Input capture (ICU)
Number of channels: 4
Rewriting a register value upon a pin input (rising, falling, or both edges)
DTP/external interrupt circuit
Number of inputs: 4
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
Wake-up interrupt
Number of inputs: 8
Started by an “L” level input.
Delayed interrupt
generation module
An interrupt generation module for switching tasks used in realtime operating systems.
I2C interface
Serial I/O port for supporting Inter IC BUS
Timebase timer
18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(at oscillation of 4 MHz)
Watchdog timer
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Low-power consumption (standby) mode
Sleep/stop/CPU intermittent operation/timebase timer/hardware stand-by
Process
CMOS
Power supply voltage for operation*
2.7 V to 5.5 V
*: Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARACTERISTICS.”)
Assurance for the MB90V670 is given only for operation with a tool at a power voltage of 2.7 V to 5.5 V, an
operating temperature of 0°C to 70°C, and an operating frequency of 1.5 MHz to 16 MHz.
■ PACKAGE AND CORRESPONDING PRODUCTS
MB90676
MB90677
MB90678
MB90T678
MB90P678
MB90V670
FPT-80P-M05
×
×
×
FPT-80P-M06
×
×
×
Package
MB90671
MB90672
MB90673
MB90T673
MB90P673
FPT-100P-M05
×
×
×
FPT-100P-M06
×
×
×
: Available
× : Not available
Note: For more information about each package, see section “■ PACKAGE DIMENSIONS.”
7
MB90670/675 Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
In evaluation with an evaluation product, note the difference between the evaluation chip and the chip actually
used. The following items must be taken into consideration.
• The MB90V670 does not have an internal ROM, however, operations equivalent to chips with an internal ROM
can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the
development tool.
• In the MB90V670, images from FF4400H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to
mapped to bank FEH and FFH only. (This setting can be changed by configuring the development tool.)
• In the MB90678/MB90P678, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to
FF3FFFH to bank FF only.
2. Mask Options
Functions selected by optional settings and methods for setting the options are dependent on the product types.
Refer to “■ Mask Options” for detailed information.
Note that mask option is fixed in MB90V670 series.
8
MB90670/675 Series
■ PIN ASSIGNMENTS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P17/AD15/WI7
P16/AD14/WI6
P15/AD13/WI5
P14/AD12/WI4
P13/AD11/WI3
P12/AD10/WI2
P11/AD09/WI1
P10/AD08/WI0
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RST
P80/PPG1
P77/DOT7
P76/DOT6
P75/DOT5
P74/DOT4
P73/DOT3
P72/DOT2
P71/DOT1
P70/DOT0
P67/ASR3
P66/ASR2
P65/ASR1
P64/ASR0
P63/INT3
P62/INT2
P61/INT1
P60/INT0
HST
MD2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P43/SIN1
P44/SOT1
P45/SCK1
P46/PPG0
P47/ATG
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
VSS
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
MD0
MD1
P20/A16
P21/A17
P22/A18
P23/A19
P24/TIN0
P25/TIN1
P26/TOT0
P27/TOT1
VSS
P30/ALE
P31/RD
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
(FPT-80P-M05)
(Continued)
9
MB90670/675 Series
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P15/AD13/WI5
P14/AD12/WI4
P13/AD11/WI3
P12/AD10/WI2
P11/AD09/WI1
P10/AD08/WI0
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
X0
VSS
RST
P80/PPG1
P77/DOT7
P76/DOT6
P75/DOT5
P74/DOT4
P73/DOT3
P72/DOT2
P71/DOT1
P70/DOT0
P67/ASR3
P66/ASR2
P65/ASR1
P64/ASR0
P63/INT3
P62/INT2
P61/INT1
P60/INT0
HST
MD2
MD1
MD0
P45/SCK1
P46/PPG0
P47/ATG
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
VSS
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P16/AD14/WI6
P17/AD15/WI7
P20/A16
P21/A17
P22/A18
P23/A19
P24/TIN0
P25/TIN1
P26/TOT0
P27/TOT1
VSS
P30/ALE
P31/RD
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT10
(FPT-80P-M06)
(Continued)
10
MB90670/675 Series
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P21/A17
P20/A16
P17/AD15/WI7
P16/AD14/WI6
P15/AD13/WI5
P14/AD12/WI4
P13/AD11/WI3
P12/AD10/WI2
P11/AD09/WI1
P10/AD08/WI0
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
PB2
PB1
PB 0
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RST
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
P77/DOT7
P76/DOT6
P75/DOT5
P74/DOT4
P73/DOT3
P72/DOT2
P71/DOT1
P70/DOT0
P67/ASR3
P66/ASR2
P65/ASR1
P64/ASR0
P63/INT3
P62/INT2
P61/INT1
P60/INT0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P81
P82
P83
P84
P85
P86
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
VSS
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P90/SDA
P91/SCL
MD0
MD1
MD2
HST
P22/A18
P23/A19
P24/TIN0
P25/TIN1
P26/TOT0
P27/TOT1
P30/ALE
P31/RD
VSS
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC
P45/SCK1
P46/PPG0
P47/ATG
P80/PPG1
(FPT-100P-M05)
(Continued)
11
MB90670/675 Series
(Continued)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P17/AD15/WI7
P16/AD14/WI6
P15/AD13/WI5
P14/AD12/WI4
P13/AD11/WI3
P12/AD10/WI2
P11/AD09/WI1
P10/AD08/WI0
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
(Top view)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P84
P85
P86
AVCC
AVRH
AVRL
AVSS
P50/AN0
P51/AN1
VSS
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P90/SDA
P91/SCL
MD0
MD1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P20/A16
P21/A17
P22/A18
P23/A19
P24/TIN0
P25/TIN1
P26/TOT0
P27/TOT1
P30/ALE
P31/RD
VSS
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC
P45/SCK1
P46/PPG0
P47/ATG
P80/PPG1
P81
P82
P83
(FPT-100P-M06)
12
PB2
PB1
PB0
RST
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
P77/DOT7
P76/DOT6
P75/DOT5
P74/DOT4
P73/DOT3
P72/DOT2
P71/DOT1
P70/DOT0
P67/ASR3
P66/ASR2
P65/ASR1
P64/ASR0
P63/INT3
P62/INT2
P61/INT1
P60/INT0
HST
MD2
MB90670/675 Series
■ PIN DESCRIPTION
Pin no.
Pin name Circuit type
LQFP
-80*1
QFP
-80*2
LQFP
-100*3
QFP
-100*4
62
64
80
82
X0
63
65
81
83
X1
39 to 41 41 to 43 47 to 49 49 to 51
MD0 to
MD2
Function
A
Crystal oscillator pins
(Oscillation)
F
(CMOS)
Input pins for selecting operation modes
Connect directly to VCC or VSS.
60
62
75
77
RST
H
External reset request input
(CMOS/H)
42
44
50
52
HST
G
Hardware standby input pin
(CMOS/H)
General-purpose I/O port
This function is valid in the single-chip mode.
P00 to P07
65 to 72 67 to 74 83 to 90 85 to 92
73 to 78, 75 to 80, 91 to 96, 93 to 98,
79, 80
1, 2
97, 98 99, 100
1, 2, 3, 4 3, 4, 5, 6
AD00 to
AD07
B
(CMOS)
I/O pins for the lower 8-bit of the external address data bus
This function is valid in the mode where the external bus is valid.
P10 to P15,
P16, P17
General-purpose I/O port
This function is valid in the single-chip mode.
AD08 to
AD13,
AD14,
AD15
I/O pins for the upper 8-bit of the external address data bus
This function is valid in the mode where the external bus is valid.
B
(CMOS)
WI0 to WI5,
WI6, WI7
I/O pins for wake-up interrupts
This function is valid in the single-chip mode.
Because the input of the DTP/external interrupt circuit is used as required when the DTP/
external interrupt circuit is enabled, and it is
necessary to stop outputs by other functions
unless such outputs are made intentionally.
P20, P21,
P22, P23
General-purpose I/O port
This function becomes valid in the single-chip
mode or the external address output control
register is set to select a port.
99, 100,
1, 2, 3, 4
1, 2
B
(CMOS)
A16, A17,
A18, 19
Output pins for the external address bus of A16
to A19
This function is valid in the mode where the external bus is valid and the upper address control register is set to select an address.
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
13
MB90670/675 Series
Pin no.
LQFP
-80*1
QFP
-80*2
LQFP
-100*3
QFP
-100*4
Pin name Circuit type
General-purpose I/O port
This function is always valid.
P24, P25
5, 6
7, 8
3, 4
5, 6
TIN0, TIN1
Event input pins of 16-bit reload timer 0 and 1
E
(CMOS/H) Because this input is used as required when the
16-bit reload timer is performing input operations,
and it is necessary to stop outputs by other functions unless such outputs are made intentionally.
General-purpose I/O port
This function is valid when outputs from 16-bit reload timer 0 and 1 are disabled.
P26, P27
7, 8
9, 10
5, 6
7, 8
TOT0,
TOT1
E
(CMOS/H) Output pins for 16-bit reload timer 0 and 1
This function is valid when output from 16-bit reload timer 0 and 1 are enabled.
P30
10
12
7
9
ALE
B
(CMOS)
P31
11
13
8
10
RD
B
(CMOS)
WRL
14
10
12
B
(CMOS)
WR
P33
13
15
11
B
(CMOS)
13
WRH
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
14
General-purpose I/O port
This function is valid in the single-chip mode.
Address latch enable output pin
This function is valid in the mode where the external bus is valid.
General-purpose I/O port
This function is valid in the single-chip mode.
Read strobe output pin for the data bus
This function is valid in the mode where the external bus is valid.
General-purpose I/O port
This function is valid in the single-chip mode or
WRL/WR pin output is disabled.
P32
12
Function
Write strobe output pin for the data bus
This function is valid when WRL/WR pin output is
enabled in the mode where external bus is valid.
WRL is used for holding the lower 8-bit for write
strobe in 16-bit access operations, while WR is
used for holding 8-bit data for write strobe in
8-bit access operations.
General-purpose I/O port
This function is valid in the single-chip mode, in the
external bus 8-bit mode, or WRH pin output is disabled.
Write strobe output pin for the upper 8-bit of the
data bus
This function is valid when the external bus 16-bit
mode is selected in the mode where the external
bus is valid, and WRH output pin is enabled.
(Continued)
MB90670/675 Series
Pin no.
LQFP
-80*1
QFP
-80*2
LQFP
-100*3
QFP
-100*4
Pin name
Circuit type
P34
14
15
16
17
18
16
17
18
19
20
12
13
14
15
16
B
(CMOS)
14
HRQ
P35
General-purpose I/O port
This function is valid when both the single-chip
mode and the hold function are disabled.
B
(CMOS)
15
HAK
Hold acknowledge output pin
This function is valid in the mode where the external bus is valid or when the hold function is enabled.
P36
General-purpose I/O port
This function is valid when both the single-chip
mode and the external ready function are disabled.
B
(CMOS)
16
RDY
Ready input pin
This function is valid when the external ready function is enabled in the mode where the external bus
is valid.
P37
General-purpose I/O port
This function is valid in the single-chip mode or
when the CLK output is disabled.
B
(CMOS)
17
CLK
CLK output pin
This function is valid when CLK output is disabled
in the mode where the external bus is valid.
P40
General-purpose I/O port
This function is always valid.
18
P41
21
17
General-purpose I/O port
This function is valid when both the single-chip
mode and the hold function are disabled.
Hold request input pin
This function is valid in the mode where the external bus is valid or when the hold function is enabled.
SIN0
19
Function
19
SOT0
Serial data input pin of UART0
E
(CMOS/H) Because this input is used as required when
UART0 is performing input operations, and it is
necessary to stop outputs by other functions unless such outputs are made intentionally.
General-purpose I/O port
This function is valid when serial data output from
UART0 is disabled.
E
(CMOS/H) Serial data output pin of UART0
This function is valid when serial data output from
UART0 is enabled.
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
15
MB90670/675 Series
Pin no.
LQFP
-80*1
QFP
-80*2
LQFP
-100*3
QFP
-100*4
Pin name
P42
20
22
18
20
SCK0
P43
21
23
19
21
SIN1
P44
22
24
20
22
SOT1
P45
23
25
22
24
SCK1
P46
24
26
23
25
PPG0
Circuit type
Function
General-purpose I/O port
This function is valid when clock output from
UART0 is disabled.
Clock I/O pin of UART0
E
This function is valid when clock output from
(CMOS/H) UART0 is enabled.
Because this input is used as required when
UART0 is performing input operations, and it is
necessary to stop outputs by other functions unless such outputs are made intentionally.
General-purpose I/O port
This function is always valid.
Serial data input pin of UART1 (SCI)
E
(CMOS/H) Because this input is used as required when
UART1 (SCI) is performing input operations, and it
is necessary to stop outputs by other functions unless such outputs are made intentionally.
General-purpose I/O port
This function is valid when serial data output from
UART1 (SCI) is disabled.
E
(CMOS/H) Serial data output pin of UART1 (SCI)
This function is valid when serial data output from
UART1 (SCI) is enabled.
General-purpose I/O port
This function is valid when clock output from
UART1 (SCI) is disabled.
Clock I/O pin of UART1 (SCI)
E
This function is valid when clock output from
(CMOS/H) UART1 (SCI) is enabled.
Because this input is used as required when
UART1 (SCI) is performing input operations, and it
is necessary to stop outputs by other functions unless such outputs are made intentionally.
General-purpose I/O port
This function is valid when waveform output from
8/16-bit PPG timer 0 is disabled.
E
(CMOS/H) Output pin of 8/16-bit PPG timer 0
This function is valid when waveform output from
8/16-bit PPG timer 0 is enabled.
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
16
MB90670/675 Series
Pin no.
LQFP
-80*1
QFP
-80*2
LQFP
-100*3
QFP
-100*4
Pin name
P47
25
27
24
26
ATG
P50, P51,
P52, P53,
30, 31, 32, 33, 36, 37, 38, 39, P54 to P57
33, 34, 35, 36, 38, 39, 40, 41,
35 to 38 37 to 40 41 to 44 43 to 46 AN0, AN1,
AN2, AN3,
AN4 to AN7
P60 to P63
43 to 46 45 to 48 51 to 54 53 to 56
INT0 to
INT3
P64 to P67
47 to 50 49 to 52 55 to 58 57 to 60
ASR0 to
ASR3
P70 to P77
51 to 58 53 to 60 59 to 66 61 to 68
DOT0 to
DOT7
Circuit type
Function
General-purpose I/O port
This function is always valid.
Trigger input pin of the 8/10-bit A/D converter
E
Because this input is used as required when the
(CMOS/H) 8/10-bit A/D converter is performing input operations, and it is necessary to stop outputs by other
functions unless such outputs are made intentionally.
I/O port of an open-drain type
The input function is valid when the analog input
enable register is set to select a port.
C
(CMOS/H) Analog input pins of the 8/10-bit A/D converter
This function is valid when the analog input enable register is set to select AD.
General-purpose I/O port
This function is always valid.
Request input pins of the DTP/external interrupt
circuit
E
(CMOS/H) Because this input is used as required when the
DTP/external interrupt circuit is performing input
operations, and it is necessary to stop outputs
from other functions unless such outputs are
made intentionally.
General-purpose I/O port
This function is always valid.
Sample data input pins for ICU0 to ICU3
E
Because this input is used as required when the
(CMOS/H) input capture (ICU) is performing input operations, and it is necessary to stop outputs from other functions unless such outputs are made
intentionally.
General-purpose I/O port
This function is valid when waveform output from
the output compare (OCU) is disabled.
E
(CMOS/H) Waveform output pins of OCU0 and OCU1
This function is valid when waveform output from
the output compare (OCU) is enabled and output
from the port is selected.
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
17
MB90670/675 Series
(Continued)
Pin no.
LQFP
-80*1
QFP
-80*2
LQFP
-100*3
QFP
-100*4
Pin name
Circuit type
General-purpose I/O port
This function is valid when waveform output from
8/16-bit PPG timer 1 is disabled.
P80
59
61
25
27
PPG1
—
—
26 to 31 28 to 33 P81 to P86
E
(CMOS/H) Output pin of 8/16-bit PPG timer 1
This function is valid when waveform output from
8/16-bit PPG timer 1 is enabled.
E
General-purpose I/O port
(CMOS/H) This function is always valid.
I/O port of an open-drain type
This function is always valid.
P90
—
—
45
47
SDA
I/O pin of the I2C interface
D
This function is valid when operation of the I2C
(NMOS/H) interface is enabled.
Hold the port output in the high-impedance status (PDR = 1) when the I2C interface is in operation.
I/O port of an open-drain type
This function is always valid.
P91
—
—
46
48
SCL
Clock I/O pin of the I2C interface
D
This function is valid when operation of the I2C
(NMOS/H) interface is enabled.
Hold the port output in the high-impedance status (PDR = 1) when the I2C interface is in operation.
—
—
67 to 74 69 to 76 PA0 to PA7
E
General-purpose I/O port
(CMOS/H) This function is always valid.
—
—
76 to 78 78 to 80 PB0 to PB2
E
General-purpose I/O port
(CMOS/H) This function is always valid.
64
66
21, 82
23, 84 VCC
Power
supply
Power supply to the digital circuit
9, 32,
61
11, 34,
63
9, 40,
79
11, 42,
VSS
81
Power
supply
Ground level of the digital circuit
26
28
32
34
AVCC
Power
supply
Power supply to the analog circuit
Make sure to turn on/turn off this power supply
with a voltage exceeding AVCC applied to VCC.
27
29
33
35
AVRH
Power
supply
Reference voltage input to the analog circuit
Make sure to turn on/turn off this power supply
with a voltage exceeding AVRH applied to AVCC.
28
30
34
36
AVRL
Power
supply
Reference voltage input to the analog circuit
29
31
35
37
AVSS
Power
supply
Ground level of the analog circuit
*1: FPT-80P-M05
*2: FPT-80P-M06
*3: FPT-100P-M05
*4: FPT-100P-M06
18
Function
MB90670/675 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
P-ch
Clock input
N-ch
• External clock frequency 3 MHz to 32
MHz
• Oscillation feedback resistor approx.
1MΩ
X0
A
Standby control signal
R
P-ch
N-ch
B
Digital output
• CMOS level input/output
(with standby control)
• Pull-up option selectable
(with standby control)
• No pull-up resistor in the MB90V670
Digital output
Digital input
Standby control signal
• N-ch open-drain output
• CMOS level hystheresis input
(with A/D control)
Digital output
C
A/D input
Digital input
A/D disable
• NMOS open-drain output
• CMOS level hysteresis input
(with standby control)
P-ch
D
N-ch
Digital output
Digital input
Standby control signal
(Continued)
19
MB90670/675 Series
(Continued)
Type
Circuit
Remarks
R
P-ch
N-ch
E
Digital output
Digital output
• CMOS level output
• CMOS level hysteresis input
(with standby control)
• Pull-up option selectable
(with standby control)
• No pull-up resistor in the MB90V670
Digital input
Standby control signal
• CMOS level input/output
(without standby control)
• Pull-up/pull-down option selectable
(without stand-by control)
• In mask ROM versions, MD2 pin is fixed
to pull-down resistor, and optionally selectable the resistor in other pins.
• The MB90V670 has no pull-up/pulldown resistors.
R
P-ch
F
N-ch
R
Digital input
• CMOS level hysteresis input
(without standby control)
P-ch
N-ch
G
Digital input
• CMOS level hysteresis input
(without standby control)
• Pull-up option selectable
(without standby control)
• No pull-up resistor in the MB90V670
R
P-ch
H
N-ch
Digital input
20
MB90670/675 Series
■ HANDLING DEVICES
1. Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up).
In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is
applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS.
When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal
break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating.
In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH) and analog
input voltages not exceed the digital voltage (VCC).
2. Connection of Unused Pins
Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up
or a pull-down resistor.
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
• Using external clock
X0
Open
X1
MB90670/675 series
4. Power Supply Pins
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to
lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
5. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.
6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after
turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously
is acceptable).
21
MB90670/675 Series
7. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
8. “MOV @AL, AH”, “MOVW @AL, AH” Instructions
When the above instruction is performed to I/O space, an unnecessary writing operation (#FF, #FFFF) may be
performed in the internal bus.
Use the compiler function for inserting an NOP instruction before the above instructions to avoid the writing
operation.
Accessing RAM space with the above instruction does not cause any problem.
9. Initialization
In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers,
turning on the power again.
10. Caution on operations during PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
22
MB90670/675 Series
■ PROGRAMMING TO THE ONE-TIME PROM ON THE MB90P673/P678
The MB90P673 and MB90P678 has a PROM mode for emulation operation of the MBM27C1000/1000A, to
which writing codes by a general-purpose ROM writer can be done via a dedicated adapter. Please note that
the device is not compatible with the electronic signature (device ID code) mode.
1. Writing Sequence
The memory map for the PROM mode is shown as follows. Write option data to the option setting area according
by referring to “7. PROM Option Bit Map”.
PROM mode
Normal operation mode
FFFFFFH
1FFFFFH
Program area
(PROM)
Program area
(PROM)
Address*1
Address*2
010000H
ROM image
004000H
0002CH
000000H
00000H
Option
setting area
Address*1
Address*2
Number of bytes
MB90P673
14000H
FF4000H
48 Kbytes
MB90P678
10000H
FF0000H
64 Kbytes
Type
Note: The ROM image size for bank 00 is 48 Kbytes (ROM image for between FF4000H to FFFFFFH).
Write data to the one-time PROM microcontrollers according to the following sequence.
(1) Set the PROM programer to select the MBM27C1000/1000A.
(2) Load the program data to the ROM programer address *1 to 1FFFFH. To select a PROM option, load the
option data from 00000H to 0002CH referring to “7. PROM Option Bit Map”.
(3) Set the chip to the adapter socket and load the socket to the ROM programer. Make sure that the device
and adapter socket are properly oriented.
(4) Program from 00000H to 1FFFFH.
Notes:
• In mask-ROM products, there is no PROM mode and it is impossible to read data by a ROM programer.
• Contact sales personnel when purchasing a ROM programer.
2. Program Mode
In the MB90P673/P678, all the bits are set to “1” upon shipping from FUJITSU or erasing operation. To write
data, set desired bit selectively to “0”. However it is impossible to write electronically to the bits.
23
MB90670/675 Series
3. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
One-time PROM microcomputer program.
Program, verify
Aging
+150°C, 48 h
Data verification
Assembly
4. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked One-time PROM microcomputer, due to its
nature. For this reason, a programming yield of 100% cannot be assured at all times.
5. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
MB90P673PF MB90P673PFV MB90P678PF MB90P678PFV
Recommended programmer manufacturer
and programmer name
Part no.
Package
QFP-80
LQFP-80
QFP-100
LQFP-100
Compatible socket adapter
Sun Hayato Co., Ltd.
ROM-80QF32DP-16L
ROM-80SQF32DP-16L
ROM-100QF32DP-16L
ROM-100SQF32DP-16L
1890A
—
—
—
Recommended
1891
—
—
—
Recommended
1930
—
—
—
Recommended
UNISITE
—
—
—
Recommended
3900
—
—
—
Recommended
2900
—
—
—
Recommended
Minato Electronics Inc.
Data I/O Co., Ltd.
Inquiry: San Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Minato Electronics Inc.: TEL: USA (1)-916-348-6066
JAPAN (81)-45-591-5611
Data I/O Co., Ltd.: TEL: USA/ASIA (1)-206-881-6444
EUROPE (49)-8-985-8580
24
MB90670/675 Series
6. Pin Assignment for EPROM Mode
• MBM27C1000/1000A pin compatible
MBM27C1000/1000A
Pin no.
Pin name
MB90P673/MB90P678
Pin no.
Pin name
MBM27C1000/1000A
Pin no.
MB90P673/MB90P678
Pin name
Pin no.
Pin name
MD2
32
VCC
VCC
2
OE
P32
31
PGM
P33
3
A15
P17
30
N.C.
—
4
A12
P14
29
A14
P16
5
A07
P27
28
A13
P15
6
A06
P26
27
A08
P10
7
A05
P25
26
A09
8
A04
P24
25
A11
9
A03
P23
24
A16
10
A02
P22
23
A10
11
A01
P21
22
CE
12
A00
P20
21
D07
13
D00
P00
20
D06
14
D01
P01
19
D05
P05
15
D02
P02
18
D04
P04
16
GND
VSS
17
D03
P03
• Pin assignments for products not compatible
with MBM27C1000/1000A
Refer to pin assignments.
Pin no.
Pin name
Connect a pull-up resistor of 4.7 kΩ.
X1
OPEN
AVCC
AVRH
P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P86
P90
P91
PA0 to PA7
PB0 to PB2
P11
P13
P30
P12
P31
P07
P06
• Power supply, GND connected pin
processing
MD0
MD1
X0
Refer to pin assignments.
VPP
Refer to pin assignments.
1
Type
Power supply
GND
Pin no.
Refer to pin
assignments.
Refer to pin
assignments.
Pin name
HST
VCC
P34
P35
P36
RST
AVRL
AVSS
VSS
Connect a pull-up
resistor having
a resistance of
approximately
1 MΩ to each pin.
Note: Only MB90675 series has P81 to P86, P90, P91, PA0 to PA7, PB0 to PB2 pins.
25
MB90670/675 Series
7. PROM Option Bit Map
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
00000H
Vacancy
RST
Pull-up
1: No
0: Yes
00004H
P07
Pull-up
1: No
0: Yes
P06
Pull-up
1: No
0: Yes
P05
Pull-up
1: No
0: Yes
P04
Pull-up
1: No
0: Yes
P03
Pull-up
1: No
0: Yes
P02
Pull-up
1: No
0: Yes
P01
Pull-up
1: No
0: Yes
P00
Pull-up
1: No
0: Yes
00008H
P17
Pull-up
1: No
0: Yes
P16
Pull-up
1: No
0: Yes
P15
Pull-up
1: No
0: Yes
P14
Pull-up
1: No
0: Yes
P13
Pull-up
1: No
0: Yes
P12
Pull-up
1: No
0: Yes
P11
Pull-up
1: No
0: Yes
P10
Pull-up
1: No
0: Yes
0000CH
P27
Pull-up
1: No
0: Yes
P26
Pull-up
1: No
0: Yes
P25
Pull-up
1: No
0: Yes
P24
Pull-up
1: No
0: Yes
P23
Pull-up
1: No
0: Yes
P22
Pull-up
1: No
0: Yes
P21
Pull-up
1: No
0: Yes
P20
Pull-up
1: No
0: Yes
00010H
P37
Pull-up
1: No
0: Yes
P36
Pull-up
1: No
0: Yes
P35
Pull-up
1: No
0: Yes
P34
Pull-up
1: No
0: Yes
P33
Pull-up
1: No
0: Yes
P32
Pull-up
1: No
0: Yes
P31
Pull-up
1: No
0: Yes
P30
Pull-up
1: No
0: Yes
00014H
P47
Pull-up
1: No
0: Yes
P46
Pull-up
1: No
0: Yes
P45
Pull-up
1: No
0: Yes
P44
Pull-up
1: No
0: Yes
P43
Pull-up
1: No
0: Yes
P42
Pull-up
1: No
0: Yes
P41
Pull-up
1: No
0: Yes
P40
Pull-up
1: No
0: Yes
0001CH
P67
Pull-up
1: No
0: Yes
P66
Pull-up
1: No
0: Yes
P65
Pull-up
1: No
0: Yes
P64
Pull-up
1: No
0: Yes
P63
Pull-up
1: No
0: Yes
P62
Pull-up
1: No
0: Yes
P61
Pull-up
1: No
0: Yes
P60
Pull-up
1: No
0: Yes
00020H
P77
Pull-up
1: No
0: Yes
P76
Pull-up
1: No
0: Yes
P75
Pull-up
1: No
0: Yes
P74
Pull-up
1: No
0: Yes
P73
Pull-up
1: No
0: Yes
P72
Pull-up
1: No
0: Yes
P71
Pull-up
1: No
0: Yes
P70
Pull-up
1: No
0: Yes
00024H
Vacancy
P86
Pull-up
1: No
0: Yes
P85
Pull-up
1: No
0: Yes
P84
Pull-up
1: No
0: Yes
P83
Pull-up
1: No
0: Yes
P82
Pull-up
1: No
0: Yes
P81
Pull-up
1: No
0: Yes
P80
Pull-up
1: No
0: Yes
00028H
PA5
Pull-up
1: No
0: Yes
PA4
Pull-up
1: No
0: Yes
PA3
Pull-up
1: No
0: Yes
PA2
Pull-up
1: No
0: Yes
PA1
Pull-up
1: No
0: Yes
PA0
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
PB2
Pull-up
1: No
0: Yes
PB1
Pull-up
1: No
0: Yes
PB0
Pull-up
1: No
0: Yes
PA7
Pull-up
1: No
0: Yes
PA6
Pull-up
1: No
0: Yes
0002CH
Vacancy
Vacancy
Vacancy
MD1
Pull-up
1: No
0: Yes
MD1
Pull-down
1: No
0: Yes
MD0
Pull-up
1: No
0: Yes
MD0
Pull-down
1: No
0: Yes
Vacancy
Notes:
• Data “1” must be programed to the reserved bits and address other than listed above.
• Only MB90P678 has pull-up options for P81 to P86, PA0 to PA7, and PB0 to PB2 pins.
• Data “1” must be programed for the MB90P673.
26
bit 0
MB90670/675 Series
■ BLOCK DIAGRAM
F2MC–16L
CPU
Interrupt controller
Port 5
X0
X1
RST
HST
Clock control block
(including timebase timer)
P10/AD08/WI0 to
P17/AD15/WI7
8
8
8
8
P50/AN0 to
P57/AN7
AVCC
AVRH
AVRL
AVSS
8/10-bit
A/D converter
Wake-up
interrupt
P47/ATG
Port 0, 1
Port 4
4
P20/A16 to P23/A19
P30/ALE
P31/RD
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
External bus
interface
2
Internal data bus
P00/AD00 to
P07/AD07
16
8
10
Port 2, 3
P24/TIN0
16-bit
reload timer 0
P26/TOT0
UART0
P40/SIN0
P41/SOT0
P42/SCK0
UART1
(SCI)
P43/SIN1
P44/SOT1
P45/SCK1
16-bit PPG timer
8-bit
PPG timer 0
P46/PPG0
8-bit
PPG timer 1
P80/PPG1
6
P81 to P86
Port 8
Port 6
16-bit
reload timer 1
P25/TIN1
P27/TOT1
DTP/external
interrupt circuit
0 to 3
4
4
Input capture
(ICU)
4
4
P60/INT0 to
P63/INT3
Port 7
4 Output compare
P70/DOT0 to
P77/DOT7
P64/ASR0 to
P67/ASR3
8
4 Output compare
(unit 1)
24-bit
free run timer
8
Port A, B *
3
PA0 to PA7
PB0 to PB2
Port 9*
P90/SDA
RAM
2
P91/SCL
Other pins
VCC,VSS,
MD0 to MD2
I2C interface *
ROM
*Not included in the MB90670 series.
27
MB90670/675 Series
■ MEMORY MAP
FFFFFFH
Single-chip mode
Internal ROM
external bus mode
ROM area
ROM area
External ROM
external bus mode
*1
Address#1
100000H
External area
010000H
Address #2
ROM area
(image of
bank FF)
ROM area
(image of
bank FF)
004000H
002000H
Address #3
000100H
0000C0H
000000H
External area
External area
RAM Register
RAM Register
RAM Register
Peripheral
External area
Peripheral
External area
Peripheral
Part number
Address #1*2
Address #2 *2
Address #3 *2
MB90671
FFC000H
00C000H
000380H
MB90672
FF8000H
008000H
000780H
MB90673
FF4000H
004000H
000900H
—
—
000900H
MB90P673
FF4000H
004000H
000900H
MB90676
FF8000H
008000H
000780H
MB90677
FF4000H
004000H
000900H
MB90678
FF0000H
004000H
000D00H
MB90T673
MB90T678
—
—
000D00H
MB90P678
FF0000H
004000H
000D00H
: Internal access memory
: External access memory
: Inhibited area
*1: The same external memory is accessed for bank 0F, 1F, 2F through FF.
*2: Addresses #1, #2 and #3 are unique to the product type.
Notes:
• The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler
small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address,
enabling reference of the table on the ROM without stating “far”.
However, the ROM area of the MB90678/P678 exceeds 48 Kbytes, and for this reason, the image from FF4000H
to FFFFFFH is reflected on bank 00 and image from FF0000H to FF3FFFH bank FF only.
• In the MB90670/675 series, the upper 4-bit of the address are not output to the external bus. For this reason,
the maximum area accessible is 1 Mbyte. The same address is accessed through different banks in different
images.
For example, accessing “A00000H” and “B00000H” accesses the same address on the external bus.
• To prevent the memory or I/O from being accessed through images, and the data from being destroyed, it is
recommended to limit number of banks to a maximum of 16 so that the banks are mapped without interfering
each other. Caution must be also taken when masking the upper address with the external address output
control register (HACR).
28
MB90670/675 Series
■ F2MC-16L CPU PROGRAMMING MODEL
(1) Dedicated Registers
: Accumulator (A)
AH
AL
Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register.
: User stack pointer (USP)
USP
The 16-bit pointer indicating a user stack address.
: System stack pointer (SSP)
SSP
The 16-bit pointer indicating the status of the system stack address.
: Processor status (PS)
PS
The 16-bit register indicating the system status.
: Program counter (PC)
PC
The 16-bit register indicating storing location of the current instruction code.
DPR
PCB
DTB
USB
SSB
ADB
: Direct page register (DPR)
The 8-bit register for specifying bit 8 through 15 of the operand address in the
short direct addressing mode.
: Program bank register (PCB)
The 8-bit register indicating the program space.
: Data bank register (DTB)
The 8-bit register indicating the data space.
: User stack bank register (USB)
The 8-bit register indicating the user stack space.
: System stack bank register (SSB)
The 8-bit register indicating the system stack space.
: Additional data bank register (ADB)
The 8-bit register indicating the additional space.
8-bit
16-bit
32-bit
29
MB90670/675 Series
(2) General-purpose Registers
Maximum of 32 banks
R7
R6
RW7
R5
R4
RW6
R3
R2
RW5
R1
R0
RW4
RL3
RL2
RW3
RL1
RW2
RW1
RL0
RW0
000180 H + (RP × 10 H )
16-bit
(3) Processor Status (PS)
ILM
RP
CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6
PS
ILM2 ILM1 ILM0
Initial value
— : Unused
X : Indeterminate
30
0
0
0
bit 5 bit 4
bit 3 bit 2
bit 1
bit 0
B4
B3
B2
B1
B0
—
I
S
T
N
Z
V
C
0
0
0
0
0
—
0
1
X
X
X
X
X
MB90670/675 Series
■ I/O MAP
Address
Abbreviated
register name
Read/
write
Resource name
Initial value
000000H
PDR0
Port 0 data register
R/W
Port 0
XXXXXXXXB
000001H
PDR1
Port 1 data register
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 data register
R/W
Port 5
1 1 1 11 1 1 1B
000006H
PDR6
Port 6 data register
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R
Port 7
Register name
XXXXXXXXB
5
000008H
PDR8
Port 8 data register
R/W
Port 8*
–XXXXXXXB
000009H
PDR9
Port 9 data register
R/W
Port 9*5
––––––11B
00000AH
PDRA
Port A data register
R/W
Port A*5
XXXXXXXXB
R/W
5
00000BH
PDRB
00000CH
to
00000EH
Port B data register
Port B*
– – – – – XXXB
(Vacancy)*3
00000FH
EIFR
Wake-up interrupt flag register
R/W
Wake-up
interrupt
– – – – – – – 0B
000010H
DDR0
Port 0 data direction register
R/W
Port 0
00000000B
000011H
DDR1
Port 1 data direction register
R/W
Port 1
00000000B
000012H
DDR2
Port 2 data direction register
R/W
Port 2
00000000B
000013H
DDR3
Port 3 data direction register
R/W
Port 3
00000000B
000014H
DDR4
Port 4 data direction register
R/W
Port 4
00000000B
000015H
ADER
Analog input enable register
R/W
Port 5,
analog input
11111111B
000016H
DDR6
Port 6 data direction register
R/W
Port 6
00000000B
000017H
DDR7
Port 7 data direction register
R/W
Port 7
00000000B
000018H
DDR8
Port 8 data direction register
R/W
Port 8*5
–0000000B
3
000019H
(Vacancy)*
00001AH
DDRA
Port A data direction register
R/W
Port A*5
00000000B
00001BH
DDRB
Port B data direction register
R/W
Port B*5
– – – – – 000B
Wake-up
interrupt
00000000B
00001CH
to
00001EH
00001FH
(Vacancy)*3
EICR
Wake-up interrupt enable register
W
(Continued)
31
MB90670/675 Series
Address
Abbreviated
register name
Read/
write
000020H
UMC0
Mode control register 0
R/W!
00000100B
000021H
USR0
Status register 0
R/W!
00010000B
000022H
UIDR0/
UODR0
Input data register 0/
output data register 0
R/W
000023H
URD0
Rate and data register 0
R/W
00000000B
000024H
SMR1
Mode register 1
R/W
00000000B
000025H
SCR1
Control register 1
R/W!
000026H
SIDR1/
SODR1
Input data register 1/
output data register 1
R/W
000027H
SSR1
Status register 1
R/W!
000028H
ENIR
DTP/interrupt enable register
R/W
Register name
000029H
EIRR
DTP/interrupt factor register
R/W
00002AH
ELVR
Request level setting register
R/W
00002DH
00002EH
UART0
UART1
(SCI)
Initial value
XXXXXXXXB
00000100B
XXXXXXXXB
00001–00B
– – – – 0000B
DTP/external interrupt circuit
– – – – 0000B
00000000B
(Vacancy)*3
00002BH
00002CH
Resource name
ADCS
A/D convertor control status register
00000000B
R/W!
8/10-bit A/D
converter
R/W!*4
00000000B
XXXXXXXXB
ADCR
A/D convertor data register
000030H
PPGC0
PPG0 operating mode control
register
R/W!
8/16-bit PPG
timer 0
0–000001B
000031H
PPGC1
PPG1 operating mode control
register
R/W!
8/16-bit PPG
timer 1
00000000B
00002FH
000032H
(Vacancy)*3
000033H
000034H
PRLL0
000035H
PRLH0
000036H
PRLL1
000037H
PRLH1
000038H
000039H
00003AH
00003BH
00003CH
00003DH
00003EH
00003FH
000000XXB
TMCSR0
PPG0 reload register
PPG1 reload register
Timer control status register 0
R/W
R/W
R/W
R/W
R/W
TMCSR1
Timer control status register 1
R/W!
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
– – – – 0000B
XXXXXXXXB
XXXXXXXXB
00000000B
16-bit reload
timer 1
R/W
XXXXXXXXB
00000000B
16-bit reload
timer 0
16-bit timer register 0/
16-bit reload register 0
16-bit timer register 1/
16-bit reload register 1
8/16-bit PPG
timer 1
R/W!
TMR0/
TMRLR0
TMR1/
TMRLR1
8/16-bit PPG
timer 0
– – – – 0000B
XXXXXXXXB
XXXXXXXXB
(Continued)
32
MB90670/675 Series
Address
Abbreviated
register name
000040H
IBSR
Read/
write
Register name
I2C bus status register
2
Resource name
Initial value
R
00000000B
00000000B
000041H
IBCR
I C bus control register
R/W
000042H
ICCR
I2C bus clock control register
R/W
000043H
IADR
I2C bus address register
R/W
–XXXXXXXB
R/W
XXXXXXXXB
000044H
IDAR
2
I C bus data register
000045H
to
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
000056H
000057H
000058H
000059H
00005AH
00005BH
00005CH
00005DH
00005EH
00005FH
000060H
000061H
000062H
000063H
000064H
000065H
000066H
000067H
000068H
000069H
I2C interface*6
– – 0XXXXXB
(Vacancy)*3
TCCR
ICC
TCRL
Free-run timer control register
R/W!
24-bit free-run
timer
ICU control register
R/W
Input capture
(ICU)
Free-run timer lower data register
24-bit free-run
timer
Free-run timer upper data register
CCR00
OCU control register 00
R/W
CCR01
OCU control register 01
R/W
CCR10
OCU control register 10
R/W
CCR11
OCU control register 11
R/W
ICDR0L
ICU lower data register 0
R
ICDR0H
ICU upper data register 0
R
ICDR1L
ICU lower data register 1
R
ICDR1H
ICU upper data register 1
R
ICDR2L
ICU lower data register 2
R
– – 111111B
00000000B
00000000B
00000000B
R
TCRH
11000000B
R
00000000B
00000000B
00000000B
11110000B
Output compare
(OCU)
(unit 0)
– – – – 0000B
– – – – 0000B
00000000B
11110000B
Output compare
(OCU)
(unit 1)
– – – – 0000B
– – – – 0000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
Input capture
(ICU)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
XXXXXXXXB
XXXXXXXXB
(Continued)
33
MB90670/675 Series
Address
00006AH
00006BH
00006CH
00006DH
00006EH
00006FH
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
Abbreviated
register name
Register name
Read/
write
ICDR2H
ICU upper data register 2
R
ICDR3L
ICU lower data register 3
R
ICDR3H
ICU upper data register 3
R
CPR00L
OCU compare lower data
register 0
R/W
CPR00H
OCU compare upper data
register 0
R/W
CPR01L
OCU compare lower data
register 1
R/W
CPR01H
OCU compare upper data
register 1
R/W
CPR02L
OCU compare lower data
register 2
R/W
CPR02H
OCU compare upper data
register 2
R/W
CPR03L
OCU compare lower data
register 3
R/W
CPR03H
OCU compare upper data register
3
R/W
CPR04L
OCU compare lower data
register 4
R/W
CPR04H
OCU compare upper data
register 4
R/W
CPR05L
OCU compare lower data
register 5
R/W
CPR05H
OCU compare upper data
register 5
R/W
CPR06L
OCU compare lower data
register 6
R/W
CPR06H
OCU compare upper data
register 6
R/W
Resource name
Initial value
XXXXXXXXB
00000000B
Input capture
(ICU)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Output compare
(OCU)
(unit 0)
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Output compare
(OCU)
(unit 1)
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
(Continued)
34
MB90670/675 Series
Address
00008CH
00008DH
00008EH
00008FH
Abbreviated
register name
Read/
write
Register name
CPR07L
OCU compare lower data
register 7
R/W
CPR07H
OCU compare upper data
register 7
R/W
000090H
to
00009EH
Resource name
Initial value
00000000B
Output compare
(OCU)
(unit 1)
00000000B
00000000B
00000000B
(System reservation area)*1
R/W
Delayed
interrupt
generation
module
– – – – – – – 0B
00009FH
DIRR
Delayed interrupt factor generation/
cancellation register
0000A0H
LPMCR
Low-power consumption mode
control register
R/W!
Low-power
consumption
(stand-by) mode
00011000B
0000A1H
CKSCR
Clock selection register
R/W!
Low-power
consumption
(stand-by) mode
11111100B
0000A2H
to
0000A4H
(Vacancy)*3
0000A5H
ARSR
Automatic ready function select
register
W
External bus pin
0011 – – 00B
0000A6H
HACR
Upper address control register
W
External bus pin
– – – – 0000B
0000A7H
EPCR
Bus control signal select register
W
External bus pin
0000*00–B
0000A8H
WDTC
Watchdog timer control register
R/W!
Watchdog timer
XXXXX111B
0000A9H
TBTC
Timebase timer control register
R/W!
Timebase timer
1 – – 00100B
0000AAH
to
0000AFH
(Vacancy)*3
0000B0H
ICR00
Interrupt control register 00
R/W!
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W!
00000111B
0000B2H
ICR02
Interrupt control register 02
R/W!
00000111B
0000B3H
ICR03
Interrupt control register 03
R/W!
00000111B
0000B4H
ICR04
Interrupt control register 04
R/W!
0000B5H
ICR05
Interrupt control register 05
R/W!
0000B6H
ICR06
Interrupt control register 06
R/W!
00000111B
0000B7H
ICR07
Interrupt control register 07
R/W!
00000111B
0000B8H
ICR08
Interrupt control register 08
R/W!
00000111B
0000B9H
ICR09
Interrupt control register 09
R/W!
00000111B
Interrupt
controller
00000111B
00000111B
(Continued)
35
MB90670/675 Series
(Continued)
Address
Abbreviated
register name
0000BAH
ICR10
Interrupt control register 10
R/W!
00000111B
0000BBH
ICR11
Interrupt control register 11
R/W!
00000111B
0000BCH
ICR12
Interrupt control register 12
R/W!
0000BDH
ICR13
Interrupt control register 13
R/W!
0000BEH
ICR14
Interrupt control register 14
R/W!
00000111B
0000BFH
ICR15
Interrupt control register 15
R/W!
00000111B
0000C0H
to
0000FFH
Register name
Read/
write
Resource name
Interrupt
controller
Initial value
00000111B
00000111B
(External area)*2
Descriptions for read/write
R/W: Readable and writable
R: Read only
W: Write only
R/W!: Bits for reading operation only or writing operation only are included. Refer to the register lists for specific
resource for detailed information.
Descriptions for initial value
0
1
*
X
–
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is “1” or “0” (decided by levels on pins of MD0 through MD2).
: The initial value of this bit is indeterminate.
: This bit is not used. The initial value is indeterminate.
*1: Access prohibited.
*2: This area is the only external access area having an address of 0000FFH or lower. An access operation to this
area is handled as that to external I/O area.
*3: The area corresponding to the “(Vacancy)” on the I/O map is reserved, and accessing operation to this area is
handled as that to internal area. No access signal to external devices are generated.
*4: Only bit 15 is writable. Reading bit 10 through bit 15 returns “0” as a reading result.
*5: In the MB90670 series, P81 through P86, P90, P91, PA0 through PA7, PB0 through PB2 are not present. For
this reason, bits corresponding to these pins are not used.
*6: The MB90670 series does not have the I2C interface. For this reason, this area is “(Vacancy)” in the MB90670
series.
Note: For bits that is only allowed to program, the initial value set by the reset operation is listed as an initial value.
Note that the values are different from reading results.
For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending
on the types of the reset. However initial value for resets that initializes the value are listed.
36
MB90670/675 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt source
EI2OS
support
Interrupt vector
Number
Interrupt control register
Address
ICR
Address
Reset
×
# 08
08H
FFFFDCH
—
—
INT9 instruction
×
# 09
09H
FFFFD8H
—
—
Exception
×
# 10
0AH
FFFFD4H
—
—
DTP/external interrupt circuit
Channel 0
# 11
0BH
FFFFD0H
DTP/external interrupt circuit
Channel 1
ICR00
0000B0H*2
# 12
0CH
FFFFCCH
DTP/external interrupt circuit
Channel 2
# 13
0DH
FFFFC8H
DTP/external interrupt circuit
Channel 3
ICR01
0000B1H*2
# 14
0EH
FFFFC4H
Output compare Channel 0
# 15
0FH
FFFFC0H
Output compare Channel 1
# 16
10H
FFFFBCH
ICR02
0000B2H*2
Output compare Channel 2
# 17
11H
FFFFB8H
Output compare Channel 3
# 18
12H
FFFFB4H
ICR03
0000B3H*2
Output compare Channel 4
# 19
13H
FFFFB0H
Output compare Channel 5
# 20
14H
FFFFACH
ICR04
0000B4H*2
Output compare Channel 6
# 21
15H
FFFFA8H
Output compare Channel 7
# 22
16H
FFFFA4H
ICR05
0000B5H*2
24-bit free-run timer Overflow
# 23
17H
FFFFA0H
24-bit free-run timer Intermediate
bit
# 24
18H
FFFF9CH
ICR06
0000B6H*2
Input capture Channel 0
# 25
19H
FFFF98H
Input capture Channel 1
# 26
1AH
FFFF94H
ICR07
0000B7H*2
Input capture Channel 2
# 27
1BH
FFFF90H
Input capture Channel 3
# 28
1CH
FFFF8CH
ICR08
0000B8H*2
16-bit reload timer/
8/16-bit PPG timer 0
# 29
1DH
FFFF88H
16-bit reload timer/
8/16-bit PPG timer 1
ICR09
0000B9H*2, *3
# 30
1EH
FFFF84H
8/10-bit A/D converter measurement complete
# 31
1FH
FFFF80H
ICR10
0000BAH
ICR11
0000BBH*2
Wake-up interrupt
×
# 33
21H
FFFF78H
Timebase timer interval interrupt
×
# 34
22H
FFFF74H
Priority*4
High
Low
(Continued)
37
MB90670/675 Series
(Continued)
Interrupt source
EI2OS
support
Interrupt vector
Number
Interrupt control register
Address
ICR
Address
ICR12
0000BCH*2
ICR13
0000BDH*2
UART1 (SCI) transmission complete
# 35
23H
FFFF70H
UART0 transmission complete
# 36
24H
FFFF6CH
UART1 (SCI) reception complete
# 37
25H
FFFF68H
# 38
26H
FFFF64H
# 39
27H
FFFF60H
ICR14
0000BEH
# 42
2AH
FFFF54H
ICR15
0000BFH
I2C interface*1
×
UART0 reception complete
Delayed interrupt generation
module
×
Priority*4
High
Low
: Can be used
× : Can not be used
: Can be used. With EI2OS stop function.
: Can be used if interrupt request using ICR are not commonly used.
*1: In MB90670 series, this interrupt vector is not used because the series does not have the I2C interface.
*2: • Interrupt levels for peripherals that commonly use the ICR register are in the same level.
• When the extended intelligent I/O service (EI2OS) is specified in a peripheral device commonly using the ICR
register, only one of the functions can be used.
• When the extended intelligent I/O service (EI2OS) is specified for one of the peripheral functions, interrupts
can not be used on the other function.
*3: Only 16-bit reload timer conforms to the extended intelligent I/O service (EI2OS). Because the 8/16-bit PPG
timer does not conform to the extended intelligent I/O service (EI2OS), disable interrupts of the 8/16-bit PPG
timer when using the extended intelligent I/O service (EI2OS) in the 16-bit reload timer.
*4: The level shows priority of same level of interrupt invoked simultaneously.
38
MB90670/675 Series
■ PERIPHERALS
1. I/O Port
(1) Input/output Port
Port 0 to 4, 6, 8, A, and B are general-purpose I/O ports having a combined function as an external bus pin and
a resource input. The input output ports function as general-purpose I/O port only in the single-chip mode. In
the external bus mode, the ports are configured as external bus pins, and part of pins for port 3 can be configured
as general-purpose I/O port by setting the bus control signal select register (ECSR). Each pin corresponding
to upper 4-bit of the port 2 can be switched between a resource and a port bitwise.
Only MB90675 series has port A and port B.
• Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR
register.
Note: When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the
destination bit of the operation is set to the specified value, not affecting the bits configured by the
DDR register for output, however, values of bits configured by the DDR register as inputs are changed
because input values to the pins are written into the output latch. To avoid this situation, configure the
pins by the DDR register as output after writing output data to the PDR register when configuring the
bit used as input as outputs.
• Operation as input port
The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.
When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance
status.
When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”)
• Block diagram
Internal data bus
PDR (port data register)
PDR read
Output latch
P-ch
PDR write
Pin
DDR (port direction register)
Direction latch
N-ch
DDR write
Standby control (SPL=1)
DDR read
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
39
MB90670/675 Series
(2) N-ch Open-drain Port
Port 5 and port 9 are general-purpose I/O ports having a combined function as resource input/output. Each pin
can be switched between resource and port bitwise.
Only MB90675 series has port 9.
• Operation as output port
When a data is written into the PDR register, the data is latched to the output latch of PDR. When the output
latch value is set to “0”, the output transistor is turned on and the pin status is put into an “L” level output, while
writing “1” turns off the transistor and put the pin in a high-impedance status.
If the output pin is pulled-up, setting output latch value to “1” puts the pin in the pull-up status.
Reading the PDR register returns the pin value (same as the output latch value in the PDR).
Note: Execution of a read-modify-write instruction (e.g. bit set instruction) reads out the output latch value
rather than the pin value, leaving output latch that is not manipulated unchanged.
• Operation as input port
Setting corresponding bit of the PDR register to “1” turns off the output transistor and the pin is put into a highimpedance status.
Reading the PDR register returns the pin level (“0” or “1”).
• Block diagram of port 5
ADER (analog input enable register)
To analog input
ADER read
ADER latch
Internal data bus
ADER write
PDR (port data register)
RMW
(read-modify-write
instruction)
PDR read
Pin
Output trigger
Output latch
PDR write
Standby control (SPL=1)
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
• Block diagram of port 9
From resource output
Standby control
(SPL=1)
Internal data bus
To resource input
PDR (port data register)
PDR read
RMW
(read-modifywrite instruction)
Output
trigger
Output latch
PDR write
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
40
Pin
MB90670/675 Series
(3) Output Port
Port 7 is a general-purpose output port having a combined function as an output compare (OCU) output. Note
that only OCU output can be output when the pin is configured as an output, and it is not used for outputting
given data by writing to the data register. Each pin can be switched between an output compare output and a
port bitwise.
• Operation as output port (operation of OCU output)
Setting the corresponding bit of the DDR register to “1” configures the pin as an output port. In this case, lower
4-bit of CCR01 and CCR register are output.
When configured as an output, the output buffer is turned on and data retained in the output latch in the PDR
of the output compare is output to the pin.
Writing data to DOT bit of the OCU control register (CCR01, CCR11) corresponding to each pin writes data
in synchronization to a match operation of the output compare and output to the pin.
Reading the PDR register returns the pin level (same as the output latch value of the PDR).
When output of output compare is enabled, an output value from the output compare can be read out.
• Operation as input port
Setting corresponding bit of the DDR register to “0” configures the pin as input port.
When the pin is configured as an input port, the output buffer is turned off and the pin is put into a highimpedance status.
Reading the PDR register returns the pin level (“0” or “1”).
• Block diagram
PDR (port data register)
Internal data bus
PDR read
OCU control register
P-ch
OCU control register write
Pin
DDR (port direction register)
Direction latch
N-ch
DDR write
Standby control (SPL=1)
DDR read
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
41
MB90670/675 Series
(4) Register Configuration
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000000H
P07
P06
P05
P04
P03
P02
P01
P00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(PDR1)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7. . . . . . . . . . . . bit 0
000001H
P17
P16
P15
P14
P13
P12
P11
P10
(PDR0)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 1 data register
(PDR1)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000002H
P27
P26
P25
P24
P23
P22
P21
P20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(PDR3)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7. . . . . . . . . . . . bit 0
000003H
P37
P36
P35
P34
P33
P32
P31
P30
(PDR2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000004H
P47
P46
P45
P44
P43
P42
P41
P40
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7. . . . . . . . . . . . bit 0
000005H
P57
P56
P55
P54
P53
P52
P51
P50
(PDR4)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000006H
P67
P66
P65
P64
P63
P62
P61
P60
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
000007H
P77
P76
P75
P74
P73
P72
P71
P70
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 7 data register
(PDR7)
(PDR6)
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000008H
—
P86
P85
P84
P83
P82
P81
P80
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7. . . . . . . . . . . . bit 0
000009H
—
—
—
—
—
—
P91
P90
(PDR8)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 8 data register
(PDR8)
Port 9 data register
(PDR9)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00000AH
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(PDRB)
Port 6 data register
(PDR6)
bit 7. . . . . . . . . . . . bit 0
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(PDR9)
Port 4 data register
(PDR4)
Port 5 data register
(PDR5)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(PDR7)
Port 2 data register
(PDR2)
Port 3 data register
(PDR3)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(PDR5)
Port 0 data register
(PDR0)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7. . . . . . . . . . . . bit 0
00000BH
—
—
—
—
—
PB2
PB1
PB0
(PDRA)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port A data register
(PDRA)
Port B data register
(PDRB)
(Continued)
42
MB90670/675 Series
(Continued)
Address bit-15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000010H
P07
P06
P05
P04
P03
P02
P01
P00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
000011H
(DDR1)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7. . . . . . . . . . . . bit 0
P17
P16
P15
P14
P13
P12
P11
P10
(DDR0)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 1 data direction register
(DDR1)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000012H
P27
P26
P25
P24
P23
P22
P21
P20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(DDR3)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7. . . . . . . . . . . . bit 0
000013H
P37
P36
P35
P34
P33
P32
P31
P30
(DDR2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000014H
P47
P46
P45
P44
P43
P42
P41
P40
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7. . . . . . . . . . . . bit 0
000015H
P57
P56
P55
P54
P53
P52
P51
P50
(DDR4)
bit 1
bit 0
000016H
P67
P66
P65
P64
P63
P62
P61
P60
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7. . . . . . . . . . . . bit 0
000017H
P77
P76
P75
P74
P73
P72
P71
P70
(DDR6)
bit 1
bit 0
000018H
P81
P80
—
P86
P85
P84
P83
P82
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
R/W
R/W
R/W
R/W
R/W
R/W
(DDRB)
00001AH
Port 6 data direction register
(DDR6)
Port 7 data direction register
(DDR7)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(Vacancy)
Port 4 data direction register
(DDR4)
Analog input enable register
(ADER)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
(DDR7)
Port 2 data direction register
(DDR2)
Port 3 data direction register
(DDR3)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(ADER)
Port 0 data direction register
(DDR0)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
R/W
.
.
.
.
.
.
.
.
.
.
.
. bit 0
bit 7
00001BH
—
—
—
—
—
PB2
PB1
PB0
(DDRA)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 8 data direction register
(DDR8)
Port A data direction register
(DDRA)
Port B data direction register
(DDRB)
Note: Only MB90675 series has P81 through P86, P90, PA0 through PA7, and PB0 through PB2, and
MB90670 series does not have such pins.
43
MB90670/675 Series
2. Timebase Timer
The timebase timer is a 18-bit free run counter (timebase counter) for counting up in synchronization to the
internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from
four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK.
The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation
stabilization time or the watchdog timer etc.
(1) Register Configuration
• Timebase timer control register (TBTC)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
0000A9H
RESV
—
—
TBIE
TBOF
R/W
—
—
R/W
R/W
bit 9
bit 8
TBR
TBC1
TBC0
W
R/W
R/W
bit 7 . . . . . . . . . . . .bit 0
(WDTC)
Initial value
1--00100B
R/W: Readable and writable
W : Read only
— : Unused
(2) Block Diagram
To watchdog timer
To PPG timer
Timebase timer counter
Divided-by-2
of HCLK
× 21 × 22 × 2 3
...
...
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
OF
OF
OF
To oscillation stabilization
time selector of clock control block
Power-on reset
Start stop mode
CKSCR : MCS = 1→0*1
Counter
clear circuit
Interval
timer selector
Set TBOF
Clear TBOF
Timebase timer control register
(TBTC)
—
—
—
TBIE TBOF TBR
Timebase timer
interrupt signal
#34(22H)*2
OF : Overflow
HCLK: Oscillation clock
*1
: Switch machine clock from oscillation clock to PLL clock
*2
: Interrupt number
44
TBC1 TBC0
MB90670/675 Series
3. Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
• Watchdog timer control register (WDTC)
Address
bit 15 . . . . . . . . . . . . bit 8
0000A8H
(TBTC)
bit 7
bit 6
bit 5
bit 4
PONR STBR WRST ERST
R
R
R
bit 3
bit 2
bit 1
bit 0
SRST
WTE
WT1
WT0
R
W
W
W
R
Initial value
XXXXX1 1 1 B
R : Read only
W : Write only
X : Indeterminate
(2) Block Diagram
Watchdog timer control register (WDTC)
PONR STBR WRST ERST SRST WTE WT1
WT0
2
Watchdog timer
CLR and start
Overflow
Start sleep mode
Start hold status
Start stop mode
Counter clear
control circuit
Count clock
selector
2-bit
counter
CLR
Watchdog reset
generation circuit
To internal reset
generation circuit
CLR
4
Clear
(Timebase timer counter)
Divided-by-2
of HCLK
× 21 × 22
...
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
HCLK: Oscillation clock
45
MB90670/675 Series
4. 8/16-bit PPG Timer
The 8/16-bit PPG timer is 2-channel reload timer module for outputting pulse having given frequencies/duty ratios.
The two modules performs the following operation by combining functions.
• 8-bit PPG output 2-channel independent operation mode
This is a mode for operating independent 2-channel 8-bit PPG timer, in which PPG0 and PPG1 pins correspond
to outputs from PPG0 and PPG1 respectively.
• 16-bit PPG output operation mode
In this mode, PPG0 and PPG1 are combined to be operated as a 1-channel 8/16-bit PPG timer operating as
a 16-bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the
same output pulses from PPG0 and PPG1 pins.
• 8 + 8-bit PPG output operation mode
In this mode, PPG0 is operated as an 8-bit prescaler, in which an underflow output of PPG0 is used as a clock
source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0 and PPG1
respectively.
The module can also be used as a D/A converter with an external add-on circuit.
(1) Register Configuration
• PPG0 operating mode control register (PPGC0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(PPGC1)
000030H
bit 6
bit 5
bit 4
bit 3
PEN0
—
POE0
PIE0
PUF0 PCM1 PCM0 RESV
R/W
—
R/W
R/W
R/W
bit 2
R/W
bit 1
R/W
bit 0
Initial value
0 - 000001 B
R/W
• PPG1 operating mode control register (PPGC 1)
bit 8 bit 7 . . . . . . . . . . . . bit 0
Address
bit 15
bit 13
bit 12
bit 11
bit 10
bit 9
000031H
PEN1 PCS1 POE1
PIE1
PUF1
MD1
MD0
RESV
R/W
R/W
R/W
R/W
R/W
R/W
bit 14
R/W
R/W
(PPGC0)
Initial value
00000001 B
• PPG reload register (PRLL0,PRLH0,PRLL1,PRLH1)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
PRLH0:000035H
(PRLH0,PRLH1)
PRLH1:000037H
R/W
Address
PRLL0:000034H
PRLL1:000036H
bit 15
bit 14
bit 13
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
R/W
bit 11
R/W
bit 10
R/W
bit 9
R/W
R/W
R/W
R/W
bit 8 bit 7 . . . . . . . . . . . . bit 0
(PRLL0,PRLL1)
R/W
R/W
R/W
R/W : Readable and writable
— : Unused
X : Indeterminate
46
bit 12
bit 6
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXX B
MB90670/675 Series
(2) Block Diagram
• Block diagram of 8/16-bit PPG timer 0
Data bus for “H” digits
Data bus for “L” digits
PPG0 reload
register
PPG0 operating mode control register (PPGC0)
PRLH0
PEN0
PRLL0
—
POE0 PIE0 PUF0 PCM1 PCM0 RESV
R
Temporary buffer
(PRLBH0)
S
Interrupt request
#29 (1DH)*
Q
2
Reload selector
(L/H selector)
Mode control signal
Select signal
PPG1 underflow
PPG0 underflow
(to PPG1)
Count value
reload
Clear
Pulse selector
Down counter
(PCNT0)
Underflow
CLK
Reverse
PPG0
output latch
Pin
P46/PPG0
Timebase timer output (512/HCLK)
Peripheral clock (16/φ)
Peripheral clock (4/φ)
Peripheral clock (1/φ)
PPG output
control circuit
Count clock selector
2
Select signal
* : Interrupt number
HCLK : Oscillation clock
φ :Machine clock frequency
47
MB90670/675 Series
• Block diagram of 8/16-bit PPG timer 1
Data bus for “H” digits
Data bus for “L” digits
PPG1 operating mode control register (PPGC1)
PPG1 reload
register
Operating mode
control signal
PRLL1
PRLH1
PEN1 PCS1 POE1 PIE1 PUF1 MD1
2
R
Temporary buffer
(PRLBH0)
S
Reload selector
(L/H selector)
Count value
Clear
Underflow
Reverse
PPG1
output latch
Pin
P80/PPG1
CLK
PPG output control circuit
PPG1 underflow
(to PPG0)
MD0
PPG0 underflow
Timebase timer output (512/HCLK)
Peripheral clock (1/φ)
Count clock selector
Select signal
* : Interrupt number
HCLK : Oscillation clock
φ : Machine clock frequency
Interrupt request
#30 (1EH)*
Q
Select signal
reload
Down counter
(PCNT1)
48
MD0 RESV
MB90670/675 Series
5. 16-bit Reload Timer
The 16-bit reload timer has an internal clock mode for counting down in synchronization to three types of internal
clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus
pin, and either of the two functions can be selectively used.
For this timer, an “underflow” is defined as the counter value of “0000H” to “FFFFH”. According to this definition,
an underflow occurs after [reload register setting value + 1] counts.
In operating the counter, the reload mode for repeating counting operation after reloading a counter setting value
after an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively
used.
Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent
I/O service (EI2OS).
The MB90670/675 series has 2 channels of 16-bit reload timers.
(1) Register Configuration
• Timer control status register upper digits (TMCSR0,TMCSR1 : H)
Address
TMCSR0:000039H
TMCSR1:00003DH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
—
—
—
—
CSL1
CSL0 MOD2 MOD1
—
—
—
—
R/W
R/W
R/W
bit 7 . . . . . . . . . . . . . bit 0
Initial value
(TMCSR : L)
- - - - 0000 B
R/W
• Timer control status register lower digits (TMCSR0,TMCSR1 : L)
Address
bit 15. . . . . . . . . . . . .bit 8 bit 7
TMCSR0:000038H
TMCSR1:00003CH
bit 6
bit 5
bit 4
MOD1 OUTE OUTL RELD
(TMCSR : H)
R/W
R/W
R/W
R/W
bit 3
bit 2
bit 1
bit 0
Initial value
INTE
UF
CNTE
TRG
00000000 B
R/W
R/W
R/W
R/W
• 16-bit timer register 0, 1 (TMR0,TMR1)
Address
00003AH
00003BH
00003EH
00003FH
bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
• 16-bit reload register 0, 1 (TMRL0,TMRL1)
Address
00003AH
00003BH
00003EH
00003FH
bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W : Readable and writable
R : Read only
W : Write only
— : Unused
X : Indeterminate
49
MB90670/675 Series
(2) Block Diagram
Internal data bus
TMRLR0*1
<TMRLR1>
16-bit reload register
reload signal
TMRR0*1
<TMR1>
reload
control circuit
16-bit timer register (down counter) UF
CLK
Count clock generation circuit
φ
Prescaler
3
Gate input
Valid clock
decision
circuit
Clear
Wait signal
To UART0, 1*1
<To 8/10-bit A/D converter>
CLK
Internal
Output control circuit
clock
Input
control
circuit
Pin
P24/TIN0*1
<P25/TIN1>
Clock
selector
External
clock
3
2
Output
generation circuit
Reverse
—
—
EN
P26/TOT0*1
<P27/TOT1>
Select
signal
Function select
—
Pin
Operation
control circuit
— CSL1 CSL0 MOD2MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
Timer control status register (TMCSR0)*1
<TMCSR1>
Interrupt request signal
#29 (1DH)*2
*1 :The timer has ch.0 and ch.1, and listed in the parenthesis <> are for ch.1.
*2 :Interrupt number
φ :Machine clock frequency
50
<#30 (1EH)>
MB90670/675 Series
6. 24-bit Free run Timer
The 24-bit free-run timer is a 24-bit up counter for counting up in synchronization to divided-by-3 or divided-by4 of the machine clock, in which an interrupt factor can be selected from the overflow interrupt and four types
of timer intermediate bit interrupt to be operated as an interval timer.
The free-run timer can be used to generating reference timing signals for the input capture (ICU) and output
compare (OCU).
(1) Register Configuration
• Free-run timer control register upper digits (TCCR : H)
Address
bit 15
bit 14
000051H
—
—
—
—
bit 13
bit 12
bit 11
bit 10
bit 9
RESV RESV RESV RESV RESV
R/W
R/W
R/W
R/W
R/W
bit 8
bit 7 . . . . . . . . . . . . . bit 0
Initial value
PR0
(TCCR : L)
- - 111111 B
R/W
• Free-run timer control register lower digits (TCCR : L)
Address
bit 15. . . . . . . . . . . . .bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
STP
CLR
IVF
IVFE
TIM
TIME
TIS1
TIS0
11000000B
W
W
R/W
R/W
R/W
R/W
R/W
R/W
000050H
(TCCR : H)
• Free-run timer upper data register (TCRH)
Address
000056H
000057H
bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
—
—
—
—
—
—
—
— T23 T22 T21 T20 T19 T18 T17 T16
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial value
00000000B
00000000B
R
• Free-run timer lower data register (TCRL)
Address
000054H
000055H
bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
T15 T14 T13 T12 T11 T10
R
R
R
R
R
R
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
R
R
R
R
R
R
R
R
R
R
Initial value
00000000B
00000000B
R/W : Readable and writable
R : Read only
W : Write only
— : Unused
51
MB90670/675 Series
(2) Block Diagram
Internal data bus
24-bit counter
(TCR)
Output buffer
8
TCRH
Carry
Upper 8-bit counter
16
TCRL
T16 to T23
To output compare (OCU)
T0 to T15
To input capture (ICU)
Lower 16-bit counter
Carry
4
Prescaler
φ/3
φ
φ/4
Count
clock
selector
Select signal
Pause
Intermediate
bit interrupt
control circuit
Carry
detection
Overflow
—
— RESV RESV RESV RESV RESV PR0 STP CLR IVF IVFE TIM TIME TIS1 TIS0
Free-run timer control register (TCCR)
* : Interrupt number
φ : Machine clock frequency
52
Intermediate bit interrupt
request signal
#24 (18H)*
Overflow interrupt
request signal
#23 (17H)*
MB90670/675 Series
7. Input Capture (ICU)
The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of
current counter value of the 24-bit free run timer to the ICU data register (ICDR) upon an input of a trigger edge
to the external pin.
There are four sets (four channels) of the input capture external pins and ICU data registers (ICDR), enabling
measurements of maximum of four events.
• The input capture has four sets of external input pins (ASR0 to ASR3) and ICU registers (ICDR), enabling
measurements of maximum of four events.
• A trigger edge direction can be selected from rising/falling/both edges.
• The input capture can be set to generate an interrupt request at the storage timing of the counter value of the
24-bit free run timer to the ICU data register (ICDR).
• The input compare conforms to the extended intelligent I/O service (EI2OS).
• The input capture function is suited for measurements of intervals (frequencies) and pulse-widths.
(1) Register Configuration
• ICU control register upper digits (ICC : H)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
000053H
IRE3
IRE2
IRE1
IRE0
IR3
IR2
R/W
R/W
R/W
R/W
R/W
R/W
bit 8 bit 7 . . . . . . . . . . . . . bit 0
Initial value
IR1
IR0
00000000B
R/W
R/W
bit 9
(ICC : L)
• ICU control register lower digits (ICC : L)
Address
bit 15. . . . . . . . . . . . bit 8
000052H
(ICC : H)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EG3B EG3A
EG2B EG2A EG1B EG1A
EG0B EG0A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
R/W
• ICU upper data register 0 to 3 (ICDR0H to ICDR3H)
Address
ICDR0H : 000063H
ICDR1H : 000067H
ICDR2H : 00006BH
ICDR3H : 00006FH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
—
—
—
—
—
—
—
—
00000000B
R
R
R
R
R
R
R
R
Address
ICDR0H : 000062H
ICDR1H : 000066H
ICDR2H : 00006AH
ICDR3H : 00006EH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D23
D22
D21
D20
D19
D18
D17
D16
XXXXXXXXB
R
R
R
R
R
R
R
R
bit 12
bit 11
bit 10
bit 9
bit 8
• ICU lower data register 0 to 3 (ICDR0L to ICDR3L)
bit 15 bit 14 bit 13
Address
ICDR0L : 000061H
ICDR1L : 000065H
ICDR2L : 000069H
ICDR3L : 00006DH
Address
ICDR0L : 000060H
ICDR1L : 000064H
ICDR2L : 000068H
ICDR3L : 00006CH
D15
D14
D13
D12
D11
D10
D9
D8
R
R
R
R
R
R
R
R
Initial value
XXXXXXXXB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Initial value
XXXXXXXXB
R/W : Readable and writable
R : Read only
— : Unused
X : Indeterminate
53
MB90670/675 Series
(2) Block Diagram
Internal data bus
Latch
signal
Output latch
ICU data register
(ICDR)
Edge detection circuit
P61/ASR0
24
Data latch signal
Pin
ICDR0H
ICDR0L
ICDR1H
ICDR1L
2
P65/ASR1
24
Pin
2
P66/ASR2
24
Pin
ICDR2H
ICDR2L
ICDR3H
ICDR3L
24-bit free-run
timer
2
P67/ASR3
24
Pin
2
ICU control
register (ICC)
IRE3 IRE2 IRE1 IRE0 IR3 IR2 IR1
IR0 EG3B EG3A EG2B EG2A EG1B EG1A EG0B EG0A
#25 (19H)*
#26 (1AH)*
#27 (1BH)*
#28 (1CH)*
*: Interrupt number
54
Input capture interrupt
request signal
MB90670/675 Series
8. Output Compare (OCU)
The output compare (OCU) is two sets of compare units consisting of four-channel OCU compare data registers,
a comparator and a control register.
An interrupt request can be generated for each channel upon a match detection by performing time-division
comparison between the OCU compare data register setting value and the counter value of the 24-bit free-run
timer.
The DOT pin can be used as a waveform output pin for reversing output upon a match detection or a generalpurpose output port for directly outputting the setting value of the DOT bit.
(1) Register Configuration
• OCU control register 00 upper digits (CCR00 : H)
Address
000059H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . . bit 0
—
—
—
—
MD3
MD2
MD1
MD0
—
—
—
—
R/W
R/W
R/W
R/W
(CCR00 : L)
Initial value
- - - - 0000 B
• OCU control register 00 lower digits (CCR00 : L)
Address
bit 15. . . . . . . . . . . . bit 8
000058H
(CCR00 : H)
bit 7
bit 6
bit 5
RESV RESV RESV
R/W
R/W
R/W
bit 4
bit 3
RESV
CPE3
R/W
R/W
bit 2
bit 1
CPE2 CPE1
R/W
R/W
bit 0
Initial value
CPE0
11110000B
R/W
• OCU control register 01 upper digits (CCR01 : H)
Address
bit 15
bit 14
bit 13
bit 12
00005BH
bit 11
bit 10
ICE3
ICE2
ICE1
ICE0
IC3
IC2
R/W
R/W
R/W
R/W
R/W
R/W
bit 8 bit 7 . . . . . . . . . . . . . bit 0
Initial value
IC1
IC0
00000000B
R/W
R/W
bit 9
(CCR01 : L)
• OCU control register 01 lower digits (CCR01 : L)
Address
bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
00005AH
(CCR01 : H)
—
—
—
—
DOT3
—
—
—
—
R/W
bit 2
bit 1
DOT2 DOT1
R/W
R/W
bit 0
Initial value
DOT0
- - - - 0000 B
R/W
R/W : Readable and writable
— : Unused
(Continued)
55
MB90670/675 Series
(Continued)
• OCU compare upper data register 0 to 7 (CPR00H to CPR07H)
Address
CPR00H : 000073H
CPR01H : 000077H
CPR02H : 00007BH
CPR03H : 00007FH
CPR04H : 000083H
CPR05H : 000087H
CPR06H : 00008BH
CPR07H : 00008FH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
—
—
—
—
—
—
—
—
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
CPR00H : 000072H
CPR01H : 000076H
CPR02H : 00007AH
CPR03H : 00007EH
CPR04H : 000082H
CPR05H : 000086H
CPR06H : 00008AH
CPR07H : 00008EH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000B
D23
D22
D21
D20
D19
D18
D17
D16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• OCU compare lower data register 0 to 7 (CPR00L to CPR07L)
Address
CPR00L : 000071H
CPR01L : 000075H
CPR02L : 000079H
CPR03L : 00007DH
CPR04L : 000081H
CPR05L : 000085H
CPR06L : 000089H
CPR07L : 00008DH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
D15
D14
D13
D12
D11
D10
D9
D8
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
CPR00L : 000070H
CPR01L : 000074H
CPR02L : 000078H
CPR03L : 00007CH
CPR04L : 000080H
CPR05L : 000084H
CPR06L : 000088H
CPR07L : 00008CH
bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000B
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
— : Unused
56
bit 6
MB90670/675 Series
(2) Block Diagram of Output Compare (OCU)
• Overall block diagram
Free-run timer data
4
Output compare unit
MATCH0 to MATCH3
23
T1 to T23
ICOMP0 to ICOMP3
Internal data bus
16
RB15 to RB0
4
OPEN
Output compare unit 00 to 03
(unit 0)
DOT0 to DOT3
EXT0 to EXT3
4
Interrupt request
(ICOMP0 to ICOMP3)
Pin
P70/DOT0 to P73/DOT3
MATCH4 to MATCH7
T1 to T23
16
4
4
ICOMP4 to ICOMP7
RB15 to RB0
Output compare unit 04 to 07
(unit 1)
DOT4 to DOT7
EXT0 to EXT3
4
Interrupt request
(ICOMP4 to ICOMP7)
Pin
P74/DOT4 to P77/DOT7
57
MB90670/675 Series
• Block diagram of unit 0
OCU control register 00 (CCR00)
—
—
—
—
MD3 MD2 MD1 MD0 RESV RESV RESV RESV CPE3 CPE2 CPE1 CPE0
4
Match operation enabled
4
General-purpose port/
compare pin switching
Compare circuit
24-bit free-run timer
bit 23 to bit 2
T1
MATCH0 to MATCH3
(to unit 1)
Output
control circuit
T0
2
Compare
control
Clock
selector
4
Compare control block
Match
signal
4
4
Internal data bus
Data latch
P73/DOT3
Pin
CPR00H
CPR00L
CPR01H
CPR01L
P72/DOT2
Pin
CPR02H
Output
latch
P71/DOT1
Pin
CPR02L
P70/DOT0
CPR03H
CPR03L
Pin
OCU compare data register 0 to 3
ICE3 ICE2 ICE1 ICE0 IC3
IC2
IC1
IC0
—
—
—
— DOT3 DOT2 DOT1 DOT0
OCU control register 01 (CCR01)
#15 (0FH)*
#16 (10H)*
#17 (11H)*
#18 (12H)*
*: Interrupt number
58
Output compare
interrupt request signal
MB90670/675 Series
• Block diagram of unit 1
OCU control register10 (CCR10)
—
—
—
—
MD3 MD2 MD1 MD0 SEL3 SEL2 SEL1 SEL0 CPE3 CPE2 CPE1 CPE0
4
4
4
General-purpose port/compare pin switching
MATCH0 to MATCH3
4
(from unit 0)
Output control circuit
Factor
selector
4
Compare circuit
24-bit free-run timer
bit 23 to bit 2
T1
Match
operation
enabled
2
T0
Compare
control
4
Compare control block
Internal data bus
Match
signal
4
Clock
selector
4
Data latch
P77/DOT7
Pin
CPR04H
CPR04L
CPR05H
CPR05L
P76/DOT6
Pin
CPR06H
CPR06L
CPR07H
CPR07L
Output
latch
P75/DOT5
Pin
P74/DOT4
Pin
OCU compare data register 4 to 7
ICE3 ICE2 ICE1 ICE0 IC3
IC2
IC1
IC0
—
—
—
— DOT3 DOT2 DOT1 DOT0
OCU control register 11 (CCR11)
#19 (13H)*
#20 (14H)*
#21 (15H)*
Output compare
interrupt request signal
#22 (16H)*
*: Interrupt number
59
MB90670/675 Series
9. I2C Interface (Included Only in MB90675 Series)
The I2C interface is a serial I/O port supporting Inter IC BUS operating as master/slave devices on I2C bus and
has the following features.
• Master/slave transmission/reception
• Arbitration function
• Clock synchronization function
• Slave address/general call address detection function
• Transmission direction detection function
• Repeated generation function start condition and detection function
• Bus error detection function
(1) Register Configuration
• I2C bus status register (IBSR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
(IBCR)
000040H
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
00000000B
R
R
R
R
R
R
R
R
• I2C bus control register (IBCR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . bit 0
Initial value
000041H
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
(IBSR)
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• I2C bus clock control register (ICCR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
000042H
(IADR)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
—
—
EN
CS4
CS3
CS2
CS1
CS0
--0XXXXXB
—
—
R/W
R/W
R/W
R/W
R/W
R/W
• I2C address register (IADR)
Address
000043H
(IADR)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7 . . . . . . . . . . . . bit 0
Initial value
—
A6
A5
A4
A3
A2
A1
A0
(ICCR)
-XXXXXXXB
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
000044H
(Reserved area)
D7
(IDAR)
R/W
R/W:
R :
—:
X :
60
Readable and writable
Read only
Unused
Indeterminate
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MB90670/675 Series
(2) Block Diagram
Internal data bus
I2C bus status register
(IBSR)
Start stop condition
generation circuit
General call
Slave
Transmit/receive
Last bit
Repeat start
Transmission
enable flag
Interrupt enable
GC-ACK enable
ACK enable
BB RSC AL LRB TRX AAS GCA FBT
Detection of first byte
Number of interrupt request
generated
Master
Start
Error
BER BEIE SCC MSS ACK GCAA INTE INT
Bus busy
I2C bus control register
(IBCR)
Start stop condition
detection circuit
Interrupt request signal
#38 (26H)*
SDA line
CCL line
Pin
P90/SDA
I2C enable
Pin
IDAR register
P91/SCL
Arbitration lost
detection circuit
Slave address
comparison circuit
IADR register
Clock control block
Sync
Clock diCount
vider 1 4
clock
(1/5 to 1/
selector 1
8)
φ
Clock
divider 2
8
Count
clock
selector 2
Shift clock
generation
circuit
I2C enable
—
—
EN CS4 CS3 CS2 CS1 CS0
I2C bus clock control register
(ICCR)
φ:Machine clock frequency
*:Interrupt number
61
MB90670/675 Series
10. UART0
UART0 is a general-purpose serial data communication interface for performing synchronous or asynchronous
communication (start-stop synchronization system). In addition to the normal duplex communication function
(normal mode), UART0 has a master/slave type communication function (multi-processor mode).
• Data buffer: Full-duplex double buffer
• Transfer mode: Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
• Baud rate: With dedicated baud rate generator, selectable from 12 types
External clock input possible
Internal clock (a clock supplied from 16-bit reload timer can be used.)
• Data length: 7 bits to 9 bits selective (with a parity bit)
6 bits to 8 bits selective (without a parity bit)
• Signal format: NRZ (Non Return to Zero) system
• Reception error detection:Framing error
Overrun error
Parity error (not available in multi-processor mode)
• Interrupt request: Receive interrupt (reception complete, receive error detection)
Receive interrupt (transmission complete)
Transmit/receive conforms to extended intelligent I/O service (EI2OS)
• Master/slave type communication function (multi-processor mode): 1 (master) to n (slave) communication
possible
(1) Register Configuration
• Status register 0 (USR0)
Address
000021H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . . bit 0
PE
TDRE
RIE
TIE
RBF
TBF
R/W
R/W
R/W
R/W
R/W
R/W
RDRF ORFE
R/W
R/W
(UMC0)
Initial value
00100000B
• Mode control register 0 (UMC0)
Address
bit 15. . . . . . . . . . . . bit 8 bit 7
(USR0)
000020H
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
00000100B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Rate and data register 0 (URD0)
bit 8 bit 7 . . . . . . . . . . . . . bit 0
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
000023H
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(UIDR0/UODR0)
Initial value
00000000B
• Input data register 0 (UIDR0)
Address
000022H
. 9 bit 8
bit 15. . . . bit
(URD0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D8
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D8
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
W
Initial value
XXXXXXXXB
• Output data register 0 (UODR)
Address
000022H
. 9 bit 8
bit 15. . . . bit
(URD0)
R/W : Readable and writable
R : Read only
W: Write only
X : Indeterminate
62
Initial value
XXXXXXXXB
MB90670/675 Series
(2) Block Diagram
Control bus
Dedicated baud
rate generator
Transmit
Clock
selector
16-bit reload
timer 0
Receive
interrupt signal
#39 (27H)*
Transmit
interrupt signal
#36 (24H)*
Receive
clock
Receive
control circuit
Transmit
control circuit
Pin
P42/SCK0
Start bit
detection circuit
Transmit start
circuit
Receive bit
counter
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Pin
P42/SOT0
Shift register for
reception
Pin
Shift register for
transmission
P40/SIN0
Reception
complete
UIDR0
Start transmission
UODR0
Receive condition
decision circuit
To EI2OS reception
error generation
signal (to CPU)
Internal data bus
UMC0
register
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
USR0
register
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
URD0
register
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
*: Interrupt number
63
MB90670/675 Series
11. UART1 (SCI)
UART1 (SCI) is a general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization system). In addition to the normal duplex communication
function (normal mode), UART1 has a master-slave type communication function (multi-processor mode).
• Data buffer: Full-duplex double buffer
• Transfer mode: Clock synchronized (no start or stop bit)
Clock asynchronized (start-stop synchronization system)
• Baud rate: With dedicated baud rate generator, selectable from 8 types
External clock input possible
Internal clock (a internal clock supplied from 16-bit reload timer can be used.)
• Data length: 7 bits (for asynchronous normal mode only)
8 bits
• Signal format: NRZ (Non Return to Zero) system
• Reception error detection:Framing error
Overrun error
Parity error (not available in multi-processor mode)
• Interrupt request: Receive interrupt (reception complete, receive error detection)
Receive interrupt (transmission complete)
Transmit/receive conforms to extended intelligent I/O service (EI2OS)
• Master/slave type communication function (multi-processor mode):1 (master) to n (slave) communication possible (supported only for master station)
(1) Register Configuration
• Control register 1 (SCR1)
Address
000025H
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
PEN
P
SBL
R/W
R/W
R/W
CL
A/D
bit 8 bit 7 ............ bit 0
REC RXE TXE
R/W R/W R/W R/W
(SMR1)
Initial value
00000100B
R/W
• Mode register 1 (SMR1)
Address
bit 15 ............ bit 8 bit 7
(SCR1)
000024H
• Status register 1 (SSR1)
Address
000027H
bit 6 bit 5
bit 4
bit 3
bit 0
Initial value
MD1 MD0 CS2
CS1
CS0 BCH SCKE SOE
00000000B
R/W
R/W R/W R/W
R/W R/W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
PE
R
ORE FRE RDRF TDRE
R
R
R
R
bit 2
bit 1
R/W
R/W
bit 8 bit 7 ............ bit 0
Initial value
00001-00B
—
RIE
TIE
—
R/W
R/W
(SIDR1/SODR1)
• Input data register 1 (SIDR1)
Address
000026H
bit 15 ............ bit 8 bit 7
(SSR1)
• Output data register 1 (SODR1)
Address
000026H
bit 3
bit 2
bit 1
bit 0
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
bit 4
bit 3
bit 2
bit 1
bit 0
bit 15 ............ bit 8 bit 7
(SSR1)
R/W : Readable and writable
R : Read only
W : Write only
— : Unused
X : Indeterminate
64
bit 4
D7
bit 6 bit 5
bit 6 bit 5
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
MB90670/675 Series
(2) Block Diagram
Control bus
Transmit
clock
Dedicated baud
rate generator
Clock
selector
16-bit reload
timer 1
Receive
interrupt signal
#37 (25H)*
Transmit
interrupt signal
#35 (23H)*
Receive
clock
Pin
P45/SCK1
Transmit
control circuit
Receive
control circuit
Start bit
detection circuit
Transmit start
circuit
Receive bit
counter
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Pin
P44/SOT1
Shift register for
reception
Pin
Shift register for
transmission
P43/SIN1
Reception
complete
Start transmission
SODR1
SIDR1
Receive condition
decision circuit
To EI2OS reception
error generation
signal (to CPU)
Internal data bus
SMR1
register
MD1
MD0
CS2
CS1
CS0
BCH
SCKE
SOE
SCR1
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR1
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
*: Interrupt number
65
MB90670/675 Series
12. DTP/External Interrupt Circuit
The DTP (Data Transfer Peripheral)/external interrupt circuit is located between peripheral equipment connected
externally and the F2MC-16L CPU and transmits interrupt requests or data transfer requests generated by
peripheral equipment to the CPU, generates external interrupt request and starts the extended intelligent I/O
service (EI2OS).
(1) Register Configuration
• DTP/interrupt factor register (EIRR)
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
—
—
—
—
ER3
ER2
ER1
ER0
—
—
—
—
R/W
R/W
R/W
R/W
Address bit 15
000029H
(ENIR)
Initial value
- - - - 0000 B
• DTP/interrupt enable register (ENIR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
—
—
—
—
EN3
EN2
EN1
EN0
—
—
—
—
R/W
R/W
R/W
R/W
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00002AH
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000028H
(EIRR)
Initial value
- - - - 0000 B
• Request level setting register (ELVR)
(Vacancy)
R/W : Readable and writable
— : Unused
66
MB90670/675 Series
(2) Block Diagram
Request level setting register (ELVR)
LB3
LA3
LB2
2
LA2
LB1
LA1
LB0
LA0
2
2
Pin
2
P60/INT0
Level edge
selector 3
Level edge
selector 1
Level edge
selector 2
Level edge
selector 0
Pin
Internal data bus
P61/INT1
DTP/external interrupt input
detection circuit
Pin
P62/INT2
Pin
P63/INT3
DTP/interrupt factor register
(EIRR)
—
—
—
—
ER3
ER2
ER1
ER0
Interrupt request signal
#14 (0EH)*
#13 (0DH)*
#14 (0CH)*
DTP/interrupt enable register
(ENIR)
—
—
—
—
#11 (0BH)*
EN3
EN2
EN1
EN0
*: Interrupt signal
67
MB90670/675 Series
13. Wake-up Interrupt
Wake-up interrupts transmits interrupt request (“L” level) generated by peripheral device located between external peripheral devices and the F2MC-16L CPU to the CPU and invokes interrupt processing.
The interrupt does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
• Wake-up interrupt flag register (EIFR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
00000FH
—
—
—
—
—
—
—
WIF
—
—
—
—
—
—
—
R/W
bit 8 bit 7 . . . . . . . . . . . . bit 0
Initial value
- - - - - - -0B
(Vacancy)
• Wake-up interrupt enable register (EICR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
00001FH
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(Vacancy)
Initial value
00000000B
R/W : Readable and writable
— : Unused
(2) Block Diagram
Internal data bus
Wake-up interrupt
enable register (EICR)
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
Wake-up interrupt flag
register (EIFR)
—
—
—
—
—
—
—
WIF
Interrupt request detection circuit
P10/AD08/WI0
Pin
P11/AD09/WI1
Pin
P12/AD10/WI2
Pin
P13/AD11/WI3
Pin
P14/AD12/WI4
Pin
P15/AD13/WI5
Pin
P16/AD14/WI6
Pin
P17/AD15/WI7
Pin
*: Interrupt number
68
Wake-up interrupt
request
#33 (21H)*
MB90670/675 Series
14. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks for development on a realtime
operating system (REALOS software). The module can be used to generate hardware interrupt requests to the
CPU with software and cancel the interrupt requests.
This module does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
• Delayed interrupt factor generation/cancellation register (DIRR)
bit 8 bit 7 . . . . . . . . . . . . bit 0
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
00009FH
—
—
—
—
—
—
—
R0
—
—
—
—
—
—
—
R/W
(Reserved area)
Initial value
- - - - - - -0B
R/W : Readable and writable
— : Unused
(2) Block Diagram
Internal data bus
—
—
—
—
—
Delayed interrupt factor generation/
cancellation register (DIRR)
—
—
R0
S factor
R latch
Interrupt request signal
#42 (2AH)*
*: Interrupt signal
69
MB90670/675 Series
15. 8/10-bit A/D Converter
The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input
voltage) to digital values (A/D conversion) and has the following features.
• Minimum conversion time: 6.13 µs (at machine clock of 16 MHz, including sampling time)
• Minimum sampling time: 3.75 µs (at machine clock of 16 MHz)
• Conversion method: RC successive approximation method with a sample and hold circuit.
• Resolution: 10-bit or 8-bit selective
• Analog input pins: Selectable from eight channels by software
One-shot conversion mode:Stops conversion after completing a conversion for a stopped channel (one
channel only) or for successive channels (maximum of eight channels can be
specified)
Continuous conversion mode:Continues conversions for a specified channel (one channel only) or for
successive channels (maximum of eight channels can be specified)
Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next
activation.
• Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the
end of A/D conversion.
• When interrupts are enabled, there is no loss of data even in continuous operations because the conversion
data protection function is in effect.
• Starting factors for conversion:Selected from software activation, 16-bit reload timer 1 output (rising edge),
and external trigger (falling edge).
(1) Register Configuration
• A/D control status register upper digits (ADCS: H)
bit 8 bit 7 . . . . . . . . . . . . bit 0
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
00002DH
BUSY
INT
INTE
PAUS
STS1
STS0
STRT RESV
R/W
R/W
R/W
R/W
R/W
R/W
W
(ADCS: L)
Initial value
00000000B
R/W
• A/D control status register lower digits (ADCS: L)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00002CH
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(ADCS: H)
• A/D data register (ADCR)
Address
00002EH
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
—
—
—
—
—
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W —
S10
—
—
—
—
R
R
R
R
R
R
R
R
R
R
R/W : Readable and writable
R : Read only
W: Write only
—: Unused
X : Indeterminate
70
Initial value
XXXXXXXXB
0000000XB
MB90670/675 Series
(2) Block Diagram
A/D control status
register (ADCS)
BUSY
Interrupt request signal #31 (1FH)*
INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
6
2
P47/ATG
TO
Decoder
Internal data bus
Clock selector
φ
Comparator
P57/AN7
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P51/AN1
P50/AN0
A/D data register
S10
(ADCR)
—
Sample hold
circuit
Control circuit
Analog
channel
selector
AVR
AVCC
AVSS
—
—
—
—
D9
D8
D/A converter
D7
D6
D5
D4
D3
D2
D1
D0
φ : Machine clock frequency
TO : 16-bit reload timer channel 1 output
* : Interrupt number
71
MB90670/675 Series
16. Low-power Consumption (Standby) Mode
The F2MC-16L has the following CPU operating mode configured by selection of an operating clock and clock
operation control.
• Clock mode
PLL clock mode: A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation
clock (HCLK).
Main clock mode: A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the
oscillation clock (HCLK).
The PLL multiplication circuits stops in the main clock mode.
• CPU intermittent operation mode
The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU
intermittently while external bus and peripheral functions are operated at a high-speed.
• Hardware stand-by mode
The hardware standby mode is a mode for reducing power consumption by stopping clock supply (sleep mode)
to the CPU by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral
functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode).
Of these modes, modes other than the PLL clock mode are power consumption modes.
(1) Register Configuration
• Clock select register (CKSCR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8 bit 7 . . . . . . . . . . . . bit 0
0000A1H
RESV
MCM
WS1
WS0
RESV
MCS
CS1
CS0
R/W
R
R/W
R/W
R/W
R/W
W
R/W
(LPMCR)
Initial value
11111100 B
• Low-power consumption mode control register (LPMCR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0000A0H
STP
SLP
SPL
RST
RESV
CG1
CG0
RESV
W
W
R/W
W
R/W
R/W
R/W
R/W
(CKSCR)
R/W : Readable and writable
R : Read only
W : Write only
72
Initial value
00011000 B
MB90670/675 Series
(2) Block Diagram
Low-power consumption mode control register (LPMCR)
STP
SLP
SPL
RST RESV CG1
CG0 RESV
Pin
high-impedance
control circuit
RST
Internal reset
generation
circuit
Pin
CPU intermittent
operation
selector
RST
Standby control
circuit
2
Cancellation of interrupt
HST
Internal reset
Select intermittent cycle
CPU clock
control circuit
Cancellation of reset
Pin Hi-z control
CPU clock
Stop and sleep signal
Pin
Stop signal
Machine clock
Peripheral clock
control circuit
Cancellation of
oscillation
stabilization time
Clock
generation
block
Clock selector
Peripheral clock
Oscillation
stabilization
time selector
2
2
PLL multiplication
circuit
System clock
generation
circuit
X0
X1
Pin
RESV MCM WS1
WS0 RESV MCS
CS1
CS0
Clock selection register (CKSCR)
Divided
-by-2
Main clock
Divided
-by-2048
Divided
-by-4
Divided
-by-4
Divided
-by-8
Timebase timer
Pin
73
MB90670/675 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 7.0
V
AVCC
VSS – 0.3
VSS + 7.0
V
*1
AVRH,
AVRL
VSS – 0.3
VSS + 7.0
V
*1
Input voltage
VI
VSS – 0.3
VCC + 0.3
V
*2
Output voltage
VO
VSS – 0.3
VCC + 0.3
V
*2
“L” level maximum output current
IOL

15
mA
*3
“L” level average output current
IOLAV

4
mA
*4
“L” level total maximum output current ΣIOL

100
mA
Power supply voltage
“L” level total average output current
ΣIOLAV

50
mA
*5
“H” level maximum output current
IOH

–15
mA
*3
“H” level average output current
IOHAV

–4
mA
*4
“H” level total maximum output current ΣIOH

–100
mA
“H” level total average output current
ΣIOHAV

–50
mA
Power consumption
PD

400
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
*5
*1:AVCC shall never exceed VCC. AVRH shall never exceed VCC and AVCC. Also, AVRL shall never exceed VCC, AVCC
and AVRH.
*2:VI and VO shall never exceed VCC + 0.3 V.
*3:The maximum output current is a peak value for a corresponding pin.
*4:Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5:Total average current is an average current value observed for a 100 ms period for all corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
74
MB90670/675 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
Operating temperature
Symbol
Value
Unit
Remarks
Min.
Max.
VCC
2.7
5.5
V
Normal operation
VCC
2.0
5.5
V
Retains status at the time of operation stop
TA
–40
+85
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
75
MB90670/675 Series
3. DC Characteristics
Parameter Symbol
Pin name
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
VIH
Pins other than VIHS
and VIHM
0.7 VCC
—
VCC + 0.3
V
VIHS
Hysteresis input pins
P24 to P27, P40 to
P47,
P60 to P67, P70 to
P77,
P80, HST, RST
0.8 VCC
—
VCC + 0.3
V
MB90670
series
VIHS
Hysteresis input pins
P24 to P27, P40 to
P47,
P60 to P67, P70 to
P77,
P80 to P86, HST,
RST,
P90, P91, PA0 to
PA7,
PB0 to PB2
0.8 VCC
—
VCC + 0.3
V
MB90675
series
VIHM
MD pin input
VCC – 0.3
—
VCC + 0.3
V
VIL
Pins other than VILS
and VILM
VSS – 0.3
—
0.3 VCC
V
VILS
Hysteresis input pins
P24 to P27, P40 to
P47,
P60 to P67, P70 to
P77,
P80, HST, RST
VSS – 0.3
—
0.2 VCC
V
MB90670
series
VILS
Hysteresis input pins
P24 to P27, P40 to
P47,
P60 to P67, P70 to
P77,
P80 to P86, HST,
RST,
P90, P91, PA0 to
PA7,
PB0 to PB2
VSS – 0.3
—
0.2 VCC
V
MB90675
series
VILM
MD pin input
VSS – 0.3
—
VSS + 0.3
V
“H” level input voltage
“L” level input voltage
—
VOH
“H” level
output voltage
VOH
Other than P50 to P57
VCC = 4.5 V
VCC – 0.5
IOH = –4.0 mA
—
—
V
Other than P50 to P57
VCC = 2.7 V
VCC – 0.3
IOH = –1.6 mA
—
—
V
VOL
“L” level
output voltage
VOL
All output pins
VCC = 4.5 V
IOL = 4.0 mA
—
—
0.4
V
All output pins
VCC = 2.7 V
IOL = 2.0 mA
—
—
0.4
V
—
0.1
10
µA
Open-drain
output leak- Ileak
age current
P50 to P57, P90,
P91*1
—
(Continued)
76
MB90670/675 Series
(Continued)
Parameter Symbol
Input leakIIL
age current
Pin name
Other than P50 to
P57, P90 and P91
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
VCC = 5.5 V
VSS < VI < VCC
–10
—
10
µA
Pull-up resistance
R
—
VCC = 5.0 V
25
45
100
kΩ
R
—
VCC = 3.0 V
40
95
200
kΩ
Pull-down
resistance
R
—
VCC = 5.0 V
25
50
200
kΩ
R
—
VCC = 3.0 V
40
100
400
kΩ
—
Internal operation at
16 MHz
VCC at 5.0 V
—
50
70
mA
Normal operation*2
—
Internal operation at
16 MHz
VCC at 5.0 V
—
10
30
mA
In sleep
mode*2
—
Internal operation at
8 MHz
VCC at 3.0 V
—
12
20
mA
Normal operation*2
—
Internal operation at
8 MHz
VCC at 3.0 V
—
2.5
10
mA
In sleep
mode*2
In stop
mode and
hardware
standby
mode*2
ICC
ICCS
Power sup- ICC
ply current
ICCS
ICCH
Input capacitance
CIN
—
TA = +25°C
Other than AVCC,
AVSS, VCC, VSS
—
—
0.1
10
µA
—
10
—
pF
*1: Only MB90675 series has P90 and P91 pins.
*2: The current value is preliminary value and may be subject to change for enhanced characteristics without
previous notice.
77
MB90670/675 Series
4. AC Characteristics
(1) Reset Input Timing, Hardware Standby Input Timing
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
Remarks
Parameter
Min.
Max.
tRSTL
RST
Hardware standby input time tHSTL
HST
Reset input time
—
16 tCP*
—
ns
16 tCP*
—
ns
*: For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
tRSTL, tHSTL
RST
HST
0.2 VCC
• Measurement conditions for AC ratings
Pin
CL
CL is a load capacitance connected to a pin under test.
CLK, ALE: CL = 30 pF
Address data bus (AD15 to AD00), RD, WR: CL = 80 pF
78
0.2 VCC
MB90670/675 Series
(2)Specification for Power-on Reset
Parameter
Symbol Pin name
Power supply rising time
tR
VCC
Power supply cut-off time
tOFF
VCC
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Min.
Max.
—
30
ms *
Due to repeated
1
—
ms
operations
Condition
—
*: VCC must be kept lower than 0.2 V before power-on.
Notes : • The above ratings are values for causing a power-on reset.
• When HST is set to “L” level, apply power according to this table to cause a power-on reset irrespective of
whether or not a power-on reset is required.
• For built-in resources in the device, re-apply power to the resources to cause a power-on reset.
• There are internal registers which can be initialized only by a power-on reset. Apply power according to this
rating to ensure initialization of the registers.
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to raise the voltage
smoothly to suppress fluctuations as shown below.
Main power
supply voltage
VCC
It is recommended to keep the rising
Sub power supply voltage
VSS
RAM data retained
speed of the supply voltage at 50 mV/ms
or slower.
79
MB90670/675 Series
(3) Clock Timing
• Operation at 5.0 V ± 10%
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
Remarks
Parameter
Min.
Typ. Max.
Clock frequency
FC
X0, X1
3
—
32
MHz
X0, X1
31.25
—
333
ns
Clock cycle time
tC
Recommended
PWH,
Input clock pulse width
X0
10
—
—
ns duty ratio of
PWL
30% to 70%
tCR,
Input clock rising/falling time
X0
—
—
5
ns
—
tCF
Internal operating clock frefCP
—
1.5
—
16
MHz
quency
Internal operating clock cycle
tCP
—
62.5
—
666
ns
time
Frequency fluctuation rate
∆f
P37/CLK
—
—
3
% *
locked
*: The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is locked.
+
+α
∆f = | α | × 100 (%)
fO
Center frequency fO
–α
–
The PLL frequency deviation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC)”,
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
80
MB90670/675 Series
• Operation at VCC = 2.7 V (minimum value)
Symbol Pin name
Parameter
Clock frequency
Clock cycle time
FC
tC
X0, X1
X0, X1
Input clock pulse width
PWH,
PWL
X0
Input clock rising/falling time
tCR,
tCF
X0
Internal operating clock frefCP
quency
Internal operating clock cycle
tCP
time
Frequency fluctuation rate
∆f
locked
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Min.
Typ. Max.
3
—
16
MHz
62.5
—
333
ns
Recommended
20
—
—
ns duty ratio of
30% to 70%
Condition
—
—
5
ns
—
1.5
—
8
MHz
—
125
—
666
ns
P37/CLK
—
—
3
%
—
*
*: The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is locked.
+
+α
|α|
∆f =
× 100 (%)
fO
Center frequency fO
–α
–
The PLL frequency deviation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC)”,
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
81
MB90670/675 Series
• Clock timing
tC
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
PWH
0.2 VCC
PWL
tCF
tCR
• PLL operation guarantee range
Relationship between internal operating clock frequency and power supply voltage
Power supply voltage VCC
(V)
5.5
4.5
Normal operation
range
PLL operation
guarantee range
3.3
2.7
1.5
3
8
Internal clock fCP
16
(MHz)
Relationship between clock frequency and internal operating clock frequency
(MHz)
Multiplied-by-4
Multiplied-by-3
Internal clock fCP
Multipliedby-2
34
8
Not multiplied
Multiplied-by-1
16
24
32
(MHz)
Oscillation clock FC
Note : The operation guarantee range on the lower voltage is 2.7 V for the evaluation chips.
The AC ratings are measured for the following measurement reference voltages.
• Input signal waveform
• Output signal waveform
Hystheresis input pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
Pins other than hystheresis input/MD input
0.7 VCC
0.3 VCC
82
Output pin
MB90670/675 Series
(4) Recommended Resonator Manufacturers
• Sample application of piezoelectric resonator (FAR family)
X0
X1
R
FAR*1
C1*2
C2*2
*1: FUJITSU MEDIA DEVICES Acoustic Resonator
FAR part number
(built-in capacitor type)
FAR-C4
FAR-C4
FAR-C4
FAR-C4
FAR-C4
FAR-C4
FAR-C4
FAR-C4
FAR-C4
C-2000- 20
A-4000- 01
B-4000- 02
B-4000- 00
B-8000- 02
B-12000- 02
B-16000- 02
B-20000-L14B
B-24000-L14A
Frequency
(MHz)
Dumping
resistor
2.00
4.00
4.00
4.00
8.00
12.00
16.00
20.00
24.00
510 Ω
—
—
—
—
—
—
—
—
Temperature charInitial deviation
acteristics of FAR
Loading caof FAR frequenfrequency
cy
pacitors*2
(TA = –20°C to
(TA = +25°C)
+60°C)
±0.5%
±0.5%
Built-in
±0.5%
±0.5%
Built-in
±0.5%
±0.5%
Built-in
±0.5%
±0.5%
Built-in
±0.5%
±0.5%
Built-in
±0.5%
±0.5%
Built-in
±0.5%
±0.5%
Built-in
±0.5%
±0.5%
Built-in
±0.5%
±0.5%
Built-in
Inquiry: FUJITSU MEDIA DEVICES LIMITED
83
MB90670/675 Series
• Sample application of ceramic resonator
X0
X1
R
*
C1
• Mask ROM product
Resonator
Resonator
manufacturer
KBR-2.0MS
PBRC-2.00A
KBR-4.0MSA
KBR-4.0MKS
PBRC4.00A
PBRC4.00B
KBR-6.0MSA
KBR-6.0MKS
Kyocera
PBRC6.00A
Corporation
PBRC6.00B
KBR-8.0M
PBRC8.00A
PBRC8.00B
KBR-10.0M
PBRC10.00B
KBR-12.0M
PBRC-12.00B
CSA2.00MG040
CST2.00MG040
CSA4.00MG040
CST4.00MGW040
Murata
Mfg. Co., Ltd.
CSA6.00MG
CST6.00MGW
CSA8.00MTZ
CST8.00MTW
C2
Frequency
(MHz)
C1 (pF)
C2 (pF)
R
2.00
2.00
4.00
4.00
4.00
4.00
6.00
6.00
6.00
6.00
8.00
8.00
8.00
10.00
10.00
12.00
12.00
2.00
2.00
4.00
4.00
6.00
6.00
8.00
8.00
150
150
33
Built-in
33
Built-in
33
Built-in
33
Built-in
33
33
Built-in
33
Built-in
33
Built-in
100
Built-in
100
Built-in
30
Built-in
30
Built-in
150
150
33
Built-in
33
Built-in
33
Built-in
33
Built-in
33
33
Built-in
33
Built-in
33
Built-in
100
Built-in
100
Built-in
30
Built-in
30
Built-in
Not required
Not required
680 Ω
680 Ω
680 Ω
680 Ω
Not required
Not required
Not required
Not required
560 Ω
Not required
Not required
330 Ω
680 Ω
330 Ω
680 Ω
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
(Continued)
84
MB90670/675 Series
(Continued)
Resonator
manufacturer
Murata
Mfg. Co., Ltd.
TDK Corporation
Resonator
CSA10.0MTZ
CST10.0MTW
CSA12.0MTZ
CST12.0MTW
CSA16.00MXZ040
CST16.00MXW0C3
CSA20.00MXZ040
CSA24.00MXZ040
CST24.00MXW0H1
CSA32.00MXZ040
CST32.00MXW040
FCR4.0MC5
Frequency
(MHz)
10.00
10.00
12.00
12.00
16.00
16.00
20.00
24.00
24.00
32.00
32.00
4.00
C1 (pF)
C2 (pF)
R
30
Built-in
30
Built-in
15
Built-in
10
5
Built-in
5
Built-in
Built-in
30
Built-in
30
Built-in
15
Built-in
10
5
Built-in
5
Built-in
Built-in
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
Not required
C1 (pF)
C2 (pF)
R
Built-in
Built-in
30
30
Built-in
Built-in
Built-in
Built-in
30
30
Built-in
Built-in
Not required
Not required
Not required
Not required
Not required
Not required
• One-time product
Resonator
manufacturer
Murata
Mfg. Co., Ltd.
TDK Corporation
Resonator
CSTCS4.00MG0C5
CST8.00MTW
CSACS8.00MT
CSA10.0MTZ
CST10.0MTW
FCR4.0MC5
Frequency
(MHz)
4.0
8.00
8.00
10.00
10.00
4.00
Inquiry:Kyocera Corporation
•AVX Corporation
North American Sales Headquarters: TEL 1-803-448-9411
•AVX Limited
European Sales Headquarters: TEL 44-1252-770000
•AVX/Kyocera H.K. Ltd.
Asian Sales Headquarters: TEL 852-363-3303
Murata Mfg. Co., Ltd.
•Murata Electronics North America, Inc.: TEL 1-404-436-1300
•Murata Europe Management GmbH: TEL 49-911-66870
•Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
TDK Corporation
•TDK Corporation of America
Chicago Regional Office: TEL 1-708-803-6100
•TDK Electronics Europe GmbH
Components Division: TEL 49-2102-9450
•TDK Singapore (PTE) Ltd.: TEL 65-273-5022
•TDK Hongkong Co., Ltd.: TEL 852-736-2238
•Korea Branch, TDK Corporation: TEL 82-2-554-6633
85
MB90670/675 Series
(5) Clock Output Timing
(AVCC = VCC = 2.7 V to 5.5V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Remarks
Parameter
Min.
Max.
Cycle time
tCYC
CLK
—
1 tCP*
—
ns
tCHCL
CLK
VCC = 5.0 V ± 10 % 1 tCP*/2 – 20 1 tCP*/2 + 20 ns 5.0 V ± 10 % is ± 20
CLK ↑ → CLK ↓
tCHCL
CLK
VCC = 3.0 V ± 10 % 1 tCP*/2 – 35 1 tCP*/2 + 35 ns 3.0 V ± 10 % is ± 35
*: For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
tCYC
tCHCL
CLK
2.4 V
2.4 V
0.8 V
86
MB90670/675 Series
(6) Bus Read Timing
Parameter
Symbol
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
tLHLL
ALE
VCC = 5.0 V ±10% 1 tCP*/2 – 20
—
ns
tLHLL
ALE
VCC = 3.0 V ±10% 1 tCP*/2 – 35
—
ns
tAVLL
AD15 to AD00 VCC = 5.0 V ±10% 1 tCP*/2 – 25
—
ns
tAVLL
AD15 to AD00 VCC = 3.0 V ±10% 1 tCP*/2 – 40
—
ns
ALE ↓ → address effectLLAX
tive time
AD15 to AD00
1 tCP*/2 – 15
—
ns
Effective address → RD
tAVRL
↓ time
AD15 to AD00
1 tCP* – 15
—
ns
ALE pulse width
Effective address →
ALE ↓ time
—
Effective address →
read data time
tAVDV
AD15 to AD00 VCC = 5.0 V ±10%
—
5 tCP*/2 – 60
ns
tAVDV
AD15 to AD00 VCC = 3.0 V ±10%
—
5 tCP*/2 – 80
ns
RD pulse width
tRLRH
RD
3 tCP*/2 – 20
—
ns
RD ↓ → read data time
tRLDV
AD15 to AD00 VCC = 5.0 V ±10%
—
3 tCP*/2 – 60
ns
tRLDV
AD15 to AD00 VCC = 3.0 V ±10%
—
3 tCP*/2 – 80
ns
RD ↑ → data hold time
tRHDX
AD15 to AD00
0
—
ns
RD ↑ → ALE ↑ time
tRHLH
RD, ALE
1 tCP*/2 – 15
—
ns
1 tCP*/2 – 10
—
ns
—
RD ↑ → address disaptRHAX
pear time
RD,
A19 to A16
Effective address →
CLK ↑ time
tAVCH
CLK,
A19 to A16
1 tCP*/2 – 20
—
ns
RD ↓ → CLK ↑ time
tRLCH
RD, CLK
1 tCP*/2 – 20
—
ns
—
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
87
MB90670/675 Series
tAVCH
tRLCH
2.4 V
2.4 V
CLK
tRHLH
2.4 V
0.8 V
2.4 V
tLHLL
ALE
tAVLL
2.4 V
tLLAX
tRLRH
RD
2.4 V
0.8 V
tAVRL
tRHAX
tRLDV
2.4 V
0.8 V
AD19 to AD16
2.4 V
0.8 V
tAVDV
AD15 to AD00
88
2.4 V
0.8 V
Address
2.4 V
0.8 V
0.7 VCC
0.3 VCC
Read data
tRHDX
0.7 VCC
0.3 VCC
MB90670/675 Series
(7) Bus Write Timing
Parameter
Symbol
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
Effective address → WR
tAVWL
↓ time
A19 to A00
WR pulse width
WR
tWLWH
Write data → WR ↑ time tDVWH
WR ↑ → data hold time
—
AD15 to AD00
1 tCP – 15
—
ns
3 tCP*/2 – 20
—
ns
3 tCP*/2 – 20
—
ns
tWHDX
AD15 to AD00 VCC = 5.0 V ±10%
20
—
ns
tWHDX
AD15 to AD00 VCC = 3.0 V ±10%
30
—
ns
1 tCP*/2 – 10
—
ns
1 tCP*/2 – 15
—
ns
1 tCP*/2 – 20
—
ns
WR ↑ → address disaptWHAX
pear time
A19 to A00
WR ↑ → ALE ↑ time
tWHLH
WRL, ALE
WR ↓ → CLK ↑ time
tWLCH
WRH, CLK
—
*: For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
WRL, WRH
2.4 V
0.8 V
tWHAX
A19 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
2.4 V
AD15 to AD00
0.8 V
Address
2.4 V
0.8 V
tWHDX
2.4 V
Write data
0.8 V
89
MB90670/675 Series
(8) Ready Input Timing
Parameter
RDY setup time
RDY hold time
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
tRYHS
RDY
VCC = 5.0 V ±10%
45
—
ns
tRYHS
RDY
VCC = 3.0 V ±10%
70
—
ns
tRYHH
RDY
—
0
—
ns
Note : Use the auto-ready function when the setup time for the rising of the RDY signal is not sufficient.
2.4 V
2.4 V
CLK
ALE
RD/WR
tRYHS
RDY
(WAIT inserted)
tRYHS
0.2 VCC
RDY
(WAIT inserted)
0.8 VCC
0.2 VCC
0.8 VCC
tRYHH
(9) Hold Timing
Parameter
Symbol
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
Pins in floating status →
tXHAL
HAK ↓ time
HAK
HAK ↑ → pin valid time
HAK
tHAHV
—
30
1 tCP*
ns
1 tCP*
2 tCP*
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
HAK
2.4 V
0.8 V
tXHAL
Pins
90
2.4 V
0.8 V
tHAHV
High impedance
2.4 V
0.8 V
MB90670/675 Series
(10) UART0 Timing
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Remarks
Parameter
Min.
Max.
Serial clock cycle time
tSCYC
—
—
8 tCP*
—
ns
—
VCC = 5.0 V ±10%
– 80
80
ns Internal shift
tSLOV
SCK ↓ → SOT delay
time
tSLOV
—
VCC = 3.0 V ±10%
– 120
120
ns clock mode
—
VCC = 5.0 V ±10%
100
—
ns CL = 80 pF
tIVSH
Valid SIN → SCK ↑
tIVSH
—
VCC = 3.0 V ±10%
200
—
ns + 1 TTL for an
output pin
SCK ↑ → valid SIN hold
tSHIX
—
1 tCP*
—
ns
time
Serial clock “H” pulse
tSHSL
—
—
4 tCP*
—
ns
width
Serial clock “L” pulse
—
4 tCP*
—
ns
tSLSH
External shift
width
tSLOV
—
VCC = 5.0 V ±10%
—
150
ns clock mode
SCK ↓ → SOT delay
time
—
VCC = 3.0 V ±10%
—
200
ns CL = 80 pF
tSLOV
+ 1 TTL for an
tIVSH
—
VCC = 5.0 V ±10%
60
—
ns
output pin
Valid SIN → SCK ↑
tIVSH
—
VCC = 3.0 V ±10%
120
—
ns
—
VCC = 5.0 V ±10%
60
—
ns
SCK ↑ → valid SIN hold tSHIX
time
tSHIX
—
VCC = 3.0 V ±10%
120
—
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
Notes : • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitor connected to pins while testing.
91
MB90670/675 Series
• Internal shift clock mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
2.4 VCC
2.4 VCC
0.8 VCC
0.8 VCC
• External shift clock mode
tSLSH
SCK
0.2 VCC
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tIVSH
SOT
2.4 V
0.2 V
tIVSH
SIN
92
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB90670/675 Series
(11) UART1 Timing
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Remarks
Parameter
Min.
Max.
Serial clock cycle time
tSCYC
—
—
8 tCP*
—
ns
—
VCC = 5.0 V ±10%
– 80
80
ns Internal shift
tSLOV
SCK ↓ → SOT delay
time
tSLOV
—
VCC = 3.0 V ±10%
– 120
120
ns clock mode
—
VCC = 5.0 V ±10%
100
—
ns CL = 80 pF
tIVSH
Valid SIN → SCK ↑
tIVSH
—
VCC = 3.0 V ±10%
200
—
ns + 1 TTL for an
output pin
SCK ↑ → valid SIN hold
tSHIX
—
1 tCP*
—
ns
time
Serial clock “H” pulse
tSHSL
—
—
4 tCP*
—
ns
width
Serial clock “L” pulse
—
4 tCP*
—
ns
tSLSH
External shift
width
tSLOV
—
VCC = 5.0 V ±10%
—
150
ns clock mode
SCK ↓ → SOT delay
time
—
VCC = 3.0 V ±10%
—
200
ns CL = 80 pF
tSLOV
+ 1 TTL for an
tIVSH
—
VCC = 5.0 V ±10%
60
—
ns
output pin
Valid SIN → SCK ↑
tIVSH
—
VCC = 3.0 V ±10%
120
—
ns
—
VCC = 5.0 V ±10%
60
—
ns
SCK ↑ → valid SIN hold tSHIX
time
tSHIX
—
VCC = 3.0 V ±10%
120
—
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
Notes : • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitor connected to pins while testing.
93
MB90670/675 Series
• Internal shift clock mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.2 V
tIVSH
SIN
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
SCK
0.2 VCC
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
94
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB90670/675 Series
(12) Timer Input Timing
Parameter
Input pulse width
Symbol
tTIWH,
tTIWL
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin name
Condition
Unit Remarks
Min.
Max.
TIN0, TON1
—
4 tCP*
—
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timing”.
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
TIN
tTIWH
tTIWL
(13) Timer Output Timing
Parameter
CLK ↑ → TOUT
transition time
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
TOT0, TOT1
VCC = 5.0 V ±10%
30
—
ns
tTO
tTO
TOT0, TOT1
VCC = 3.0 V ±10%
80
—
ns
2.4 V
CLK
TOUT
2.4 V
0.8 V
tTO
95
MB90670/675 Series
(14) I2C Timing
(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Remarks
Min.
Max.
fSCL
—
0
100
kHz
Parameter
SCL clock frequency
Bus free time between
tBUS
stop and start conditions
Hold time
(re-transmission) start
LOW status hold time of
SCL clock
HIGH status hold time of
SCL clock
Setup time for conditions
for starting re-transmission
Data hold time
Data setup time
Rising time of SDA and
SCL signals
Falling time of SDA and
SCL signals
Setup time for stop conditions
—
4.7
—
µs
tHDSTA
—
4.0
—
µs
tLOW
—
4.7
—
µs
tHIGH
—
4.0
—
µs
The first clock
pulse is generated after this
period.
—
tSUSTA
—
4.7
—
µs
tHDDAT
tSUDAT
—
—
0
250
—
—
µs
ns
tR
—
—
1000
ns
tF
—
—
300
ns
tSUSTO
—
4.0
—
µs
Note : Only MB90675 series has I2C.
0.8 VCC
0.2 VCC
SDA
tBUS
tLOW
tR
tF
tHDSTA
0.8 VCC
SCL
0.2 VCC
tHDSTA
tSUDAT
tHDDAT
96
tHIGH
fSCL
tSUSTA
tSUSTO
MB90670/675 Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, 2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Parameter
Min.
Typ.
Max.
Resolution
—
—
—
—
10
bit
Total error
—
—
—
—
±3.0
LSB
Linearity error
—
—
—
—
±2.0
LSB
Differential linearity error
—
—
—
—
±1.5
LSB
AVRL
AVRL
AVRL
—
AN0 to
Zero transition voltage
VOT
– 1.5
+ 0.5
+ 2.5
mV
AN7
LSB
LSB
LSB
AVRH
AVRH
AVRH
AN0 to
Full-scale transition voltage
VFST
– 4.5
– 1.5
+ 0.5
mV
AN7
LSB
LSB
LSB
VCC = 5.0 V ±10%
—
—
at machine clock of 6.125
—
—
µs
16 MHz
Conversion time
VCC = 3.0 V ±10%
—
—
at machine clock of 12.25
—
—
µs
8 MHz
AN0 to
Analog port input current
IAIN
—
0.1
10
µA
AN7
AN0 to
Analog input voltage
VAIN
AVRL
—
AVRH
V
AN7
—
AVRL
—
AVRH
—
AVCC
V
– 2.7
Reference voltage
AVRH
—
AVRL
0
—
V
– 2.7
IA
AVCC
—
3
—
mA
Supply current
when CPU stopped
Power supply current
and A/D converter
IAH
AVCC
—
—
5
µA
not in operation
(VCC = AVCC =
AVRH = 5.0 V)
IR
AVRH
—
—
200
—
µA
Supply current
when CPU stopped
Reference voltage supply curand A/D converter
rent
IRH
AVRH
—
—
5
µA
not in operation
(VCC = AVCC =
AVRH = 5.0 V)
AN0 to
Offset between channels
—
—
—
—
4
LSB
AN7
97
MB90670/675 Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error:The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000
0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics
Differential linearity error:The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error:The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
3FE
0.5 LSB’
Actual conversion
characteristics
Digital output
3FD
{1 LSB × (N – 1) + 0.5 LSB}
004
VNT
(Measured value)
003
Actual conversion
characteristics
002
Theoretical
characteristics
001
0.5 LSB’
AVRL
AVRH
Analog input
1 LSB’ = (Theoretical value)
AVRH – AVRL
[V]
1024
VOT’ (Theoretical value) = AVRL + 0.5 LSB’ [V]
Total error for digital output N =
VNT – {1 LSB’ × (N – 1) + 0.5 LSB’}
[LSB]
1 LSB’
VNT: Voltage at a transition of digital output from (N – 1) to N
VFST’ (Theoretical value) = AVRH – 1.5 LSB’ [V]
(Continued)
98
MB90670/675 Series
(Continued)
Linearity error
Differential linearity error
Theoretical
characteristics
3FF
Actual conversion
characteristics
3FE
N+1
{1 LSB × (N – 1)
+ VOT’}
VFST
(Measured value)
Digital output
Digital output
3FD
Actual conversion
characteristics
VNT
004
Actual conversion
characteristics
003
N
V(N + 1)T
(Measured value)
N–1
VNT (Measured value)
002
Theoretical
characteristics
001
Actual conversion
characteristics
N–2
VOT (Measured value)
AVRL
Analog input
AVRH
AVRL
VNT – {1 LSB × (N – 1) + VOT}
Linearity error of
[LSB]
=
1 LSB’
digital output N
1 LSB =
Analog input
Differential linearity error
=
of digital output N
AVRH
V(N + 1)T – VNT
1 LSB’
– 1 LSB [LSB]
AVRH – AVRL
[V]
1022
VOT:Voltage at transition of digital output from “000H” to “001H”
VFST:Voltage at transition of digital output from “3FEH” to “3FFH”
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions.
Output impedance values of the external circuit of 7 kΩ or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor
value is recommended to minimized the effect of voltage distribution between the external capacitor and internal
capacitor.
When the output impedance of the external circuit is too high, the sampling time for analog voltages may not be
sufficient (sampling time = 3.75 µs @machine clock of 16 MHz).
• Block diagram of analog input circuit model
Sample hold circuit
Analog input
C0
Comparator
RON1
RON2
RON3
RON4
RON1: Approx. 1.5 kΩ(VCC = 5.0 V)
RON2: Approx. 0.5 kΩ (VCC = 5.0 V)
RON3: Approx. 0.5 kΩ(VCC = 5.0 V) C0: Approx. 60 pF
RON4: Approx. 0.5 kΩ (VCC = 5.0 V) C1: Approx. 4 pF
C1
Note : Listed values must be considered as standards.
• Error
The smaller the | AVRH – AVRL |, the greater the error would become relatively.
99
MB90670/675 Series
■ EXAMPLE CHARACTERISTICS
(1) “H” Level Output Voltage
VOH (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
(2) “L” Level Output Voltage
VOL (V)
VOH vs. IOH
VCC = 2.7 V
TA = +25°C
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
–2
–4
–6
–8
IOH (mA)
(3) “H” Level Input Voltage/“L” Level Input Voltage
(CMOS Input)
VIN (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2
100
VIN vs. VCC
TA = +25°C
3
4
5
6
VCC (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VOL vs. IOL
TA = +25°C
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
2
4
6
8
IOL (mA)
(4) “H” Level Input Voltage/“L” Level Input Voltage
(Hysteresis Input)
VIN (V)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2
VIN vs. VCC
TA = +25°C
VIHS
VILS
3
4
5
VIHS:Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS:Threshold when input voltage in hysteresis
characteristics is set to “L” level
6
VCC (V)
MB90670/675 Series
(5) Power Supply Current (fCP = Internal Operating Clock Frequency)
ICC vs. VCC
ICC (mA)
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
3.0
4.0
ICCS (mA)
15
fCP = 16 MHz
14
TA = +25°C
13
12
fCP = 12.5 MHz
11
10
9
8
fCP = 8 MHz
7
6
fCP = 4 MHz
5
4
3
2
1
0
5.0
6.0
3.0
VCC (V)
IA vs. AVCC
IA (mA)
6.0
ICCS vs. VCC
TA = +25°C
fCP = 16 MHz
fCP = 12.5 MHz
fCP = 8 MHz
fCP = 4 MHz
4.0
5.0
6.0
VCC (V)
IR vs. AVR
IA (mA)
0.30
TA = +25°C
fCP = 16 MHz
5.5
5.0
TA = +25°C
fCP = 16 MHz
4.5
0.20
4.0
3.5
3.0
2.5
0.10
2.0
1.5
1.0
0.5
0
0
3.0
4.0
5.0
6.0
AVCC (V)
3.0
4.0
5.0
6.0
AVR (V)
(6) Pull-up Resistance
R vs. VCC
R (kΩ)
1000
TA = +25°C
100
10
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
101
MB90670/675 Series
■ MASK OPTIONS
• MB90670 series
MB90671
Part number
No.
MB90672
MB90P673
MB90V670
Set with EPROM programmer
Setting not possible
MB90673
Specifying procedure
Specify when ordering
masking
1
Pull-up resistors
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P67,
P70 to P77, P80,
RST, MD1, MD0
Specify by pin
Specify by pin
Without pull-up resistor
2
Pull-down resistors
MD1, MD0
Specify by pin
Specify by pin
Without pull-up resistor
• MB90675 series
MB90676
Part number
No.
MB90677
MB90P678
MB90V670
Set with EPROM programmer
Setting not possible
MB90678
Specifying procedure
Specify when ordering
masking
1
Pull-up resistors
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P67,
P70 to P77, P80 to P86,
P90, P91, PA0 to PA7,
PB0 to PB2,
RST, MD1, MD0
Specify by pin
Specify by pin
Without pull-up resistor
2
Pull-down resistors
MD1, MD0
Specify by pin
Specify by pin
Without pull-up resistor
Notes : • The pull-up register configured as a port pin is switched-off in the stop mode and during the
hardware standby.
• In turning on power, option settings can not be made until clocks are supplied because 8 machine cycles
are needed for option settings for the MB90P670/P675.
102
MB90670/675 Series
■ ORDERING INFORMATION
Part number
Package
MB90671PFV
MB90672PFV
MB90673PFV
MB90T673PFV
MB90P673PFV
80-pin Plastic LQFP
(FPT-80P-M05)
MB90671PF
MB90672PF
MB90673PF
MB90T673PF
MB90P673PF
80-pin Plastic QFP
(FPT-80P-M06)
MB90676PFV
MB90677PFV
MB90678PFV
MB90T678PFV
MB90P678PFV
100-pin Plastic LQFP
(FPT-100P-M05)
MB90676PF
MB90677PF
MB90678PF
MB90T678PF
MB90P678PF
100-pin Plastic QFP
(FPT-100P-M06)
Remarks
103
MB90670/675 Series
■ PACKAGE DIMENSIONS
80-pin Plastic LQFP
(FPT-80P-M05)
Note: pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
60
0.145±0.055
(.006±.002)
41
40
61
(Mounting height)
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
INDEX
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
21
80
"A"
LEAD No.
1
20
0.50(.020)
C
(Mounting height)
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
M
2000 FUJITSU LIMITED F80008S-c-3-7
Dimensions in mm (inches)
80-pin Plastic QFP
(FPT-80P-M06)
Note: pins width and pins thickness include plating thickness.
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
64
41
65
40
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
80
25
0.25(.010)
+0.30
3.05 –0.20
+.012
.120 –.008
(Mounting height)
1
24
0.80(.031)
"A"
C
2001 FUJITSU LIMITED F80010S-c-4-4
0.37±0.05
(.015±.002)
0.20(.008)
0~8°
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
+0.10
0.30 –0.25
+.004
.012 –.010
(Stand off)
Dimensions in mm (inches)
(Continued)
104
MB90670/675 Series
(Continued)
100-pin Plastic LQFP
(FPT-100P-M05)
Note: pins width and pins thickness include plating thickness.
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
1
25
0.50(.020)
0.20±0.05
(.008±.002)
0.08(.003)
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
"A"
0.145±0.055
(.0057±.0022)
M
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches)
2000 FUJITSU LIMITED F100007S-3c-5
C
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
100-pin Plastic QFP
(FPT-100P-M06)
Note: pins width and pins thickness include plating thickness.
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8°
31
2001 FUJITSU LIMITED F100008S-c-4-4
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches)
105
MB90670/675 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0111
 FUJITSU LIMITED Printed in Japan