FUJITSU SEMICONDUCTOR DATA SHEET DS07-13712-4E 16-Bit Proprietary Microcontroller CMOS F2MC-16LX MB90470 Series MB90473/474/477/478/F474L/F474H ■ DESCRIPTIONS The FUJITSU MB90470 Series is a 16-bit general-purpose microcontroller designed for consumer products and other process control applications requiring high-speed and real-time processing. The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for use with high-level languages, expanded addressing mode, enhanced multiply and divide instructions, and full bit processing. Also included is a built-in 32-bit accumulator for long-word processing. Peripheral resources built into the MB90470 series include 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit input-output timer, 8/16-bit up-counter, PWC timer, I2C*2 interface, DTP/external interrupt, chip select, and 16-bit reload timer. *1 : F2MC is an abbreviation for FUJITSU Flexible Microcontroller, and is a registered trademark of FUJITSU, Ltd. *2 : I2C license : This product includes licensing of Philips I2C patents if used by the customer in an I2C system subject to the I2C standard specifications established by Philips. ■ PACKAGES 100-pin plastic QFP 100-pin plastic LQFP (FPT-100P-M06) (FPT-100P-M05) MB90470 Series ■ FEATURES • Clocks Minimum instruction execution time : 50.0 ns at 5 MHz base oscillation with 4 × multiplier (internal operation at 20 MHz/3.3 V ± 0.3 V) 62.5 ns at 4 MHz base oscillation with 4 × multiplier (internal operation at 16 MHz/3.0 V ± 0.3 V) Uses PLL clock multiplier. • Maximum memory size 16 Mbytes • Instruction set optimized for control applications Handles bit, byte, word, long-word data 23 standard addressing modes 32-bit accumulator for enhanced high-precision calculation Signed multiply-divide and expanded RETI instructions • Instruction system compatible with high-level language (C) multitasking System stack pointer Instruction set correlation and barrel shift instructions • Non-multi bus or multi-bus compatible • Program patch function (for two address pointers) • Improved execution speed 4-byte queue • Powerful interrupt functions 8 external interrupt functions with 8-level programmable priority • Data transfer functions (µ µDMA or Extended intelligent I/O service) 16 channels maximum µDMA maximum assured operation frequency : 16 MHz Extended intelligent I/O service maximum assured operation frequency : 20 MHz • Built-in ROM Flash versions : 256 KB, Mask ROM versions : 128 KB/256 KB • Built-in RAM 10 KB/16 KB • General purpose ports 84 ports maximum (includes 16 ports with input pull-up resistance setting, 14 ports with output open drain setting) • A/D converter RC sequential comparator type, 8 channels 10-bit resolution, conversion time 4.65 µs (at 20 MHz operation) • I2C interface 1 channel • µPG 1 channel • UART 1 channel • I/O expansion serial interface (SIO) 2 channels • 8/16-bit up/down timer 1 channel • 16-bit PWC 3 channels (including 2-channel input comparison function) (Continued) 2 MB90470 Series (Continued) • 16-bit reload timer 1 channel (8-bit × 2-channel, 16-bit × 1-channel mode switching function provided) • 16-bit input-output timer 2-channel input capture, 6-channel output compare, 1-channel free run timer • 2 built-in clock generator systems • Low power modes Stop, sleep, CPU intermittent mode, watch mode, etc. • Package options QFP100/LQFP100 • Process CMOS technology • Supply voltage Can operate on 3 V single supply systems (with 5 V interface provided by some pins with 3/5 V dual-supply capability) 3 MB90470 Series ■ PRODUCT LINEUP Part number Parameter ROM capacity RAM capacity MB90F474L MB90F474H MB90473 MB90474 FLASH 256 KB FLASH 256 KB MASKROM 128 KB MASKROM 256 KB 16 KB 16 KB 10 KB 16 KB CPU functions Basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Ports General purpose input/output ports : 84 Max General purpose input/output ports (CMOS output) General purpose input/output ports (built-in pull-up resistance) General purpose input/output ports (N-ch open drain) UART Stop-start synchronized : 1 channel 8/16-bit PPG timer 8-bit 6-channel/16-bit 3-channel 8/16-bit up-down counter/timer Two 8-bit up-down counters with 6 event input pins Two 8-bit reload/compare registers 16-bit 16-bit free-run timer input/ Output compare (OCU) output timers Input capture (ICU) : 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bit, 16-bit : 62.5 ns (with 16 MHz machine clock) Channel : 1 Overflow interrupt Channels : 6 Pin input source : from compare register match signal Channels : 2 Register rewritten from pin input (rising/falling/both edges) DTP/external interrupt circuit External interrupt pins : 8 channels (set to edge or level correlation) I/O expansion serial interface 2-channel, built-in 2 I C interface 1-channel, built-in Time base timer 18-bit counter Interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (minimum times, at base oscillator frequency 4 MHz) A/D converter Conversion accuracy : 8/10-bit switchable Single conversion mode (converts selected channel 1 time only) Scan conversion mode (converts multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (converts selected channels continuously) Stop conversion mode (converts selected channel, stops and repeats) Watchdog timer Reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum times, at base oscillator frequency 4 MHz) Low power (standby) modes Sleep, stop, CPU intermittent, watch mode Process CMOS Notes Flash model, low Flash model, high voltage version voltage version (f = 10 MHz or (f = 20 MHz) less at VCC = 2.4 V) Emulator dedicated power supply Mask version Mask version (Continued) 4 MB90470 Series (Continued) Part number MB90477 MB90478 MB90V470B ROM capacity MASKROM 256 KB MASKROM 256 KB RAM capacity 8 KB 8 KB 16 KB Parameter : 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bit, 16-bit : 50 ns (with 20 MHz machine clock) CPU functions Basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Ports General purpose input/output ports : 84 Max General purpose input/output ports (CMOS output) General purpose input/output ports (built-in pull-up resistance) General purpose input/output ports (N-ch open drain) UART Stop-start synchronized : 1 channel 8/16-bit PPG timer 8-bit 6-channel/16-bit 3-channel 8/16-bit up-down counter/timer Two 8-bit up-down counters with 6 event input pins Two 8-bit reload/compare registers 16-bit free-run timer 16-bit input/ Output compare (OCU) output timers Input capture (ICU) Channel : 1 Overflow interrupt Channels : 6 Pin input source : from compare register match signal Channels : 2 Register rewritten from pin input (rising/falling/both edges) DTP/external interrupt circuit External interrupt pins : 8 channels (set to edge or level correlation) I/O expansion serial interface 2-channel, built-in 2 I C interface 1-channel, built-in Time base timer 18-bit counter Interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (minimum times, at base oscillator frequency 4 MHz) A/D converter Conversion accuracy : 8/10-bit switchable Single conversion mode (converts selected channel 1 time only) Scan conversion mode (converts multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (converts selected channels continuously) Stop conversion mode (converts selected channel, stops and repeats) Watchdog timer Reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum times, at base oscillator frequency 4 MHz) Low power (standby) modes Sleep, stop, CPU intermittent, watch mode Process CMOS Notes Emulator dedicated power supply Mask version Mask version without I2C built-in interface EVA function User pin Included 5 MB90470 Series ■ PIN ASSIGNMENTS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P74/TOT0 P75/PWC2 P76/SCL P77/SDA AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 Vss P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0 P37/A07/PWC1 P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00 P44/A12/MT01 VCC5 P45/A13/EXTC P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 P71/SOT0 P72/SCK0 P73/TIN0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS (TOP VIEW) (FPT-100P-M06) 6 X0A X1A P57/CLK RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 MD2 MB90470 Series 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P21/A17 P20/A16 P17/AD15/D15 P16/AD14/D13 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS X0A X1A P57/CLK (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P71/SOT0 P72/SCK0 P73/TIN0 P74/TOT0 P75/PWC2 P76/SCL P77/SDA AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 P82/IRQ2 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0 P37/A07/PWC1 P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00 P44/A12/MT01 VCC5 P45/A13/EXTC P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 (FPT-100P-M05) 7 MB90470 Series ■ PIN DESCRIPTION Pin no. Pin name Circuit type Description LQFP QFP 80 82 X0 A Oscillator pin 81 83 X1 A Oscillator pin 78 80 X0A A 32 kHz oscillator pin 77 79 X1A A 32 kHz oscillator pin 75 77 RST B Reset input pin General purpose input/output ports. Set the pull-up resistance setting register (RDR0) to add pull-up resistance (RD00-RD07 = “1” ) . (Not valid when set for output) P00 to P07 83 to 90 85 to 92 91 to 98 99 100 1 2 3 to 6 93 to 100 1 to 4 5 to 8 AD00 to AD07 C (CMOS) In multiplex mode, these pins function as external address/ data bus lower input/output pins. D00 to D07 In non-multiplex mode, these pins function as external data bus lower output pins. P10 to P17 General purpose input/output ports. Set the pull-up resistance setting register (RDR1) to add pull-up resistance (RD10-RD17 = “1” ) . (Not valid when set for output) AD08 to AD15 C (CMOS) In multiplex mode, these pins function as external address/ data bus higher input/output pins. D08 to D15 In non-multiplex mode, these pins function as external data bus higher output pins. P20 to P23 General purpose input/output ports. In external bus mode, pins for which the corresponding bit in the external address output control register (HACR) is “1” function as the general purpose input/output ports. A16 to A19 E In multiplex mode, pins for which the corresponding bit in the (CMOS/H) external address output control register (HACR) is “0” function as the upper address output pins (A16 to A19) . A16 to A19 In non-multiplex mode, pins for which the corresponding bit in the external address output control register (HACR) is “0” function as the upper address output pins (A16 to A19) . P24 to P27 General purpose input/output ports. In external bus mode, pins for which the corresponding bit in the external address output control register (HACR) is “1” function as the general purpose input/output ports. A20 to A23 In multiplex mode, pins for which the corresponding bit in the E external address output control register (HACR) is “0” function (CMOS/H) as the upper address output pins (A20 to A23) . A20 to A23 In non-multiplex mode, pins for which the corresponding bit in the external address output control register (HACR) is “0” function as the upper address output pins (A20 to A23) . PPG0 to PPG3 PPG timer output pins. (Continued) LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package 8 MB90470 Series Pin no. LQFP QFP Pin name Circuit type P30 7 8 10 11 12 13 9 10 12 13 14 15 A00 General purpose input/output port. E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. AIN0 8/16-bit up-down timer input pin. (ch0) P31 General purpose input/output port. A01 E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. BIN0 8/16-bit up-down timer input pin. (ch0) P32 General purpose input/output port. A02 E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. ZIN0 8/16-bit up-down timer input pin. (ch0) P33 General purpose input/output port. A03 E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. AIN1 8/16-bit up-down timer input pin. (ch1) P34 General purpose input/output port. A04 E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. BIN1 8/16-bit up-down timer input pin. (ch1) P35 General purpose input/output port. A05 E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. ZIN1 8/16-bit up-down timer input pin. (ch1) P36, P37 14 15 16 17 A06, A07 General purpose input/output ports. E In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. PWC0, PWC1 Functions as PWC input pin. P40 16 17 18 19 Description A08 General purpose input/output port. G In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. SIN2 Single serial I/O input pin P41 General purpose input/output port. A09 SOT2 F (CMOS) In non-multibus bus mode, this pin functions as an external address pin. Single serial I/O output pin (Continued) LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package 9 MB90470 Series Pin no. LQFP QFP Pin name Circuit type P42 18 20 A10 General purpose input/output port. G In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. SCK2 Single serial I/O clock input/output pin P43, P44 19 20 21 22 A11, A12 General purpose input/output ports. F (CMOS) P45 24 A13 General purpose input/output ports. G In non-multibus bus mode, this pin functions as an external (CMOS/H) address pin. µPG input pin EXTC P46, P47 23 24 25 26 A14, A15 General purpose input/output ports. F (CMOS) OUT4/OUT5 P50 68 70 ALE P51 69 71 RD D (CMOS) D (CMOS) 71 D (CMOS) 72 In non-multibus bus mode, this pin functions as an external address pin. Output compare event output pins P52 70 In non-multibus bus mode, this pin functions as an external address pin. µPG input pins MT00, MT01 22 Description General purpose input/output port. In external bus mode, this pin functions as the ALE pin In external bus mode, this pin functions as the address load enable signal (ALE) pin General purpose input/output port. In external bus mode, this pin functions as the RD pin. In external bus mode, this pin functions as the read strobe output (RD) pin. General purpose input/output port. In external bus mode, this pin functions as the WRL pin when the WRE bit in the EPCR register is set to “1”. WRL In external bus mode, this pin functions as the lower data write strobe output (WRL) pin. When the WRE bit in the EPCR register is set to “0”,this pin functions as a general purpose input/output port. P53 General purpose input/output port. In external bus mode with 16-bit bus width, this pin functions as the WRH pin when the WRE bit in the EPCR register is set to “1”. D (CMOS) 73 WRH In external bus mode with 16-bit bus width, this pin functions as the higher data write strobe output (WRH) pin. When the WRE bit in the EPCR register is set to “0”,this pin functions as a general purpose input/output port. (Continued) LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package 10 MB90470 Series Pin no. LQFP QFP Pin name Circuit type P54 72 73 74 76 D (CMOS) 74 In external bus mode, this pin functions as the hold request input (HRQ) pin. When the HDE bit in the EPCR register is set to “0”,this pin functions as a general purpose input/output port. P55 General purpose input/output port. In external bus mode, this pin functions as the HAK pin when the HDE bit in the EPCR register is set to “1”. D (CMOS) HAK In external bus mode, this pin functions as the hold acknowledge output (HAK) pin. When the HDE bit in the EPCR register is set to “0”,this pin functions as a general purpose input/output port. P56 General purpose input/output port. In external bus mode, this pin functions as the DRY pin when the RYE bit in the EPCR register is set to “1”. D (CMOS) 76 RDY In external bus mode, this pin functions as the external ready input (RDY) pin. When the RYE bit in the EPCR register is set to “0”,this pin functions as a general purpose input/output port. P57 General purpose input/output port. In external bus mode, this pin functions as the CLK pin when the CKE bit in the EPCR register is set to “1”. D (CMOS) 78 CLK 41 to 44 43 to 46 25 27 26 28 27 29 28 30 29 31 General purpose input/output port. In external bus mode, this pin functions as the HRQ pin when the HDE bit in the EPCR register is set to “1”. HRQ 75 36 to 39 38 to 41 Description P60 to P63 AN0 to AN3 P64 to P67 AN4 to AN7 P70 SIN0 P71 SOT0 P72 SCK0 P73 TIN0 P74 TOT0 H (CMOS) H (CMOS) In external bus mode, this pin functions as the machine cycle clock output (CLK) pin. When the CKE bit in the EPCR register is set to “0”,this pin functions as a general purpose input/output port. General purpose input/output ports. Analog input pins. General purpose input/output ports. Analog input pins. General purpose input/output port. G (CMOS/H) UART data input pin. F (CMOS) General purpose input/output port. UART data output pin. General purpose input/output port. G (CMOS/H) UART clock input pin. General purpose input/output port. G (CMOS/H) 16-bit reload timer event input pin. F (CMOS) General purpose input/output port. 16-bit reload timer output pin. (Continued) LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package 11 MB90470 Series Pin no. LQFP QFP 30 32 Pin name P75 PWC2 P76 31 33 SCL P77 32 34 45 46 47 48 50 to 55 52 to 57 SDA P80, P81 IRQ0, IRQ1 P82 to P87 IRQ2 to IRQ7 P90 56 58 SIN1 CS0 Circuit type General purpose input/output port. G (CMOS/H) PWC input pin. General purpose input/output port. I 2 2 (NMOS/H) I C interface data input/output pin. During I C interface operation, the port output should be set to High-Z level. General purpose input/output port. I 2 2 (NMOS/H) I C interface clock input/output pin. During I C interface operation, the port output should be set to High-Z level. General purpose input/output ports. E (CMOS/H) External interrupt input pins. General purpose input/output ports. E (CMOS/H) External interrupt input pins. General purpose input/output port. E Single serial I/O data input pin. (CMOS/H) Chip select 0. P91 57 59 SOT1 General purpose input/output port. D (CMOS) CS1 P92 58 60 SCK1 CS2 59 61 ADTG General purpose input/output port. E Single serial I/O clock input/output pin. (CMOS/H) Chip select 2. General purpose input/output port. In free run timer operation, this pin functions as the external clock input pin. E (CMOS/H) In A/D converter operation, this pin functions as the external trigger input pin. CS3 60 62 61 63 62 64 P94 PPG4 P95 PPG5 P96 IN0 Single serial I/O data output pin. Chip select 1. P93 FRCK Description Chip select 3. D (CMOS) D (CMOS) General purpose input/output port. PPG timer output pin. General purpose input/output port. PPG timer output pin. General purpose input/output port. E (CMOS/H) Functions as input capture ch 0 trigger input. (Continued) LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package 12 MB90470 Series (Continued) Pin no. LQFP QFP 63 65 64 to 67 66 to 69 Pin name P97 IN1 PA0 to PA3 Circuit type Description General purpose input/output port. E (CMOS/H) Functions as input capture ch 1 trigger input. OUT0 to OUT3 D (CMOS) General purpose input/output ports. Output compare event output pins. 33 35 AVCC A/D converter power supply pin. 34 36 AVRH A/D converter external reference power pin. 35 37 AVSS A/D converter power supply pin. 47 to 49 49 to 51 MD0 to MD2 J Input pins for specifying operating mode. (CMOS/H) 82 84 VCC3 3.3 V ± 0.3 V power supply pin (VCC3) . 21 23 VCC5 3.3 V ± 0.3 V/5.0 V ± 0.5 V dual power supply pin (VCC5) . 9 40 79 11 42 81 VSS Power supply input pins (GND) . LQFP : FPT-100P-M05 package QFP : FPT-100P-M06 package Notes : • For use as a 3.3 V single supply device, apply the same voltage to the VCC3 and VCC5 power supply pins. • For use with a dual power supply, apply the respective voltages to the VCC3 and VCC5 power supply pins. • In use with a dual power supply, a total of 32 pins (P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/ A07/PWC1, P40/A08/SIN2 to P47/A15/OUT5 and P70/SIN0 to P77/SDA) can be used in a 5 V interface. Note that all other pins must be used in 3 V interface. • In use with a dual power supply, it is not possible to turn on only the 5 V or the 3 V power supply independently. Always turn on both power supplies simultaneously. (It is recommended that the 3 V power to the MB90470 series be turned on first.) 13 MB90470 Series ■ I/O CIRCUIT TYPES Type Circuit Remarks X1, X1A A Oscillator feedback resistance : X1,X0 1 MΩ approx. X1A,X0A 10 MΩ approx. Includes standby control X0, X0A Standby control signal B Hysteresis with pull-up resistance Input resistance 50 kΩ approx. HYS CTL Includes input pull-up resistance control CMOS level input/output Resistance : 50 kΩ approx. C CMOS D CMOS level input/output CMOS Hysteresis input CMOS level input/output E CMOS (Continued) 14 MB90470 Series (Continued) Type Circuit Remarks Open drain control signal CMOS level input/output Includes open drain control F CMOS Open drain control signal CMOS level output Hysteresis input Includes open drain control G HYS CMOS level input/output Analog input H CMOS Analog input Digital output Hysteresis input N-ch open drain output I HYS (Flash model) Flash model Control signal J CMOS level input Includes high voltage control for FLASH test Mode input Spreading resistance (Mask version) HYS Mask version Hysteresis input port 15 MB90470 Series ■ HANDLING DEVICES (1) Strictly observe maximum rated voltages (prevent latchup) When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output pins other than medium- and high-withstand voltage pins, or to voltages lower than VSS, or when voltages in excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. In a latchup condition, supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings. Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power supply (AVCC, AVRH) and analog input do not exceed the digital power supply (VCC) . (2) Treatment of unused pins If unused input pins are left open, abnormal operation or latchup may cause permanent damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least 2 kΩ. Also any unused input/output pins should be left open in output status, or if set to input status should be treated in the same way as input pins. (3) Precautions for use of external clock signals Even when an external clock is used, a stabilization period is required following a power-on reset or release from sub clock mode or stop mode. Also, when an external clock is used 20 MHz should be used as a guideline for an upper frequency limit. The following figure shows a sample use of external clock signals. X0 OPEN X1 (4) Power supply pins When using multiple VCC/VSS sources, always make sure to design devices with external connections of all power supply pins to supply or ground elements, in order to prevent latchup, reduce unwanted radiation, and prevent abnormal strobe signal operation due to rise in ground level, as well as to maintain total rated output current. In addition, care must be given to connecting the VCC and VSS pins of this device to a current source with as little impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between VCC and VSS as close to the pins as possible. (5) Crystal oscillator circuits Abnormal operation of this device can result from noise in the proximity of the X0/X1 and X0A/X1A pins. For stable operation, it is strongly recommended that the printed circuit artwork provide capacitors placed as close as possible between the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) as well as ground, and be wired so as to avoid crossing other wiring wherever possible. 16 MB90470 Series (6) Precautions for use of external oscillators (crystals) The target value for the upper limit of oscillator (crystals) frequencies should be 20 MHz. Also, when operating at internal frequencies of 16 MHz, the PLL multiplier should be used. (7) Proper power-on/off sequence The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power supply (VCC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut off before the digital power supply (VCC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AVCC. Note : VCC = VCC3 = VCC5 (8) Treatment of A/D converter power supply pins Even if the A/D converter is not used, pins should be connected so that AVCC = AVRH = VCC, and AVSS = VSS. (9) Power-on procedures In order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise during power-on should be attained within 50 µs (0.2 V to 2.7 V) . (10) Stable power supply Even within the operating range of the VCC supply voltage, rapid changes in supply voltage may cause abnormal operation. As a basis for stable operation, it is recommended that voltage variation be restricted in order to limit VCC ripple fluctuations (P-P values) to 10% at commercial frequencies of 50 Hz to 60 Hz, and transient fluctuations to 0.1 V/ms at instantaneous points such as power switching. (11) Precautions for use of two power supplies The MB90470 series usually uses the 3-V power supply as the main power source. With VCC3 = 3 V and VCC5 = 5 V, however, it can interface with P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/A07/PWC1, P40/A08/SIN2 to P47/A15/OUT5, P70/SIN0 to P77/SDA for the 5-V power supply separetely from the 3-V power supply at all operation mode. (Caution) The analog power supply for the A/D converter (AVCC, AVSS etc.) can only operate with the 3 V system. (12) Crystal oscillator circuits during power-saving operation When the power supply is lower than 2.0 V, the external crystal oscillator may not operate even when power is on. For this reason, the use of an external clock signal is recommended. (13) Caution : low-voltage flash models (2.4 V to 3.6 V/10 MHz) do not have security functions (14) Treatment of unused input pins N.C. (internally connected) pins should always be left open. (15) When the dual-supply MB90470 series is used as a 1-supply device, use connections so that X0A = VSS, and X1A = Open. 17 MB90470 Series (16) For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V. (17) Caution on Operations during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 18 MB90470 Series ■ BLOCK DIAGRAM X0, X1, RST X0A, X1A MD2, MD1, MD0 CPU FMC-16LX series core Clock control circuit 8 RAM Interrupt controller ROM PPG0, PPG1 PPG2, PPG3 PPG4, PPG5 8/16-bit PPG µDMA AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 8/16-bit up/down counter Communication prescaler 2 SIN1, SIN2 SOT1, SOT 2 SCK1, SCK2 AVCC AVRH AVSS ADTG AN0 to AN7 PWC0 PWC1 PWC2 F2MC-16LX BUS SIN0 SOT0 SCK0 UART I/O expansion serial interface × 2 channels EXTC MT00 MT01 µPG Chip select CS0, CS1, CS2, CS3 Input/output timer 16-bit input capture × 2 IN0, IN1 OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 16-bit output compare × 6 16-bit free-run timer A/D converter (10-bit) 16-bit reload timer TIN0 TOT0 I2C interface SCL SDA 16-bit PWC 3 channels External interrupt 8 IRQ0 to IRQ7 I/O ports 8 8 P00 P10 8 P20 8 P30 8 P40 8 P50 8 P60 8 P70 4 8 P80 P90 PA0 ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ P00 to P07 (8 pins) P10 to P17 (8 pins) P40 to P47 (8 pins) P70 to P75 (6 pins) P76, P77 (2 pins) 8 P07 P17 P27 P37 P47 P57 P67 P77 P87 P97 PA3 : Input pull-up resistance setting register provided. : Input pull-up resistance setting register provided. : Open drain setting register provided. : Open drain setting register provided. : Open drain Note : In the above diagram, I/O ports are shown sharing pin numbers with the built-in function blocks. However pins may not be used as I/O ports when they are in use as pins for build-in function modules. 19 MB90470 Series ■ MEMORY MAP Single chip Internal ROM external bus ROM area ROM area ROM area FF bank image ROM area FF bank image External ROM external bus FFFFFFH Address 1# 010000H 004000H * Address 2# RAM Register RAM Register RAM Register 000100H 0000D0H Peripheral Peripheral Peripheral 000000H : Internal : External : Access not available * : In models where address 2# coincides with 004000H, there is no external area. Model Address 1# Address 2# MB90473 FE0000H 002900H MB90474 FC0000H 004000H MB90477/478 FC0000H 002100H MB90F474 FC0000H 004000H MB90V470 (FC0000H) 004000H The image of FF bank ROM is reflected in the top of the 00 bank, for greater efficiency in using the C compiler for small models. The lower 16-bit address on the FF bank is the same as the lower 16-bit address on the 00 bank, so that it is possible to reference tables in ROM without using the pointer for a far specification. For example, when accessing 00C000H, it is actually the content of ROM at FFC000H that is accessed. Here, because the ROM area on the FF bank exceeds 48 KB, it is not possible to view the entire area in the image on the 00 bank. Therefore, the image from FF4000H to FFFFFFH is visible on the 00 bank, and FF0000H to FF3FFFH is visible only on the FF bank. 20 MB90470 Series ■ F2MC-16L CPU PROGRAMMING MODEL • Special purpose registers AH AL Accumulator USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8 bit 16 bit 32 bit • General purpose registers MSB LSB 16 bit 000180H + RP × 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 • Processor status 13 12 15 PS ILM 8 7 RP 0 CCR 21 MB90470 Series ■ I/O MAP Address Register name Symbol Access Resource name Default 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXX 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXX 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXX 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXX 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXX 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXX 07H Port 7 data register PDR7 R/W Port 7 1 1XXXXXX 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXX 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXX 0AH Port A data register PDRA R/W Port A - - - - XXXX 0BH Port 3 timer input enable register UDRE R/W Up/down timer input control XX 0 0 0 0 0 0 0CH Interrupt/DTP enable register ENIR R/W 0DH Interrupt/DTP enable register EIRR R/W 0EH Demand level setting register 0FH Demand level setting register 10H Port 0 direction register DDR0 R/W Port 0 00000000 11H Port 1 direction register DDR1 R/W Port 1 00000000 12H Port 2 direction register DDR2 R/W Port 2 00000000 13H Port 3 direction register DDR3 R/W Port 3 00000000 14H Port 4 direction register DDR4 R/W Port 4 00000000 15H Port 5 direction register DDR5 R/W Port 5 00000000 16H Port 6 direction register DDR6 R/W Port 6 00000000 17H Port 7 direction register DDR7 R/W Port 7 --000000 18H Port 8 direction register DDR8 R/W Port 8 00000000 19H Port 9 direction register DDR9 R/W Port 9 00000000 1AH Port A direction register DDRA R/W Port A ----0000 1BH Port 4 pin register ODR4 R/W Port 4 (OD control) 00000000 1CH Port 0 resistance register RDR0 R/W Port 0 (pull-up) 00000000 1DH Port 1 resistance register RDR1 R/W Port 1 (pull-up) 00000000 1EH Port 7 pin register ODR7 R/W Port 7 (OD control) --000000 1FH Analog input enable register ADER R/W Port 5, A/D 11111111 ELVR R/W 00000000 DTP/external interrupt R/W 00000000 00000000 00000000 (Continued) 22 MB90470 Series Address Register name Symbol Access Resource name Default 20H Serial mode register 0 SMR0 R/W 00000X00 21H Serial control register 0 SCR0 R/W 00000100 22H Serial input register/ serial output register SIDR/ SODR0 R/W 23H Serial status register SSR0 R/W 24H UART0 XXXXXXXX 00001000 Reserved Communication prescaler (UART) 25H Clock divider control register CDCR R/W 26H Serial mode control status register 0 SMCS0 R/W 27H Serial mode control status register 0 SMCS0 R/W 28H Serial data register SDR0 R/W 29H Clock divider control register SDCR0 R/W 2AH Serial mode control status register 1 SMCS1 R/W 2BH Serial mode control status register 1 SMCS1 R/W 2CH Serial data register SDR1 R/W 2DH Clock divider control register SDCR1 R/W 2EH PPG reload register L (ch0) PRLL0 R/W XXXXXXXX 2FH PPG reload register H (ch0) PRLH0 R/W XXXXXXXX 30H PPG reload register L (ch1) PRLL1 R/W XXXXXXXX 31H PPG reload register H (ch1) PRLH1 R/W XXXXXXXX 32H PPG reload register L (ch2) PRLL2 R/W XXXXXXXX 33H PPG reload register H (ch2) PRLH2 R/W XXXXXXXX 34H PPG reload register L (ch3) PRLL3 R/W XXXXXXXX 35H PPG reload register H (ch3) PRLH3 R/W XXXXXXXX 36H PPG reload register L (ch4) PRLL4 R/W 37H PPG reload register H (ch4) PRLH4 R/W 38H PPG reload register L (ch5) PRLL5 R/W XXXXXXXX 39H PPG reload register H (ch5) PRLH5 R/W XXXXXXXX 3AH PPG0 operating mode control register PPGC0 R/W 0 X 0 0 0XX 1 3BH PPG1 operating mode control register PPGC1 R/W 0X000001 3CH PPG2 operating mode control register PPGC2 R/W 0 X 0 0 0XX 1 3DH PPG3 operating mode control register PPGC3 R/W 0X000001 3EH PPG4 operating mode control register PPGC4 R/W 0 X 0 0 0XX 1 3FH PPG5 operating mode control register PPGC5 R/W 0X000001 40H PPG0, 1 output control register PPG01 R/W 00--0000 ----0000 SCI1 (ch0) 00000010 XXXXXXXX Communication prescaler (SCI0) 0---0000 ----0000 SCI2 (ch1) 00000010 XXXXXXXX Communication prescaler (SCI1) 8/16-bit PPG (ch0-ch5) 8/16-bit PPG 0---0000 XXXXXXXX XXXXXXXX 00000000 (Continued) 23 MB90470 Series Address Register name 41H 42H PPG2, 3 output control register 47H 48H 49H Resource name Default PPG23 R/W 8/16-bit PPG 00000000 8/16-bit PPG 00000000 Reserved PPG4, 5 output control register 45H 46H Access Reserved 43H 44H Symbol PPG45 R/W Reserved Control status register Data register ADCS1 R/W ADCS2 R/W ADCR1 R ADCR2 R OCCP0 R/W OCCP1 R/W OCCP2 R/W OCCP3 R/W OCCP4 R/W OCCP5 R/W 00000000 A/D converter 00000000 XXXXXXXX 0 0 0 0 0 XXX 4AH Output compare register (ch0) low 4BH Output compare register (ch0) high 4CH Output compare register (ch1) low 4DH Output compare register (ch1) high 4EH Output compare register (ch2) low 4FH Output compare register (ch2) high 50H Output compare register (ch3) low 51H Output compare register (ch3) high 52H Output compare register (ch4) low 53H Output compare register (ch4) high 54H Output compare register (ch5) low 55H Output compare register (ch5) high 56H Output compare control register (ch0) OCS0 R/W 0000--00 57H Output compare control register (ch1) OCS1 R/W ---00000 58H Output compare control register (ch2) OCS2 R/W 0000--00 59H Output compare control register (ch3) OCS3 R/W ---00000 5AH Output compare control register (ch4) OCS4 R/W 0000--00 5BH Output compare control register (ch5) OCS5 R/W 16-bit output timer OCU (ch4, 5) 5CH Input capture register (ch0) low 5DH Input capture register (ch0) high 5EH Input capture register (ch1) low 5FH Input capture register (ch1) high 60H Input capture control register 61H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit output timer output compare (ch0-ch5) R XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ---00000 XXXXXXXX R IPCP1 XXXXXXXX XXXXXXXX R IPCP0 ICS01 XXXXXXXX XXXXXXXX 16-bit output timer Input capture (ch0, 1) XXXXXXXX R XXXXXXXX R/W 00000000 Reserved (Continued) 24 MB90470 Series Address Register name Symbol Access Resource name Default 62H Timer data register low TCDT R/W 00000000 63H Timer data register high TCDT R/W 00000000 64H Timer control status register TCCS R/W 65H Timer control status register TCCS R/W 66H Compare clear register low 67H Compare clear register high CPCLR R/W 68H Up down count register ch0 UDCR0 R 00000000 69H Up down count register ch1 UDCR1 R 00000000 6AH Reload compare register ch0 RCR0 W 6BH Reload compare register ch1 RCR1 W 6CH Counter control register low ch0 CCRL0 R/W 0X00X000 6DH Counter control register high ch0 CCRH0 R/W 00000000 6EH ROM mirror function select register ROMM W 70H Counter control register low ch1 CCRL1 R/W 71H Counter control register high ch1 72H Count status register ch0 Count status register ch1 75H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 85H XXXXXXXX XXXXXXXX 8/16-bit up-down timer-counter 00000000 00000000 CCRH1 R/W CSR0 R/W ROM mirror function -------1 0X00X000 8/16-bit up-down timer-counter -0000000 00000000 CSR1 R/W 8/16-bit UDC 00000000 Reserved PWC0 control status register PWCSR0 00000000 R/W 16-bit PWC timer (ch0) PWC0 data buffer register PWC1 control status register PWCR0 R/W PWCSR1 R/W PWC1 data buffer register PWC2 control status register PWCR1 R/W PWCSR2 R/W PWC0 division ratio register PWCR2 R/W DIVR0 R/W 00000000 00000000 0000000X 00000000 00000000 00000000 16-bit PWC timer (ch2) PWC2 data buffer register 0000000X 00000000 16-bit PWC timer (ch1) 83H 84H 0--00000 Reserved 73H 76H 00000000 Reserved 6FH 74H 16-bit output timer Free run timer 0000000X 00000000 00000000 PWC (ch0) ------00 PWC (ch1) ------00 Reserved PWC1 division ratio register DIVR1 R/W Reserved (Continued) 25 MB90470 Series Address 86H Register name PWC2 division ratio register 89H Access Resource name Default DIVR2 R/W PWC (ch2) ------00 Reserved 87H 88H Symbol I2C bus status register IBSR R 2 IBCR R/W 2 I C bus control register 00000000 00000000 I C functions 8AH I C bus clock select register ICCR R/W 8BH I2C bus address register IADR R/W - XXXXXXX 8CH I2C bus data register IDAR R/W XXXXXXXX 8DH 8EH 2 - - 0XXXXX Reserved µPG control register 8FH to 9BH PGCSR R/W µPG 00000--- Prohibited 9CH µDMA status register DSRL R/W µDMA 00000000 9DH µDMA status register DSRH R/W µDMA 00000000 9EH Program address detection control status resister PACSR R/W Address Match Detection Function 00000000 9FH Delay interrupt source generate/ release register DIRR R/W Delay interrupt generator module --------0 A0H Low power mode register LPMCR R/W Low power modes 00011000 A1H Clock select register CKSCR R/W Low power modes 11111100 A2H, A3H Reserved A4H µDMA stop status register DSSR R/W µDMA 00000000 A5H Auto ready function select register ARSR W External pins 0011--00 A6H External address output control register HACR W External pins 00000000 A7H Bus control signal control register EPCR W External pins 1000*10- A8H Watchdog control register WDTC R/W Watchdog timer XXXXX 1 1 1 A9H Time base timer control register TBTC R/W Time base timer 1XX00100 AAH Watch timer control register WTC R/W Watch timer 10001000 Reserved ABH ACH µDMA control register DERL R/W µDMA 00000000 ADH µDMA control register DERH R/W µDMA 00000000 AEH Flash memory control status register FMCR R/W Flash memory interface 000X0000 AFH Prohibited B0H Interrupt control register 00 ICR00 R/W XXXX 0 1 1 1 B1H Interrupt control register 01 ICR01 R/W XXXX 0 1 1 1 B2H Interrupt control register 02 ICR02 R/W XXXX 0 1 1 1 B3H Interrupt control register 03 ICR03 R/W XXXX 0 1 1 1 (Continued) 26 MB90470 Series Address Register name Symbol Access Resource name Default B4H Interrupt control register 04 ICR04 R/W XXXX 0 1 1 1 B5H Interrupt control register 05 ICR05 R/W XXXX 0 1 1 1 B6H Interrupt control register 06 ICR06 R/W XXXX 0 1 1 1 B7H Interrupt control register 07 ICR07 R/W XXXX 0 1 1 1 B8H Interrupt control register 08 ICR08 R/W XXXX 0 1 1 1 B9H Interrupt control register 09 ICR09 R/W XXXX 0 1 1 1 BAH Interrupt control register 10 ICR10 R/W XXXX 0 1 1 1 BBH Interrupt control register 11 ICR11 R/W XXXX 0 1 1 1 BCH Interrupt control register 12 ICR12 R/W XXXX 0 1 1 1 BDH Interrupt control register 13 ICR13 R/W XXXX 0 1 1 1 BEH Interrupt control register 14 ICR14 R/W XXXX 0 1 1 1 BFH Interrupt control register 15 ICR15 R/W XXXX 0 1 1 1 C0H Chip select MASK register 0 CMR0 R/W C1H Chip select area register 0 CAR0 R/W 11111111 C2H Chip select MASK register 1 CMR1 R/W 00001111 C3H Chip select area register 1 CAR1 R/W 11111111 C4H Chip select MASK register 2 CMR2 R/W 00001111 C5H Chip select area register 2 CAR2 R/W 11111111 C6H Chip select MASK register 3 CMR3 R/W 00001111 C7H Chip select area register 3 CAR3 R/W 11111111 C8H Chip select control register CSCR R/W ----000* C9H Chip select control active level register CALR R/W ----0000 TMCSR R/W CAH CBH CCH CDH Timer control status registers Chip select functions 0 0 0 0 1 1 1 1 00000000 16-bit reload timer 16-bit timer register 16-bit reload register TMR/ TMRLR R/W CEH, CFH Reserved D0H to FFH External area 100H to #H RAM area 1FF0 Program address detection resister0 (Low order address) 1FF1 Program address detection resister0 (Middle order address) 1FF2 Program address detection resister0 (High order address) PADR0 R/W ----0000 XXXXXXXX Address Match Detection Function XXXXXXXX (Continued) 27 MB90470 Series (Continued) Address Register name 1FF3 Program address detection resister1 (Low order address) 1FF4 Program address detection resister1 (Middle order address) 1FF5 Program address detection resister1 (High order address) Interrupt symbols : R/W : Read/write enabled R : Read only W : Write only Default value symbols : 0 : This bit initialized to “0” 1 : This bit initialized to “1” * : This bit initialized to “0” or “1” X : Default value undefined - : This bit is not used. 28 Symbol Access Resource name Default PADR1 R/W Address Match Detection Function XXXXXXXX MB90470 Series ■ INTERRUPT SOURCES, INTERRUPT VECTORS & INTERRUPT CONTROL REGISTERS Interrupt source EI2OS µDMA support channel no. Interrupt vector Interrupt control register No. Address No. Address Reset #08 FFFFDCH INT9 instruction #09 FFFFD8H Exception #10 FFFFD4H INT0 0 #11 FFFFD0H INT1 × #12 FFFFCCH ICR00 0000B0H INT2 × #13 FFFFC8H INT3 × #14 FFFFC4H ICR01 0000B1H INT4 × #15 FFFFC0H INT5 × #16 FFFFBCH ICR02 0000B2H INT6 × #17 FFFFB8H INT7 × #18 FFFFB4H ICR03 0000B3H PWC1 × #19 FFFFB0H PWC2 × #20 FFFFACH ICR04 0000B4H PWC0 1 #21 FFFFA8H PPG0/PPG1 counter borrow 2 #22 FFFFA4H ICR05 0000B5H PPG2/PPG3 counter borrow 3 #23 FFFFA0H PPG4/PPG5 counter borrow 4 #24 FFFF9CH ICR06 0000B6H 8/16-bit up/down counter timer compare/ underflow /overflow/ amp down inversion (ch0, 1) × #25 FFFF98H ICR07 0000B7H Input capture (ch0) load 5 #26 FFFF94H Input capture (ch1) load 6 #27 FFFF90H Output compare (ch0) match 8 #28 FFFF8CH ICR08 0000B8H Output compare (ch1) match 9 #29 FFFF88H Output compare (ch2) match 10 #30 FFFF84H ICR09 0000B9H Output compare (ch3) match × #31 FFFF80H Output compare (ch4) match × #32 FFFF7CH ICR10 0000BAH Output compare (ch5) match × #33 FFFF78H UART send end 11 #34 FFFF74H ICR11 0000BBH 16-bit free run timer/ 16-bit reload timer overflow 12 #35 FFFF70H ICR12 0000BCH UART receive end 7 #36 FFFF6CH (Continued) 29 MB90470 Series (Continued) Interrupt source EI2OS µDMA support channel no. Interrupt vector Interrupt control register No. Address No. Address ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH SIO1 13 #37 FFFF68H SIO2 14 #38 FFFF64H × #39 FFFF60H 15 #40 FFFF5CH I2C interface × A/D Flash write/erase, time base timer, watch timer* × × #41 FFFF58H Delay interrupt generator module × × #42 FFFF54H : Interrupt request flag cleared by the interrupt clear signal. The stop request is available. : Interrupt request flag cleared by the interrupt clear signal. × : Interrupt request flag not cleared by the interrupt clear signal. * : Note that flash write/erase cannot be used at the same time as the time base timer or watch timer. Note : • If two or more interrupt sources have the same interrupt number, the resource will clear both interrupt request flags at the EI2OS/DMAC interrupt clear signal. Thus when EI2OS/µDMA function of two sources is used, the other interrupt function cannot be used. The interrupt request enable bit of the corresponding resource should be set to “0” for software polling processing. • Maximum assured operation frequency of µDMA is 16 MHz. 30 MB90470 Series ■ PERIPHERAL RESOURCES 1. I/O Ports The I/O ports output data from the CPU to the I/O pins, and also load signals input at the I/O pins into the CPU, according to the port register (PDR) . The ports can also control the input/output direction of the I/O pins in bit units according to the port direction register (DDR) . The MB90470 series has 82 input/output pins and two open drain output pins. Ports 0 through A are input/output ports, and port 76, and 77 are the open drain ports. (1) Port Registers PDR0 Address : 000000H PDR1 Address : 000001H PDR2 Address : 000002H PDR3 Address : 000003H PDR4 Address : 000004H PDR5 Address : 000005H PDR6 Address : 000006H PDR7 Address : 000007H PDR8 Address : 000008H PDR9 Address : 000009H PDRA Address : 00000AH 7 6 5 4 3 2 1 0 Default value Access P07 P06 P05 P04 P03 P02 P01 P00 Undefined R/W* 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Undefined R/W* Undefined R/W* Undefined R/W* Undefined R/W* Undefined R/W* Undefined R/W* 11XXXXXX R/W* Undefined R/W* Undefined R/W* Undefined R/W* 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 7 6 5 4 3 2 1 0 P57 P56 P55 P54 P53 P52 P51 P50 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 7 6 5 4 3 2 1 0 PA3 PA2 PA1 PA0 * : Input/output port read/write operations are somewhat different than reading and writing to memory, and operate as follows. •Input mode Read : Reads the signal level of the corresponding pin. Write : Writes to the output latch. •Output mode Read : Reads the value of the data register latch. Write : Value is output to the corresponding pin. 31 MB90470 Series (2) Port Direction Registers DDR0 Address : 000010H DDR1 Address : 000011H DDR2 Address : 000012H DDR3 Address : 000013H DDR4 Address : 000014H DDR5 7 6 5 4 3 2 1 0 Default value Access D07 D06 D05 D04 D03 D02 D01 D 00 00000000 R/W 7 6 5 4 3 2 1 0 D17 D16 D15 D14 D13 D12 D11 D10 00000000 R/W 7 6 5 4 3 2 1 0 D27 D26 D25 D24 D23 D22 D21 D20 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W - - - - 0000 R/W 7 6 5 4 3 2 1 0 D37 D36 D35 D34 D33 D32 D31 D30 7 6 5 4 3 2 1 0 D47 D46 D45 D44 D43 D42 D41 D40 7 6 5 4 3 2 1 0 D57 D56 D55 D54 D53 D52 D51 D50 7 6 5 4 3 2 1 0 D67 D66 D65 D64 D63 D62 D61 D60 DDR7 7 6 5 4 3 2 1 0 Address : 000017H D75 D74 D73 D72 D71 D70 Address : 000015H DDR6 Address : 000016H DDR8 Address : 000018H DDR9 Address : 000019H DDRA Address : 00001AH 7 6 5 4 3 2 1 0 D87 D86 D85 D84 D83 D82 D81 D80 7 6 5 4 3 2 1 0 D97 D96 D95 D94 D93 D92 D91 D90 7 6 5 4 3 2 1 0 DA3 DA2 DA1 DA0 • When a pin is functioning as a port, the corresponding pin control setting is as follows : 0 : Input mode 1 : Output mode The register value is “0” at reset. • Port 76, 77 These ports do not have DDR registers. Data at these pins is always valid, so that when P76, P77 are used as I2C pins the PDR value should be “1”. (The I2C functions should be stopped, when these pins are used as P76,P77 .) These ports have open drain configuration. If they are used as input ports, the output transistor is turned off, so that the output data register must be set to “1” and pull-up resistance applied. Note : If these registers are accessed using read-modify-write instructions (such as bit set instructions) ,the bit that is the object of the instruction will be set to the specified value but for other bits the value of the corresponding output register will be rewritten to the input value of the pin at that time. For this reason when a pin used for input is switched to output, first write the desired value to the PDR register, then set the DDR register to switch the pin direction. 32 MB90470 Series (3) Input Resistance Registers RDR0 Address : 00001CH RDR1 Address : 00001DH 7 6 5 4 3 2 1 0 Default value Access RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 00000000 R/W 7 6 5 4 3 2 1 0 RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 00000000 R/W These registers control pull-up resistance in input mode. 0 : No pull-up resistance in input mode. 1 : Pull-up resistance applied in input mode. In output mode, the setting has no significance (no pull-up resistance) . The direction registers (DDR) control switching between input and output modes. In stop mode (SPL = 1) pull-up resistance is removed (high impedance) . When an external bus is used, this function is prohibited and no values should be written to this register. (4) Output Pin Registers ODR7 7 6 5 4 3 2 1 0 Default value Access Address : 00001EH OD75 OD74 OD73 OD72 OD71 OD70 00000000 R/W 00000000 R/W ODR4 Address : 00001BH 7 6 5 4 3 2 1 0 OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 These registers control open drain operation in output mode. 0 : Operates as standard output port in output mode. 1 : Operates as open drain port in output mode. In input mode, the setting has no significance (High-Z output) . The direction registers (DDR) control switching between input and output modes. When an external bus is used, this function is prohibited and no values should be written to this register. (5) Analog Input Enable Register ADER Address : 00001FH 7 6 5 4 3 2 1 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Default value Access 11111111 R/W Default value Access XX000000 R/W This register controls the port 6 pins as follows. 0 : Port input/output mode. 1 : Analog input mode. The register value is “1” at reset. (6) Up-down Timer Input Enable Mode UDER Address : 00000BH 7 6 5 4 3 2 1 0 UDE5 UDE4 UDE3 UDE2 UDE1 UDE0 This register controls the port 3 pins as follows. 0 : Port input mode 1 : Up-down timer input mode. The register value is “0” at reset. In the MB90470 series, the pin functions are as follows : UDE0 : P30/AIN0, UDE1 : P31/BIN0, UDE2 : P32/ ZIN0, UDE3 : P33/AIN1, UDE4 : P34/BIN1, UDE5 : P35/ZIN1 33 MB90470 Series 2. UART The UART is a serial I/O port for asynchronous (start-stop synchronized) communication or CLK synchronized communication. • Full duplex double buffer • Asynchronous (start-stop synchronized) and CLK synchronized (no start bit or stop bit) operation • Supports multi-processor modes • Built-in dedicated baud rate generator Asynchronous operation : 76923/38461/19230/9615/500 K/250 Kbps CLK synchronized : 16 M/8 M/4 M/2 M/1 M/500 K • Baud rate can be set independently from external clock • Can use internal clock feed from PPG1. • Data length : 7 bits (asynchronous normal mode only) or 8 bits • Master-slave communication functions (in multi-processor mode) : allows 1 (master) -to-n (slave) communications • Error detection functions (parity, framing, overrun) • NRZ-encoded transfer signal • DMAC support (receiving/sending) 34 MB90470 Series (1) Register List 8 7 15 0 CDCR SCR SMR SSR SIDR (R)/SODR (W) 8 bit 8 bit Serial mode register (SMR) Address : 000020H 7 6 5 4 3 2 1 MD1 MD0 CS2 CS1 CS0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (X) (R/W) (0) (R/W) (0) 15 14 13 12 11 10 9 8 PEN P SBL CL A/D REC RXE TXE (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (W) (1) (R/W) (0) (R/W) (0) Reserved SCKE 0 SOE Default value Serial control register (SCR) Address : 000021H Default value Serial input/output register (SIDR/SODR) Address : 000022H 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) Default value Serial data register (SSR) Address : 000023H 15 14 13 12 11 10 9 8 PE ORE FRE RDRF TDRE BDS RIE TIE (R) (0) (R) (0) (R) (0) (R) (0) (R) (1) (R/W) (0) (R/W) (0) (R/W) (0) Default value Communication prescaler control register (CDCR) Address : 000025H 15 14 13 12 11 10 9 8 MD SRST DIV3 DIV2 DIV1 DIV0 (R/W) (0) (R/W) (0) () () () () (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Default value 35 MB90470 Series (2) Block Diagram Control signal Receiving interrupt (to CPU) Dedicated baud rate generator PPG1 (internal connection) SCK0 TX clock Clock select circuit Sending interrupt (to CPU) RX clock External clock SIN0 Receiving control circuits Sending control circuits Start bit detect circuit Send start circuit Receiving bit counter Sending bit counter Receiving parity counter Sending parity counter SOT0 Receiving status judgement circuit DMAC receiving error transmission signal (to CPU) Receiving shifter Sending shifter Receiving control circuit Sending control circuit SIDR SODR F2MC-16LX BUS SMR register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR register PEN P SBL CL A/D REC REX TXE SSR register PE ORE FRE RDRF TDRE BDS RIE TIE Control signal 36 MB90470 Series 3. Expanded I/O Serial Interface The expended I/O serial interface is a serial I/O interface in 8-bit × 1 channel configuration allowing clock synchronized data transmission. The interface has two serial I/O operating modes. • Internal shift clock mode : Data transfer is synchronized with an internal clock. • External shift clock mode : Data transfer is synchronized with a clock input from an external pin (SCK) . This mode allows the external clock pin (SCK) to be shared with a general purpose port that can transfer data according to CPU instructions. (1) Register List Serial mode control status register (SMCS) Address : Address : 000027H 00002BH 000026H 00002AH 15 14 13 12 11 10 9 8 SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 MODE BDS SOE SCOE () () () () (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 0 0 0 0 0 0 1 0B Initial value - - - - 0 0 0 0B Serial data register (SDR) Address : 000028H 00002CH (R/W) Initial value XXXXXXXXB Communication prescaler control register (SDCR0, SDCR1) 000029H Address : 00002DH 15 14 13 12 11 10 9 8 MD DIV3 DIV2 DIV1 DIV0 (R/W) () () () (R/W) (R/W) (R/W) (R/W) Initial value 0 - - - 0000B 37 MB90470 Series (2) Block Diagram Internal data bus (MSB first) D0 to D7 D7 to D0 (LSB first) Default value Select transfer direction SIN1, 2 Read Write SDR (Serial data register) SOT1, 2 SCK1, 2 Control circuit Shift clock counter Internal clock 2 1 0 SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS Interrupt request Internal data bus 38 SOE SCOE MB90470 Series 4. 8/10-bit A/D Converter The A/D converter converts analog input voltages into digital values, and provides the following features : • Conversion time : minimum 4.9 µs per channel (at 98 machine cycles/machine clock 20 MHz, including sampling time) • Sampling time : minimum 3.0 µs per channel (at 60 machine cycles/machine clock 20 MHz) • Uses RC sequential comparison conversion with sample & hold circuit. • Selection of 8- or 10-bit resolution • Analog input from 8 channels, by program selection Single conversion mode : Convert 1 selected channel Scan conversion mode : Convert multiple consecutive channels. Select up to 8 channels by program selection. Continuous conversion mode : Convert specified channel continuously. Stop conversion mode : Convert one channel, pause and stand by until the next start. (Simultaneous conversion start available.) • At the end of A/D conversion, an A/D conversion end interrupt request can be sent to the CPU. This interrupt request can start the µDMA and transfer the conversion data to memory, making it ideal for continuous processing. • Start sources include selection of software, external trigger (falling edge) , or timer (rising edge) . (1) Register List ADCS2, ADCS1 (Control status registers) ADCS1 Address : 000046H ADCS2 bit Address : 000047H 7 6 5 4 3 2 1 0 MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 BUSY INT INTE PAUS STS1 STS0 STRT Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 W 0 R/W ←Default value ←Bit attributes ←Default value ←Bit attributes ADCR2, ADCR1 (Data registers) ADCR1 bit Address : 000048H ADCR2 bit Address : 000049H 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 X R X R X R X R X R X R X R X R 15 14 13 12 11 10 9 8 S10 ST1 ST0 CT1 CT0 D9 D8 0 R/W 0 W 0 W 0 W 0 W X R X R X R ←Default value ←Bit attributes ←Default value ←Bit attributes 39 MB90470 Series (2) Block Diagram AVCC AVRH AVSS D/A converter Input circuit MP Sequential comparison register Comparator Data bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Decoder Sample & hold circuit Data register ADCR1, ADCR2 A/D control register 1 ADTG A/D control register 2 Trigger start Timer (PPG1 output) Timer start φ 40 ADCS1, ADCS2 Operating clock Prescaler MB90470 Series 5. 8/16-bit PPG The 8/16-bit PPG is an 8-bit reload timer module that produces a PPG output in the form of a pulse for timer operation. The hardware configuration includes six 8-bit down counters, twelve 8-bit reload timers, three 16-bit control registers, six external pulse output pins, and six interrupt outputs. The MB90470 provides six 8-bit PPG channels, which can also operate as three 16-bit PPG channels in the combination PPG0 + PPG1, PPG2 + PPG3, PPG4 + PPG5. The following is an overview of the functions of the PPG. • Six-channel independent 8-bit PPG output mode : Provides PPG output operation independently on six channels. • 16-bit PPG output operation mode : Provides 16-bit PPG output operation on three channels, using the combination PPG0 + PPG1, PPG2 + PPG3, PPG4 + PPG5. • 8 + 8-bit PPG output operation mode : Uses the PPG0 (PPG2/PPG4) output as the PPG1 (PPG3/PPG5) clock input, to enable 8-bit PPG output with any desired period. • PPG output operation : Outputs pulse waves at a specified period and duty ratio. Can be also used with an external circuit as a D/A converter. 41 MB90470 Series (1) Register List PPGC0 (PPG0/2/4 operating mode control register) 00003AH 00003CH 00003EH 7 6 5 4 3 2 1 0 PEN0 PE00 PIE0 PUF0 Reserved (R/W) (0) () (X) (R/W) (0) (R/W) (0) (R/W) (0) () (X) () (X) () (1) Read/write Default value PPGC1 (PPG1/3/5 operating mode control register) 00003BH 00003DH 00003FH 15 14 13 12 11 10 9 8 PEN1 PE10 PIE1 PUF1 MD1 MD0 Reserved (R/W) (0) () (X) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) () (1) 1 0 Read/write Default value PPG01/PPG23/PPG45 (PPG0-PPG5 output control register) 000040H 000042H 000044H 7 6 5 4 3 PCS2 PCS1 PCS0 PCM2 PCM1 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 4 3 2 1 0 D04 D03 D02 D01 D00 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 12 11 10 9 8 D12 D11 D10 D09 D08 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) PPLL0 to PPLL5 (Reload register L) 00002EH 7 6 5 000030H D07 D06 D05 000032H (R/W) (R/W) (R/W) 000034H (X) (X) (X) 000036H 000038H PPLH0 to PPLH5 (Reload register H) 00002FH 15 14 13 000031H D15 D14 D13 000033H (R/W) (R/W) (R/W) 000035H (X) (X) (X) 000037H 000039H 42 2 PCM0 Reserved Reserved Read/write Default value Read/write Default value Read/write Default value MB90470 Series (2) Block Diagram • 8-bit PPG ch 0/2/4 Block Diagram Peripheral clock 16 divider Peripheral clock 8 divider Peripheral clock 4 divider Peripheral clock 2 divider Peripheral clock PPG 0/2/4 output enable PPG0/2/4 A/D converter PPG 0/2/4 output latch PEN0 S R Q PCNT (down counter) Count clock selection IRQ ch 1/3/5 borrow L/H selector Time base counter output clock 512 divider PUF0 PIE0 L/H selection PRLL PRLBH PPGC0 (output mode control) PRLL L data bus H data bus 43 MB90470 Series • 8-bit PPG ch 1/3/5 Block Diagram Peripheral clock 16 divider Peripheral clock 8 divider Peripheral clock 4 divider Peripheral clock 2 divider Peripheral clock PPG 1/3/5 output enable PPG1/3/5 UART0 PPG 1/3/5 output latch PEN1 S R Q PCNT (down counter) IRQ Count clock selection L/H selector Time base counter output clock 512 divider PUF1 PIE1 L/H selection PRLL PRLBH PPGC1 (output mode control) PRLL L data bus H data bus 44 MB90470 Series 6. 8/16-bit Up-down Counter/Timer This block is an up-down counter/timer configured with six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and related control circuits. (1) Principal functions • 8-bit count registers for counting in the range 0 to 256. (Also operates in 16-bit × 1 mode for counting in the range 0 to 65535.) • Count clock selection provides four count modes. Count mode Time mode Up/down count mode Phase differential count mode (2 × ) Phase differential count mode (8 × ) • In timer mode, there is a choice of two internal count clocks. Count clock 125 ns (8 MHz : divided by 2) (16 MHz operation) 0.5 µs (2 MHz : divided by 8) • In up/down count mode, there is a choice of external pin input signal detection edge. Detection edge Falling edge detection Rising edge detection Falling/rising edge, both edges’ detection Edge detection disabled • In phase differential count mode, to provide counts for encoders for motors, etc., the A phase, B phase, and Z phase of the encoder can be input separately for highly precise counts of rotation angle, rotary speed, etc. • The ZIN pin provides a choice of two functions. ZIN pin Counter clear function Gate function • Compare and reload functions are provided, each available independently or in combination. Both can be started together to provide any desired type of up/down count. Compare/reload function Compare function (outputs interrupt at compare events) Compare function (outputs interrupt and clears count at compare events) Reload function (outputs interrupt and reloads at underflow events) Compare/reload function (outputs interrupt and clears count at compare events, outputs interrupt and reloads at underflow events) Compare/reload disabled • Individually controllable interrupts at compare, reload (underflow) and overflow events. • Count direction flag enables detection of immediately preceding count direction. • Interrupt generation at change of count direction. 45 MB90470 Series (2) Register List 8 7 15 0 UDCR1 UDCR0 RCR1 RCR0 Reserved CSR0 CCRH0 CCRL0 Reserved CSR1 CCRH1 CCRL1 8 bit 8 bit CCRH0 (Counter control register high ch.0) Address : 00006DH 15 14 13 12 11 10 9 8 M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W R/W R/W Default value 00000000B CCRH1 (Counter control register high ch.1) Address : 000071H 15 14 13 12 11 10 9 8 CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W R/W Default value -0000000B CCRL0/1 (Counter control register low ch.0/1) Address : 00006CH Address : 000070H 7 6 5 4 3 2 1 0 UDMS CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 R/W W R/W R/W W R/W R/W R/W Default value 0X00X000B CSR0/1 (Counter status register ch. 0/1) Address : 000072H Address : 000074H 7 6 5 4 3 2 1 0 CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 R/W R/W R/W R/W R/W R/W R R Default value 00000000B UDCR0/1 (Up down count register ch. 0/1) Address : 000069H Address : 000068H 15 14 13 12 11 10 9 8 D17 D16 D15 D14 D13 D12 D11 D10 R R R R R R R R 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 R R R R R R R R Default value 00000000B Default value 00000000B RCR0/1 (Reload/compare register ch. 0/1) Address : 00006BH Address : 00006AH 46 15 14 13 12 11 10 9 8 D17 D16 D15 D14 D13 D12 D11 D10 W W W W W W W W 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 W W W W W W W W Default value 00000000B Default value 00000000B MB90470 Series (3) Block Diagram Data bus 8 bit RCR0 (Reload/compare register 0) CGE1 CGE0 CGSC ZIN0 Edge/level detection CTUT Reload control UCRE RLDE Counter clear UDCC 8 bit UCDR0 (Up/down count register 0) Carry CES1 CES0 CMS1 CMS0 UDFF OVFF Count clock UDMS AIN0 BIN0 CMPF Up-down count clock selection UDF1 UDF0 CDCF CFIE Prescaler CSTR CITE UDIE Interrupt output CLKS 47 MB90470 Series 7. DTP/External Interrupts The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L CPU. The DTP receives DMA request from external peripherals and passes the requests to the F2MC-16L CPU to activate the extended µDMA or interrupt processing. (1) Register Descriptions Interrupt/DTP enable register (ENIR : Enable Interrupt Request Register) ENIR Address : 00000CH 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W R/W Default value 00000000B Interrupt/DTP source register (EIRR : External Interrupt Request Register) EIRR Address : 00000DH 15 14 13 12 11 10 9 8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 R/W R/W R/W R/W R/W R/W R/W R/W Default value 00000000B (note that both registers relate to different interrupts) Request level setting register (ELVR : External Level Register) 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 R/W R/W R/W R/W R/W R/W R/W R/W Address : 00000EH Address : 00000FH Default value 00000000B Default value 00000000B (2) Block Diagram F2MC-16 bus 4 4 4 8 48 Interrupt/DTP enable register Gate Source F/F Interrupt/DTP source register Interrupt level setting register Edge detection circuit 4 Request input MB90470 Series 8. 16-bit Input Output Timer The 16-bit input/output timer is composed of one 16-bit free-run timer module, 6 output compare modules, and 2 input capture modules. These functions can be used to produce output of six independent wave forms based on the 16-bit free-run timer, with input pulse width measurement and external clock period measurement. • List of Registers for All Modules • 16-bit free-run timer 15 0 000066/67H CPCLR 000062/63H TCDT Timer data register 000064/65H TCCS Control status register Compare clear register • 16-bit output compare 15 0 00004A, 4C, 4E, 50, 52, 54H 00004B, 4D, 4F, 51, 53, 55H OCCP0 to OCCP5 000056, 58, 5AH 000057, 59, 5BH OCS1/3/5 Compare register Control status register OCS0/2/4 • 16-bit input capture 15 00005C, 5EH 00005D, 5FH 000060H 0 IPCP0, ICCP1 Compare register ICS Control status register 49 MB90470 Series • Overall Block Diagram To blocks Control logic Interrupt 16-bit free-run timer 16-bit timer Clear Output compare 0 Bus Output compare 1 Output compare 2 Output compare 3 Output compare 4 Output compare 5 Compare register 0 TQ OUT0 Compare register 1 TQ OUT1 Compare register 2 TQ OUT2 Compare register 3 TQ OUT3 Compare register 4 TQ OUT4 Compare register 5 TQ OUT5 Input capture 0 Capture register 0 Edge selection IN0 Capture register 1 Edge selection IN1 Input capture 1 50 MB90470 Series (1) 16-bit Free-run Timer The 16-bit free-run timer is composed of a 16-bit up-down counter and control register. The count value from this timer is used as the base timer for the input capture and output compare modules. • A selection of 8 clock types for counter operation is available. • Counter overflow interrupts can be generated. • By a mode setting, the counter can be initialized when the timer value matches the compare register value for the output compare module. • Register list Compare clear register (CPCLR) 000067H 000066H 15 14 13 12 11 10 9 8 CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Default value XXXXXXXXB Default value XXXXXXXXB Timer counter data register (TCDT) 000063H 000062H 15 14 13 12 11 10 9 8 T15 T14 T13 T12 T11 T10 T09 T08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 T07 T06 T05 T04 T03 T02 T01 T00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Default value 00000000B Default value 00000000B Timer counter control/status register (TCCS) 000065H 000064H 15 14 13 12 11 10 9 8 ECKE MSI2 MSI1 MSI0 ICLR ICRE (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Default value 0--00000B Default value 00000000B 51 MB90470 Series • Block Diagram φ Interrupt request IVF Frequency divider IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Bus Clock 16-bit free-run timer Count value output T15 to T00 16-bit compare clear register Compare circuit MSI3 to 0 ICLR ICRE Interrupt request A/D converter startup 52 MB90470 Series (2) Output Compare The output compare module consists of a 16-bit compare register, compare output pin unit, and control register. When the value in the compare register in this module matches the value of the 16-bit free-run timer, the pin output level can be inverted and an interrupt generated. • There are six compare registers that can operate independently. Module settings can be used to use the two compare registers to control the output. • The interrupt can be set by a compare match. • Register List Compare register (OCCP0 to OCCP5) 15 00004BH 00004DH 00004FH 000051H 000053H 000055H 00004AH 00004CH 00004EH 000050H 000052H 000054H 14 13 12 11 10 9 8 C15 C14 C13 C12 C11 C10 C09 C08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 6 5 4 3 2 1 0 C07 C06 C05 C04 C03 C02 C01 C00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 CMOD OTE1 OTE0 OTD1 OTD0 () () () (R/W) (R/W) (R/W) (R/W) (R/W) Default value XXXXXXXXB Default value XXXXXXXXB Control register (OCS1/3/5) 000057H 000059H 00005BH Default value ---00000B Control register (OCS0/2/4) 000056H 000058H 00005AH 7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 CST1 CST0 (R/W) (R/W) (R/W) (R/W) () () (R/W) (R/W) Default value 0000--00B 53 MB90470 Series • Block Diagram 16-bit timer counter value (T15 to T00) Compare control TQ OTE0 OUT0 (2) (4) OTE1 OUT1 (3) (5) Compare register 0 (2) CMOD Bus 16-bit timer counter value (T15 to T00) Compare control TQ Compare register 1 (3) ICP1 Control unit Control blocks 54 ICP0 ICE0 ICE0 Compare 1 (3) (5) interrupt Compare 0 (2) (4) interrupt MB90470 Series (3) Input Capture The input capture module detects the rising edge, falling edge, or both edges of an input signal and saves the value of the 1-bit free-run timer at that moment in a register. This module can also generate an interrupt when an edge is detected. The input capture module is composed of input capture registers and a control register. Each of the input captures has a corresponding external input pin. • Selection of three valid edges for external input : Rising edge/falling edge/both edges • An interrupt can be generated when the valid edge is detected. • Register List Input capture data registers (IPCP0, IPCP1) 00005DH 00005FH 00005CH 00005EH 15 14 13 12 11 10 9 8 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 (R) (R) (R) (R) (R) (R) (R) (R) 7 6 5 4 3 2 1 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 (R) (R) (R) (R) (R) (R) (R) (R) Default value XXXXXXXXB Default value XXXXXXXXB Control status register (ICS0, ICS1) 000060H 7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Default value 00000000B • Block Diagram Bus Capture data register 0 Edge detection 16-bit timer counter value (T15 to T00) EG11 EG10 EG01 EG00 Capture data register 1 ICP1 Edge detection ICP0 IN0 ICE1 IN1 ICE0 Interrupt Interrupt 55 MB90470 Series 9. I2C Interface The I2C interface is a serial I/O port supporting Inter IC bus operation, and operates as a master/slave device on the I2C bus. The following features are provided. • Master/slave sending and receiving • Arbitration functions • Clock synchronization functions • Slave address/general call address detection functions • Transfer direction detection function • Start condition repeat generator and detection function • Bus error detection function (1) Register List IBSR (bus status register) Address : 000088H Read/write Default value 7 6 5 4 3 2 1 0 BB RSC AL LRB TRX AAS GCA FBT (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 15 14 13 12 11 10 9 8 BER BEIE SCC MSS ACK GCAA INTE INT (R/W) (0) (R/W) (0) (R/W) (0) (R/W) ( 0) (R/W) (0) (R/W) (0) (R/W) (0) Bit no. IBCR (bus control register) Address : 000089H Read/write Default value (R/W) (0) Bit no. ICCR (clock control register) Address : 00008AH Read/write Default value 7 6 5 4 3 2 1 0 EN CS4 CS3 CS2 CS1 CS0 () () () () (R/W) (0) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 15 14 13 12 11 10 9 8 A6 A5 A4 A3 A2 A1 A0 () () (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) Bit no. IADR (address register) Address : 00008BH Read/write Default value (R/W) (X) Bit no. IDAR (data register) Address : 00008CH Read/write Default value 56 (R/W) (X) Bit no. MB90470 Series (2) Block Diagram ICCR I2C enable F2MC-16 bus EN Clock divider 1 6 7 8 5 ICCR CS4 CS3 Peripheral clock Clock select 1 Clock divider 2 2 4 8 16 32 64 128 CS2 CS1 CS0 256 RSC LRB TRX Shift clock generator Clock select 2 Shift clock edge change timing IBSR BB Sync Bus busy Repeat start Start/stop condition detector Last Bit Error Send/receive First Byte FBT AL Arbitration lost detector IBCR SCL BER BEIE Interrupt request IRQ SDA INTE INT End IBCR SCC MSS ACK GCAA Start Master ACK enable Start/stop condition generator GC-ACK enable IDAR IBSR AAS GCA Slave Global call Slave address compare IADR 57 MB90470 Series 10. 16-bit reload timer The 16-bit reload timer provides a choice of two functions, one is an internal clock countdown synchronized with any of 3 types of internal clock, and the other is an event count mode that counts down at detection of a given edge of a pulse input externally. This timer defines an underflow as a transition of the count value from 0000H to FFFFH. Therefore, an underflow will occur at the count value “reload register setting count + 1”. The count operation includes a choice of reload mode in which the count set value is reloaded at each underflow event, and one-shot mode in which the count stops at an underflow event. An interrupt can be generated when the counter reaches an underflow, and the timer is DTC compatible. (1) Register List • TMCSR (Timer control status registers) Timer control status register (high) 0000CBH 15 14 13 12 11 10 9 8 CSL1 CSL0 MOD2 MOD1 () () () () () () () () (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Read/write Default value Timer control status register (low) 0000CAH 7 6 5 4 3 2 1 0 MOD0 OUTE OUTL RELD INTE UF CNTE TRG (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Read/write Default value • 16-bit timer register/16-bit reload register TMR/TMRLR (high) 0000CDH 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D09 D08 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) Read/write Default value TMR/TMRLR (low) 0000CCH 58 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) Read/write Default value MB90470 Series (2) Block Diagram Internal data bus TMRLR 16-bit reload register Reload signal TMR 16-bit timer register (down counter) Reload control circuit UF CLK Count clock generator circuit Machine clock φ Prescaler 3 Gate input Wait signal Valid clock decision circuit Clear CLK To A/D converter Pin (TIN0) Input control circuit Clock selector Invert Output signal generator circuit Output signal generator circuit EN External clock OUTL Function select 3 Select signal Pin (TOT0) 2 RELD Operation control circuit OUTE Timer control status register (TMCSR) 59 MB90470 Series 11. µPG Timer The µPG timer produces a pulse output according to an external input signal. (1) Register List PGCSR (PG control/status register) Operating mode control register 00008EH 7 6 5 4 3 2 1 0 PEN0 PE1 PE0 PMT1 PMT0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) () () () () () () Read/write Default value (2) Block Diagram MT00 MT01 Output enable MT00 output latch MT00 output latch Control circuit 60 EXTC MB90470 Series 12. PWC (Pulse Width Count) Timer The PWC timer is a 16-bit multi-function up-count timer with an input signal pulse width measurement function. The hardware includes a total of three channels, each with one 16-bit up-count timer, one input pulse divider and divider ration control register, one measurement input pin, and one 16-bit control register. The following functions are provided : Timer functions : An interrupt can be generated each time a set time interval elapses. A choice of three internal reference clocks is available. Pulse width measurement functions : Measures the time between designated events on an externally input pulse signal. The reference clock is selected from three internal clock signals. Measurement modes : 1) H pulse width (↑ to ↓) /L pulse width (↑ to ↓) 2) Rise period (↑ to ↑) /fall period (↓ to ↓) 3) Measurement between edges (high or low to low or high) An 8-bit input divider can divide the input pulse into 22n divisions (n = 1, 2, 3, 4) and measure the divisions. An interrupt can be generated when measurement is ended. Both one-time and continuous measurement are enabled. 61 MB90470 Series (1) Register List 8 7 15 0 PWCSR0 to PWCSR2 (R/W) PWC0 to PWC2 (R/W) DIVR0 to DIVR2 (R/W) PWCSR0 to PWCSR2 (PWC control/status registers) 000077H 00007BH 00007FH 000076H 00007AH 00007EH 15 14 13 12 11 10 9 8 STRT STOP EDIR EDIE OVIR OVIE ERR Reserved (R/W) (0) (R/W) (0) (R) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R) (0) () (X) 7 6 5 4 3 2 1 0 CKS1 CKS0 PIS1 PIS0 S/C MOD2 MOD1 MOD0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Read/write Default value Read/write Default value PWCR0 to PWCR2 (PWC data buffer registers) 000079H 00007DH 000081H 000078H 00007CH 000080H 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Read/write Default value Read/write Default value DIVR0 to DIVR2 (Divider control register) 000082H 000084H 000086H 62 7 6 5 4 3 2 1 0 DIV1 DIV0 () (X) () (X) () (X) () (X) () (X) () (X) (R/W) (0) (R/W) (0) Read/write Default value MB90470 Series (2) Block Diagram PWCR read Error detector ERR PWCR 16 Internal clock (machine clock / 4) Reload Data transfer 16 Clock Overflow 22 16-bit up/down timer Clock divider F2MC-16 bus Timer clear Control bit output Flag set etc. Control circuit Start edge End edge selection selection Measure start edge Edge detection Measure end edge Measurement end interrupt request Overflow interrupt request 15 PWCSR CKS1/CKS0 Count enable Input waveform comparator Divider on/off PIS0/PIS1 ERR 23 Divider clear PWC0 PWC1 8-bit divider CKS0/CKS1 Divider select 2 DIVR 63 MB90470 Series 13. Watch Timer The watch timer is a 15-bit timer using a sub-clock signal. This timer can generate interval interrupts. Also, by a register setting, it can be used as a clock source for the watchdog timer. (1) Register List Watch timer control register (WTC) 0000AAH 7 6 5 4 3 2 1 0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 (R/W) (1) (R) (0) (R/W) (0) (R/W) (0) (R/W) (1) (R/W) (0) (R/W) (0) (R/W) (0) WTC2 WTC1 WTC0 Default value (2) Block Diagram Watch timer control register (WTC) WDCS SCE WTIE WTOF WTR Clear 28 29 Sub-clock Watch counter 210 211 Interval selector Interrupt generator circuit Watch timer interrupt 212 213 210 213 214 215 214 To watchdog timer 64 MB90470 Series 14. Watchdog Timer The watchdog timer is a 2-bit counter that uses a count clock signal output by the timer base timer or watch timer and will reset the CPU unless cleared within a specified period of time. (1) Register List Watchdog timer control register (WDTC) 7 0000A8H 6 4 3 2 1 0 PONR Reserved WRST ERST SRST WTE WT1 WT0 () (X) (R) (X) (R) (X) (W) (1) (W) (1) (W) (1) (R) (X) 5 (R) (X) Default value (2) Block Diagram Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE WT1 WT0 Watch timer control register (WT0) WDCS bit Clock select register (CKSCR) SCM bit 2 Watch mode start Time base timer mode start Sleep mode start Hold status start CLR and start Watchdog timer Count clock selector Counter clear control circuit Stop mode start 2-bit counter CLR Watchdog reset generator circuit Internal reset generator circuit CLR 4 Clear 4 Time base counter HCLK signal / 2 × 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 SCLK × 21 × 2 2 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 HCLK : Oscillator clock SCLK : Sub-clock 65 MB90470 Series 15. Time Base Timer The time base timer is an 18-bit free-run timer that counts up in synchronization with the internal count clock (base oscillator divided by 2) . It functions as an interval timer with a selection of four types of time intervals. Other functions of this timer also include output of a timer signal for the oscillator stabilization wait time and an operating clock signal for the watchdog timer. (1) Register List Time base timer control register (TBTC) 0000A9H 15 14 13 12 11 10 9 8 RESV TBIE TBOF TBR TBC1 TBC0 (R/W) (1) () (X) () (X) (R/W) (0) (R/W) (0) (W) (1) (R/W) (0) (R/W) (0) (2) Block Diagram To PPG timer To watchdog timer Time base timer/ counter HCLK signal /2 × 21 × 2 2 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 OF OF Power-on reset Stop mode start Mode start Hold status start CKSCR : MCR = 1 → 0*1 CKSCR : SCS = 0 → 1*2 OF OF Clock control unit Oscillator stabilization wait To interval selector Counter clear control circuit Interval timer selector TBOF set TBOF clear Time base timer control register (TBTC) RESV TBIE TBOF TBR TBC1 TBC0 Time base timer interrupt signal OF HCLK *1 *2 66 : Not used : Overflow : Oscillator clock : Switches machine clock from main clock or sub-clock to PLL clock. : Switches machine clock from sub-clock to main clock. MB90470 Series 16. Clock The clock generator module controls the operation of the internal clocks that produce the operating clock signals for the CPU and peripheral devices. This internal clock signal is called the machine clock, and one period is called a machine cycle. The clock signal from the base oscillator is called the oscillator clock, and the clock signal generated by the internal PLL module is called the PLL clock. (1) Register List Clock select register (CKSCR) 0000A1H 15 14 13 12 11 10 9 8 SCM MCM WS1 WS0 SCS MCS CS1 CS0 (R) (1) (R) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (0) ( R/W ) (0) Default value 67 MB90470 Series (2) Block Diagram Standby control circuit Low power mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved RST pin Pin High-Z control circuit Pin high-impedance control Internal reset generator circuit Internal reset CPU intermittent operation selector Intermittent cycle selection CPU clock control circuit Standby control circuit Interrupt release CPU clock Stop, sleep signals Stop signal Peripheral clock control circuit Machine clock Oscillator stabilization wait release Clock generator module Clock selector Divide by 4 2 2 SCM MCM WS1 WS0 SCS MCS CS1 CS0 Sub-clock generator circuit pin X1A pin Oscillator stabilization wait period selector SCLK PLL multiplier circuit X0A Clock select register (CKSCR) System clock generator circuit Divide by 2 HCLK X0 pin X1 pin Divide by 1024 Divide by 2 Divide by 4 Divide by 4 Divide by 4 MCLK Time base timer To watchdog timer HCLK : Oscillator clock MCLK : Main clock SCLK : Sub-clock 68 Peripheral clock Divide by 2 MB90470 Series (3) Clock Signal Supply Map 4 Clock generator ratio Peripheral function Watchdog timer 4 Watch timer X0A pin X1A pin Sub-clock generator circuit 8/16-bit PPG timer 0 PPG0, PPG1 pin 8/16-bit PPG timer 1 PPG2, PPG3 pin 8/16-bit PPG timer 2 PPG4, PPG5 pin Time base timer 1 2 3 4 PLL multiplier circuit Divide by 4 X0 pin X1 pin SCLK System clock generator circuit Divide by 2 HCLK TIN0 pin PCLK Clock selector 16-bit reload timer φ TOT0 pin MCLK SCK0, SIN0 pin UART CPU, µDMA I/O expansion serial interface 2 ch SOT0 pin SCK1, SCK2, SIN1, SIN2 pin SOT1, SOT2 pin AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 8/16-bit U/D counter Chip select 16-bit output compare pin CS0, CS1, CS2, CS3 pin OUT0, OUT1,OUT2, OUT3, OUT4, OUT5 pin 16-bit free-run timer FRCK pin 16-bit input capture IN0, IN1 pin 10-bit A/D converter AN0 to AN7, ADTG pin External interrupt IRQ0 to IRQ7 pin IN0, IN1 pin µPG HCLK MCLK SCLK PCLK φ : Oscillator clock : Main clock : Sub-clock : PLL clock : Machine clock I2C interface 16-bit PWC 3ch 3 MT00, MT01 pin SCL, SDA pin PWC1, PWC2, PWC3 pin Oscillator stabilization wait control 69 MB90470 Series 17. Low Power Modes The MB90470 series uses a selection of operating clock signals and clock operation controls to provide the following CPU operating modes. • Clock modes (PLL clock mode, main clock mode, sub-clock mode) • CPU intermittent operation modes (PLL clock intermittent operation mode, main clock intermittent operation mode, sub-clock intermittent operation mode) • Standby mode (Sleep mode, time base timer mode, stop mode, watch mode) (1) Register List Low power mode control register (LPMCR) 7 0000A0H 70 6 5 4 3 2 1 0 STP SLP SPL RST TMD CG1 CG0 Reserved (W) (0) (W) (0) (R/W) (0) (W) (1) (R/W) (1) (R/W) (0) (R/W) (0) (R/W) (0) Default value MB90470 Series (2) Block Diagram Standby control circuit Low power mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved RST pin Pin High-Z control circuit Pin high-impedance control Internal reset generator circuit Internal reset CPU intermittent operation selector Intermittent cycle selection CPU clock control circuit Standby control circuit Interrupt release CPU clock Stop, sleep signals Stop signal Peripheral clock control circuit Machine clock Oscillator stabilization wait release Clock generator module Clock selector Divide by 4 SCLK 2 SCM MCM WS1 WS0 SCS MCS CS1 CS0 Sub-clock generator circuit pin X1A pin Oscillator stabilization wait period selector 2 PLL multiplier circuit X0A Peripheral clock Clock select register (CKSCR) System clock generator circuit Divide by 2 HCLK X0 pin X1 pin Divide 1024 Divide by 2 Divide by 4 Divide by 4 Divide by 4 Divide by 2 MCLK Time base timer To watchdog timer HCLK : Oscillator clock MCLK : Main clock SCLK : Sub-clock 71 MB90470 Series (3) Status Transition Chart External reset, watchdog timer reset, software reset Power on Reset SCS = 0 Power-on reset Oscillator stabilization wait end SCS = 1 MCS = 0 Main clock mode SLP = 1 MCS = 1 Interrupt Main sleep mode TMD = 0 Interrupt SCS = 0 PLL clock mode SLP = 1 TMD = 0 Oscillator stabilization wait end Main clock oscillator stabilization wait 72 Interrupt Time base timer mode STP = 1 Main stop mode Interrupt Interrupt PLL sleep mode Time base timer mode STP = 1 SCS = 1 SLP = 1 Interrupt Sub-sleep mode TMD = 0 Interrupt Watch mode STP = 1 PLL stop mode Interrupt Sub-clock mode Oscillator stabilization wait end Main clock oscillator stabilization wait Sub-stop mode Interrupt Oscillator stabilization wait end Sub-clock oscillator stabilization wait MB90470 Series 18. Overview of the Chip Select Function This module issues chip select signals in order to facilitate connection to external memory. There are four chip select output pins, with hardware areas set using a register for each output, so that the select signal is output from the related pin whenever access to an external address is detected. • Features of the chip select function The chip select function has two 8-bit registers for settings for each of the four output pins. One register (CARx) is used to specify the upper 8 bits of the address for match detection, thereby providing memory area detection in 64 KB units. The other register (CMRx) can be set to detect areas larger than 64 KB by masking bits in the match detection value. Note that the CS output is set to high impedance during a bus hold condition. (1) Register List 8 7 15 0 (R/W) CAR0 CMR0 (R/W) CAR1 CMR1 (R/W) CAR2 CMR2 (R/W) CAR3 CMR3 (R/W) CALR CSCR (R/W) Chip select area MASK register (CMRx) 0000C0H 0000C2H 0000C4H 0000C6H 7 6 5 4 3 2 1 0 M7 M6 M5 M4 M3 M2 M1 M0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (1) (R/W) (1) (R/W) ( 1) (R/W) (1) Read/write Default value Chip select area register (CARx) 0000C1H 0000C3H 0000C5H 0000C7H 15 14 13 12 11 10 9 8 A7 A6 A5 A4 A3 A2 A1 A0 (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) Read/write Default value Chip select control register (CSCR) 0000C8H 7 6 5 4 3 2 1 0 OPL3 OPL2 OPL1 OPL0 () () () () () () () () (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (∗) Read/write Default value Chip selector active level register (CALR) 0000C9H 15 14 13 12 11 10 9 8 ACTL3 ACTL2 ACTL1 ACTL0 () () () () () () () () (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Default value 73 MB90470 Series FMC-16 bus (2) Block Diagram CMRx CARx Chip select output pin A23 to A16 74 MB90470 Series 19. ROM Mirror Function Select Module The ROM mirror function select module provides a register selection that allows the FF bank in ROM to be viewed in the 00 bank. (1) Register List bit ROMM Address : 00006FH 15 14 13 12 11 10 9 8 MI Default value - - - - - - - 1B W W : Write only - : Not used (2) Block Diagram F2MC-16LX ROM mirror function select Address area 00 bank FF bank ROM Note : Do not access this register during operations to address 004000H to 00FFFFH. 75 MB90470 Series 20. Interrupt Controller The interrupt control registers are located in the interrupt controller. An interrupt control register is provided for each I/O with an interrupt function. The registers have the following functions. • Set the interrupt level of the corresponding peripheral. (1) Register List Interrupt control register Address: ICR01: 0000B1H ICR03: 0000B3H bit ICR05: 0000B5H ICR07: 0000B7H 15 ICR09: 0000B9H ICR11: 0000BBH ICR13: 0000BDH ICR15: 0000BFH Read/Write→ (W) Initial value→ (0) 14 13 12 11 10 9 8 IL2 IL1 IL0 - - - Reserved (W) (0) (W) (0) (W) (0) (R/W) (0) 14 13 12 11 (R/W) (R/W) (1) (1) ICR01, 03, 05, 07, 09, 11, 13, 15 (R/W) (1) Address: ICR00: 0000B0H bit ICR02: 0000B2H ICR04: 0000B4H ICR06: 0000B6H ICR08: 0000B8H ICR14: 0000BEH 15 - Read/Write→ (W) Initial value→ (0) - - - Reserved (W) (0) (W) (0) (W) (0) (R/W) (0) 10 IL2 9 8 IL1 IL0 (R/W) (R/W) (1) (1) ICR00, 02, 04, 26, 08, 10, 12, 14 (R/W) (1) Note : Do not access these registers using read-modify-write instructions as this can cause misoperation. (2) Block Diagram F2MC-16LX Bus 3 76 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Re se r ve d 3 I L2 I L1 IL0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 32 Interrupt request (peripheral resource) Determine priority of interrupt 3 (CPU) Interrupt level MB90470 Series 21. µDMA µDMA is the simplified DMA which has the equivalent function to EI2OS function µDMA has DMA transfer channel which consists of 16 channels and has the following functions. • Automatic data transfer between peripheral resources (I/O) and memory. • CPU program executing stops dring DMA operation. • Selectable for address transfer increase/decrease . • DMA transfer control is done at DMA enable register, DMA stop status register, DMA status register and descriptor. • Stop request stops DMA transfer from resources. • After DMA transfer, flag is set to bit corresponding to DMA status register transfer stop channel and stop interrupt is output to interrupt controller. (1) Register List DMA enable register bit DERH : 0000ADH 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0B EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 Initial value STP7 STP6 STP5 STP4 STP3 STP2 STP1 STP0 0 0 0 0 0 0 0 0B (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 Initial value DE15 DE14 DE13 DE12 DE11 DE10 DE9 DE8 0 0 0 0 0 0 0 0B (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 Initial value DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 0 0 0 0 0 0 0 0B ( R/W ) ( R/W ) ( R/W ) ( R/W ) (R/W) (R/W) (R/W) (R/W) DMA enable register bit DERL : 0000ACH Initial value 0 0 0 0 0 0 0 0B DMA stop status register bit DSSR : 0000A4H DMA status register bit DSRH : 00009DH DMA status register bit DSRL : 00009CH 77 MB90470 Series (2) Block Diagram Memory area by IOA I/O register I/O register DER read DMA controller At transfer stop by BAP Buffer by DCT Transfer IOA : Address pointer BAP : Buffer address pointer DER : DMA enable register (ENx selection is done.) DTC : Data counter 78 CPU Interrupt controller F2MC-16LX Bus DMA transfer request Not transfer stop DMA descriptor Peripheral functions (I/O) MB90470 Series 22. External Bus Pin Control Circuit The external bus pin control circuit controls the external bus pins used to expand the CPU address/data bus connections to external circuits. (1) Register List • Auto ready function select register (ARSR) Address : 0000A5H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ICR1 ICR0 HMR1 HMR0 LMR1 LMR0 W W W W W W Initial value 0011- - 00B • External address output control register (HACR) Address : 0000A6H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 E23 E22 E21 E20 E19 E18 E17 E16 W W W W W W W W Initial value 00000000B • Bus control signal select register (EPCR) Address : 0000A7H W − * bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 CKE RYE HDE ICBS HMBS WRE LMBS W W W W W W W Initial value 1000∗10 -B : Write only : Not used : May be either “1” or “0” (2) Block Diagram P5 P0 P0 data P1 P2 P3 P4 P5 P0 P0 direction RB Data control Address control Access control Access control 79 MB90470 Series 23. Address Match Detection Function When the address is equal to a value set in the address detection register, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function to be implemented. Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code. (1) Register Configuration • Program address detection register 0 to 2 (PADR0) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W PADR0 (Low order address): 001FF0H Address PADR0 (Middle order address): 001FF1H Address PADR0 (High order address): 001FF2H Initial value XXXXXXXX B Initial value XXXXXXXX B Initial value XXXXXXXX B • Program address detection register 3 to 5 (PADR1) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W R/W R/W R/W R/W R/W R/W R/W bit 3 bit 2 bit 1 bit 0 AD0E RESV R/W R/W PADR1 (Low order address): 001FF3H Address PADR1 (Middle order address): 001FF4H Address PADR1 (High order address): 001FF5H Initial value XXXXXXXX B Initial value XXXXXXXX B Initial value XXXXXXXX B • Program address detection control status register (PACSR) Address bit 7 00009EH RESV R/W R/W :Readable and writable X :Undefined RESV:Reserved bit 80 bit 6 bit 5 RESV RESV R/W R/W bit 4 RESV AD1E RESV R/W R/W R/W Initial value 00000000 B MB90470 Series Internal data bus Address latch Address detection register Enable bit Compare (2) Block Diagram INT9 instruction F2MC-16LX CPU core 81 MB90470 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter (VSS = AVSS = 0.0 V) Symbol Rating Unit Remarks Min Max VCC3 VSS − 0.3 VSS + 4.0 V VCC5 VSS − 0.3 VSS + 7.0 V AVCC VSS − 0.3 VSS + 4.0 V AVRH VSS − 0.3 VSS + 4.0 V VSS − 0.3 VSS + 4.0 V *2 VSS − 0.3 VSS + 7.0 V *2 VSS − 0.3 VSS + 4.0 V *2 VSS − 0.3 VSS + 7.0 V *2 ICLAMP − 2.0 + 2.0 mA *6 Σ| ICLAMP | 20 mA *6 IOL 10 mA *3 “L” level average output current IOLAV 3 mA *4 “L” level maximum total output current ΣIOL 60 mA ΣIOLAV 30 mA *5 IOH − 10 mA *3 “H” level average output current IOHAV −3 mA *4 “H” level maximum total output current ΣIOH − 60 mA ΣIOHAV −30 mA Power consumption PD 410 mW Operating temperature TA − 40 + 85 °C Tstg − 55 + 150 °C Supply voltage Input voltage VI Output voltage VO Maximum clamp current Total maximum clump current “L” level maximum output current “L” level average total output current “H” level maximum output current “H” level average total output current Storage temperature *1 *5 *1: AVCC and AVRH must not exceed VCC3. Also, AVRH must not exceed AVCC ,too. *2: VI, and VO must not exceed VCC (including VCC3, VCC5) plus 0.3 V. *3: Maximum output current is defined as the peak value at one corresponding pin. *4: Average output current is defined as the average current flowing through one corresponding pin in an interval of 100 ms. *5: Average total output current is defined as the total average current flowing through all corresponding pins in an interval of 100 ms. *6: 82 • Applicable to pins: General purpose CMOS input port (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA3) • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. (Continued) MB90470 Series (Continued) • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Sample recommended circuits: • Input/output equivalent circuits Protective diode Vcc P-ch Limiting resistance +B input (0 V to 16 V) N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 83 MB90470 Series 2. Recommended Operating Conditions Parameter Symbol (VSS = AVSS = 0.0 V) Value Unit Max 1.8 3.6 V MASK version 2.4 3.6 V Low voltage FLASH version 3.0 3.6 V High speed FLASH version 1.8 5.5 V MASK version 2.4 5.5 V Low voltage FLASH version 3.0 5.5 V High speed FLASH version 1.8 3.6 V Hold stop status 1.8 5.5 V Hold stop status (MASK version) 1.8 5.5 V Hold stop status (FLASH version) VIH 0.7 VCC VCC + 0.3 V All pins other than VHIS, VIHM pins VIHS 0.8 VCC VCC + 0.3 V Hysteresis input pins VIHM VCC − 0.3 VCC + 0.3 V MD pin input VIL VSS − 0.3 0.3 VCC V All pins other than VILS, VILM pins VILS VSS − 0.3 0.2 VCC V Hysteresis input pins VILM VSS − 0.3 VSS + 0.3 V MD pin input TA − 40 + 85 °C VCC3* VCC5* Supply voltage VCC3 VCC5 “H” level input voltage “L” level input voltage Operating temperature Remarks Min * : Pay attention to operating frequency. Note : When using I2C functions, the voltage should be at least 2.4 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 84 MB90470 Series 3. DC Characteristics (MASK version : VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) * (Low voltage FLASH version : VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) * (High speed FLASH version : VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) * Parameter “H” level output voltage “L” level output voltage Symbol VOH VOL Pin name Remarks Max VCC = 2.7 V IOH = − 1.6 mA VCC3 − 0.3 V VCC = 4.5 V IOH = − 4.0 mA VCC5 − 0.5 V VCC = 2.7 V IOL = 2.0 mA 0.4 V VCC = 4.5 V IOL = 4.0 mA 0.4 V VCC = 3.3 V VSS < VI < VCC − 10 + 10 µA VCC = 3.0 V, at TA = + 25 °C 20 65 200 kΩ 0.1 10 µA 60 80 mA MASK version 65 85 mA 51 66 mA FLASH version 56 71.5 mA at VCC = 3.3 V, flash write/erase at internal 20 MHz 57 71.5 mA FLASH version VCC = 3.3 V, sleep mode at 20 MHz 18 33 mA at VCC = 3.3 V, sub operation, external 32 kHz, internal 8 kHz operation (TA = + 25 °C) 16 140 µA All pins except P76-P77 All output pins All pins except P76, P77 Pull-up resistance RPULL Open drain output current Ileak P40 to P47, P70 to P77 Supply current ICCL Unit Typ IIL ICCS Value Min Input leak current ICC Conditions at VCC = 3.3 V, at normal internal 20 MHz operation Using 5 V system power supply Using 5 V system power supply MASK version (A/D operation) FLASH version (A/D operation) * : Pay attention to operating frequency. (Continued) 85 MB90470 Series (Continued) Parameter (MASK version : VCC = 1.8 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) * (Low voltage FLASH version : VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) * (High speed FLASH version : VCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) * Symbol Pin name Conditions ICCT Unit Remarks 40 µA MASK version 15 40 µA FLASH version 0.1 20 µA MASK version 0.2 40 µA FLASH version 5 15 pF Min Typ Max 10 at VCC = 3.3 V, watch operation, external 32 kHz, internal 8 kHz operation (TA = + 25 °C) ICCH TA = + 25 °C, stop mode, at VCC = 3.3 V CIN All pins except AVCC, AVSS, VCC, VSS Supply current Input capacitance Value * : Pay attention to operating frequency. Notes : • Pins P40-P47 and P70-P75 are N-ch open drain pins with controls, and normally used at CMOS level. • P76 and P77 are N-ch open drain pins. • VCC = VCC3 = VCC5. • When using two power supplies, the 5 V system pins are P20 to P27, P30 to P37, P40 to P47 and P70 to P77. All other pins are 3 V input/output pins. 86 MB90470 Series 4. AC Characteristics (1) Clock Timing Ratings Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rise, fall time (VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol FCH X0, X1 Conditions Value Min Typ Max 3 20 Unit MHz 3 40 Remarks for crystal oscillation*2 for external clock FCL X0A, X1A 32.768 kHz tC X0, X1 25 333 ns tCL X0A, X1A 30.5 µs PWH PWL X0 5 ns *1 PWLH PWLL X0A 15.2 µs *1 tcr tcf X0 5 ns Using external clock 1.5 20 MHz *2 1.5 16 MHz MB90474 only 8.192 kHz 3 20 MHz MB90F474H 3 12 MHz MB90F474L fCP Internal operating clock frequency fCPL Internal operating clock cycle time Pin name tCP tCPL *2 50.0 666 ns *2 62.5 666 ns MB90474 only 122.1 µs *1 : VCC = VCC3 = VCC5 *2 : Observe the operating voltage with care. 87 MB90470 Series • X0, X1 clock timing tC 0.8 VCC X0 0.2 VCC PWH PWL tcf tcr • X0A, X1A clock timing tCL 0.8 VCC X0A 0.2 VCC PWLH PWLL tcf 88 tcr MB90470 Series • PLL warranted operating range Internal operating clock frequency vs. Supply voltage High speed flash model operating range Supply voltage VCC (V) 3.6 PLL warranted operating range 3.13 3.0 2.5 2.4 1.8 Low voltage flash model operating range Normal operating range 1.5 3 5 12 10 Internal clock fCP (MHz) 16 20 Note : Use it at f = 16 MHz for MB90474. When using the high speed flash model at f = 20 MHz, use supply voltages of 3.13 V to 3.6 V. For A/D operating frequencies, see the electrical characteristics of the A/D converter module. Maximum assured operation frequency (fcp) of µDMA is 16 MHz. Base oscillator frequency vs. Internal operating clock frequency Internal clock fCP (MHz) 20 16 12 9 8 4 34 8 10 16 20 24 Base oscillator clock FC (MHz) 32 40 Note : Use PLL circuit when using internal clock at 16 MHz or more. It is recommended to use base oscillator clock of up to 20 MHz. AC characteristics are determined using the following measurement reference voltage values. • Input signal waveform • Output signal waveform Hysteresis input pins Output pins 0.8 VCC 2.4 V 0.2 VCC 0.8 V Pins other than hysteresis input/MD input pins 0.7 VCC 0.3 VCC 89 MB90470 Series (2) Clock Output Timing Parameter Cycle time CLK ↑→ to CLK ↓ (VSS = 0.0 V, TA = −40 °C to +85 °C) SymPin name bol tCYC tCHCL Conditions CLK CLK Value Min Max tCP ns ns at fcp = 20 MHz VCC = 2.7 V to 3.3 V tCP / 2 − 20 tCP / 2 + 20 ns at fcp = 16 MHz VCC = 2.7 V to 3.3 V tCP / 2 − 64 tCP / 2 + 64 ns at fcp = 5 MHz tCYC tCHCL 2.4 V 90 Remarks VCC = 3.0 V to 3.6 V tCP / 2 − 15 tCP / 2 + 15 Notes : • tCP : See (1) Clock Timing Ratings. • VCC = VCC3 = VCC5 CLK Unit 2.4 V 0.8 V MB90470 Series (3) Reset Input Ratings Parameter Reset input time (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tRSTL Value Pin name Conditions RST Unit Remarks Min Max 16 tCP ns In normal operation Oscillator oscillation time* + 16 tCP ms In stop mode * : Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several dozen ms; for a FAR/ceramic oscillator, this is several hundred µs to a few ms, and for an external clock this is 0 ms. Note: tCP : See (1) Clock Timing Ratings. • In stop mode tRSTL RST 0.2 Vcc X0 Internal operation clock 0.2 Vcc 90 % of amplitude Oscillator oscillation time 16 tcp Oscillator stabilization wait time Execution of the instruction Internal reset • Measurement conditions for AC ratings CL : Load capacitance applied to pin during testing Pin CL CLK, ALE, CL = 30 pF AD15 to AD00 (Address, data bus) , RD, WR, A23 to A00/D15 to D00 : CL = 80 pF 91 MB90470 Series (4) Power On Ratings (Power-on reset) Parameter Symbol Pin name tR VCC tOFF VCC Power rise time Power cutoff time (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Conditions Value Unit Remarks Min Max 30 ms * 1 ms For continuous operation * : Power supply rise time requires VCC < 0.2 V. Notes : • VCC = VCC3 = VCC5 • The above ratings are values for power-on reset. • A power-on reset should be applied by restarting the power supply inside the device. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Extreme variations in supply voltage may activate a power-on reset. As the illustration shows below , when varying supply voltage during operation the use of a smooth voltage rise with suppressed fluctuation is recommended. Main supply voltage VCC Sub supply voltage VSS 92 Hold RAM data A rise slope of 50 mV or less is recommended MB90470 Series (5) Bus read timing Parameter ALE pulse width (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tLHLL Pin name ALE Conditions Value Unit Remarks ns at fcp = 20 MHz tCP / 2 − 20 ns at fcp = 16 MHz tCP / 2 − 35 ns at fcp = 8 MHz tCP / 2 − 20 ns tCP / 2 − 40 ns Min Max tCP / 2 − 15 Valid address → ALE ↓ time tAVLL Address pins, ALE ALE ↓ → address valid time tLLAX ALE, Address pins tCP / 2 − 15 ns Valid address → RD ↓ time tAVRL RD, address tCP − 20 ns Valid address → valid data input tAVDV Address/data 5 tCP / 2 − 60 ns 5 tCP / 2 − 80 ns at fcp = 8 MHz RD pulse width tRLRH RD 3 tCP / 2 − 25 ns at fcp = 20 MHz 3 tCP / 2 − 20 ns at fcp = 16 MHz RD ↓ → valid data input tRLDV RD, Data 3 tCP / 2 − 60 ns 3 tCP / 2 − 80 ns RD ↑ → data hold time tRHDX RD, Data 0 ns RD ↑ → ALE ↑ time tRHLH RD, ALE tCP / 2 − 15 ns RD ↑ → address valid time tRHAX Address, RD tCP / 2 − 10 ns Valid address → CLK ↑ time tAVCH Address, CLK tCP / 2 − 20 ns RD ↓ → CLK ↑ time tRLCH RD, CLK tCP / 2 − 20 ns ALE ↓ → RD ↓ time tLLRL RD, ALE tCP / 2 − 15 ns at fcp = 8 MHz at fcp = 8 MHz Notes : • tCP : See (1) Clock Timing Ratings. • VCC = VCC3 = VCC5 93 MB90470 Series tAVCH tRLCH 2.4 V 2.4 V CLK tRHLH ALE 2.4 V 2.4 V tLHLL 2.4 V 0.8 V tRLRH 2.4 V RD tAVLL tLLAX 0.8 V tLLRL Multiplex mode tAVRL A23 to A16 tRLDV 2.4 V 2.4 V 0.8 V 0.8 V tAVDV AD15 to AD00 tRHAX 2.4 V 2.4 V tRHDX 0.7 VCC Address 0.8 V 0.7 VCC Read data 0.8 V 0.3 VCC 0.3 VCC tRHAX Non-multiplex mode A23 to A00 2.4 V 2.4 V 0.8 V 0.8 V tRLDV tRHDX tAVDV D15 to D00 94 0.7 VCC 0.7 VCC Read data 0.3 VCC 0.3 VCC MB90470 Series (6) Bus Write Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Value Parameter Symbol Pin name Conditions Min Max Valid address → WR ↓ time tAVWL Address pins, WR tCP − 20 ns WR pulse width tWLWH WRL, WRH 3 tCP / 2 − 25 ns at fcp = 20 MHz 3 tCP / 2 − 20 ns at fcp = 16 MHz Valid data output → WR ↑ time tDVWH Data pins, WR 3 tCP / 2 − 20 ns 15 ns at fcp = 20 MHz tWHDX WR, Data pins 20 ns at fcp = 16 MHz 30 ns at fcp = 8 MHz WR, Address pins tCP / 2 − 10 ns WR ↑ → data hold time WR ↑ → address valid time tWHAX Unit WR ↑ → ALE ↑ time tWHLH WR , ALE tCP / 2 − 15 ns WR ↓ → CLK ↑ time tWLCH WR , CLK tCP / 2 − 20 ns Remarks Notes : • tCP : See (1) Clock Timing Ratings. • VCC = VCC3 = VCC5 95 MB90470 Series tWLCH 2.4 V CLK tWHLH 2.4 V ALE tWLWH 2.4 V WR (WRL, WRH) 0.8 V Multiplex mode tAVWL A23 to A16 tWHAX 2.4 V 2.4 V 0.8 V 0.8 V tDVWH AD15 to AD00 2.4 V 2.4 V 2.4 V Address Write data 0.8 V 0.8 V 0.8 V tWHAX Non-multiplex mode A23 to A00 2.4 V 2.4 V 0.8 V 0.8 V tDVWH D15 to D00 96 tWHDX 2.4 V 2.4 V 0.8 V tWHDX Write data 0.8 V MB90470 Series (7) Ready Input Timing Parameter (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol RDY setup time tRYHS RDY hold time tRYHH Pin name RDY Value Conditions Min Max 45 ns 70 ns 0 ns Unit Remarks fcp = 8 MHz Notes : • If the RDY setup time is not sufficient, use the auto ready function. • VCC = VCC3 = VCC5 • If input from the RDY pin, note that the AC ratings must be satisfied so that the chip will not drive recklessly. 2.4 V 2.4 V CLK ALE RD/WR tRYHS tRYHH RDY wait not applied RDY wait applied (1 cycle) 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tRYHS 97 MB90470 Series (8) Hold Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Pin floating → HAK ↓ time tXHAL HAK HAK ↓ → valid data time tHAHV HAK Value Conditions Max 30 tCP ns tCP 2 tCP ns Notes : • tCP : See (1) Clock Timing Ratings. • VCC = VCC3 = VCC5 • If the HRQ pin is read, at least one cycle is required before the HAK pin changes. HAK 2.4 V 0.8 V tXHAL 2.4 V All pins 98 0.8 V tHAHV High-Z Unit Min 2.4 V 0.8 V Remarks MB90470 Series (9) UART Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOV Valid SIN → SCK ↑ tIVSH SCK ↑ → valid SIN hold time tSHIX Serial clock “H” pulse width Parameter Conditions Value Unit Min Max 8 tCP ns − 80 + 80 ns − 120 + 120 ns 100 ns 200 ns tCP ns tSHSL 4 tCP ns Serial clock “L” pulse width tSLSH 4 tCP ns SCK ↓ → SOT delay time tSLOV 150 ns 200 ns Valid SIN → SCK ↑ tIVSH 60 ns 120 ns SCK ↑ → valid SIN hold time tSHIX 60 ns 120 ns Internal shift clock mode output pin CL = 80 pF + 1 TTL External shift clock mode output pin CL = 80 pF + 1 TTL Remarks fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz Notes : • These AC characteristics are for operation in CLK synchronous mode. • CL is the load capacitance applied to pins during testing. • tCP : See (1) Clock Timing Ratings. • VCC = VCC3 = VCC5 99 MB90470 Series • Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External Shift Clock Mode tSLSH tSHSL SCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN 100 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB90470 Series (10) I/O Expanded Serial Interface Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOV Valid SIN → SCK ↑ tIVSH SCK ↑ → valid SIN hold time tSHIX Serial clock “H” pulse width Parameter Conditions Value Unit Min Max 8 tCP ns − 80 + 80 ns − 120 + 160 ns 100 ns 200 ns tCP ns tSHSL 4 tCP ns Serial clock “L” pulse width tSLSH 4 tCP ns SCK ↓ → SOT delay time tSLOV 150 ns 200 ns Valid SIN → SCK ↑ tIVSH 60 ns 120 ns SCK ↑ → valid SIN hold time tSHIX 60 ns 120 ns Internal shift clock mode output pin CL = 80 pF + 1 TTL External shift clock mode output pin CL = 80 pF + 1 TTL Remarks fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz Notes : • These AC ratings are for operation in CLK synchronous mode. • CL is the load capacitance applied to pins during testing. • tCP : See (1) Clock Timing Ratings. • Values shown are target values. • VCC = VCC3 = VCC5 101 MB90470 Series • Internal shift clock mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH tSHSL SCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN 102 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB90470 Series (11) I2C Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name SCL clock frequency fSCL Bus free time between stop and start Parameter Value Conditions Unit Min Max 0 100 kHz tBUS 4.7 µs tHDSTA 4.0 µs SCL clock “L” status hold time tLOW 4.7 µs SCL clock “H” status hold time tHIGH 4.0 µs Resend start condition setup time tSUSTA 4.7 µs Data hold time tHDDAT 0 µs Data setup time tSUDAT 40 ns SDA and SCL signal rise time tR 1000 ns SDA and SCL signal fall time tF 300 ns tSUSTO 4.0 µs Hold time (resend) start Stop condition setup time Remarks First clock pulse is generated after this interval. Note : VCC = VCC3 = VCC5 0.8 VCC SDA 0.2 VCC tBUS tLOW tR tHIGH tF tHDSTA 0.8 VCC SCL 0.2 VCC tHDSTA tHDDAT tSUDAT tSUSTA tSUSTO fSCL 103 MB90470 Series (12) Timer Input Timing Parameter (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Conditions Min Max tTIWH tTIWL TIN0, IN0, IN1, PWC0 to PWC3 4 tCP Input pulse width Unit Remarks ns Notes : • tCP : See (1) Clock Timing Ratings. • VCC = VCC3 = VCC5 0.8 VCC TIN0, PWC0 to PWC3, IN0, IN1 0.8 VCC 0.2 VCC tTIWH (13) Timer Output Timing Parameter CLK ↑ → Tout change time PPG0 to PPG5 change time OUT0 to OUT5 change time TOUT, PPG0 to PPG5, OUT0 to OUT5 Value Symbol Pin name Conditions Min Max tTO TOT0, PPG0 to PPG5, OUT0 to OUT5 80 pF load 30 0.7 VCC 0.7 VCC 0.3 VCC tTO 104 tTIWL (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Note : VCC = Vcc3 = VCC5 CLK 0.2 VCC Unit ns Remarks MB90470 Series (14) Trigger Input Timing Parameter Input pulse width (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name tTRGH tTRGL ADTG, IRQ0 to IRQ7 Conditions Value Unit Remarks Min Max 5 tCP ns In normal operation 1 µs Stop mode Notes : • tCP : See (1) Clock Timing Ratings. • VCC = VCC3 = VCC5 0.8 VCC IRQ0 to IRQ7, ADTG 0.8 VCC 0.2 VCC tTRGH (15) Up/down Counter Timing Parameter 0.2 VCC tTRGL (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Conditions Value Min Max Unit AIN input “H” pulse width tAHL 8 tCP ns AIN input “L” pulse width tALL 8 tCP ns BIN input “H” pulse width tBHL 8 tCP ns BIN input “L” pulse width tBLL 8 tCP ns AIN ↑ → BIN ↑ time tAUBU 4 tCP ns BIN ↑ → AIN ↓ time tBUAD 4 tCP ns AIN ↓ → BIN ↑ time tADBD 4 tCP ns BIN ↓ → AIN ↑ time tBDAU 4 tCP ns BIN ↑ → AIN ↑ time tBUAU 4 tCP ns AIN ↑ → BIN ↓ time tAUBD 4 tCP ns BIN ↓ → AIN ↑ time tBDAD 4 tCP ns AIN ↓ → BIN ↑ time tADBU 4 tCP ns ZIN input “H” pulse width tZHL 4 tCP ns ZIN input “L” pulse width tZLL 4 tCP ns AIN0, AIN1, BIN0, BIN1 80 pF load ZIN0, ZIN1 Remarks Notes : • tCP : See (1) Clock Timing Ratings. • VCC = VCC3 = VCC5 105 MB90470 Series tAHL 0.8 VCC tALL 0.8 VCC AIN 0.2 VCC tAUBU tBUAD tADBD 0.8 VCC 0.2 VCC tBDAU 0.8 VCC BIN 0.2 VCC tBHL 0.8 VCC 0.2 VCC tBLL 0.8 VCC BIN 0.2 VCC tBUAU tAUBD tBDAD 0.2 VCC tADBU 0.8 VCC AIN 0.2 VCC 0.8 VCC ZIN 0.8 VCC tZHL tZLL 0.2 VCC 106 0.2 VCC MB90470 Series (16) Chip Select Output Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Conditions Min Max Chip select output valid time → RD ↓ tSVRL CS0 to CS3, RD tCP / 2 − 10 ns Chip select output valid time → WR ↓ tSVWL CS0 to CS3, WRH, WRL tCP / 2 − 10 ns RD ↑ → chip select output valid time tRHSV RD, CS0 to CS3 tCP / 2 − 20 ns WR ↑ → chip select output valid time tWHSV WRH, WRL, CS0 to CS3 tCP / 2 − 20 ns Parameter Unit Remarks Notes : • tCP : See (1) Clock Timing Ratings. • VCC = VCC3 = VCC5 tSVRL 2.4 V RD 0.8 V tRHSV A23 to A16, CS0 to CS3 2.4 V 0.8 V 2.4 V D15 to D00 Read data 0.8 V tSVWL tWHSV 2.4 V WRH, WRL 0.8 V D15 to D00 Undefined Write data Note : The chip select output signal changes at the same time due to the structure of the internal bus, leading to the possibility of a bus fight. AC warranty does not apply between ALE output signals and chip select output signals. 107 MB90470 Series 5. A/D Converter Electrical Characteristics (VCC = AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Resolution Total error Linear error Differential linear error Zero transition voltage Symbol Pin name Value Unit Remarks Min Typ Max 10 bit ±3.0 LSB ±4.0 LSB 1.8 V to 2.2 V ±2.5 LSB at VCC = AVCC = 2.2 V to 3.6 V ±3.0 LSB at VCC = AVCC = 1.8 V to 2.2 V ±1.9 LSB 2.2 V to 3.6 V ±2.4 LSB at VCC = AVCC = 1.8 V to 2.2 V at VCC = AVCC = 2.2 V to 3.6 V at VCC = AVCC = 2.2 V to 3.6 V at VCC = AVCC = at VCC = AVCC = AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV AVSS − 2.0 LSB AVSS + 0.5 LSB AVSS + 3.0 LSB mV 1.8 V to 2.2 V VOT AN0 to AN7 at VCC = AVCC = AVRH − 3.5 LSB AVRH − 1.5 LSB AVRH + 0.5 LSB mV at VCC = AVCC = 2.2 V to 3.6 V AVRH − 4.0 LSB AVRH − 1.5 LSB AVRH + 1.0 LSB mV at VCC = AVCC = 1.8 V to 2.2 V at AVRH ≥ 2.7 V Full scale transition voltage VFST AN0 to AN7 Conversion time 5.8125*1 µs Analog port input current IAIN AN0 to AN7 0.1 10 µA Analog input voltage VAIN AN0 to AN7 AVSS AVRH V AVSS + 2.2 AVCC V at VCC = AVCC = 2.2 V to 3.6 V AVSS + 1.8 AVCC V at VCC = AVCC = 1.8 V to 2.2 V AVCC 1.2 4.4 mA IAH AVCC 5* 2 µA IR AVRH 95 170 Reference voltage Supply current IA AVRH Reference voltage supply current IRH AVRH 5* Inter-channel variation AN0 to AN7 4 2 µA µA LSB *1 : At machine clock frequency 16 MHz. *2 : Current with A/D converter not operating, and CPU in stop mode (VCC = AVCC = AVRH = 3.0 V) 108 MB90470 Series Notes : • VCC = VCC3 = VCC5 • The relative error increases as |AVRH − AVSS| is reduced. • Observe the following conditions in applying output impedance on the external circuits of the analog input. Output impedance on the external circuit is recommended to be 6 kΩ or less. If external capacitance is used, it is recommended that this be several thousand times the level of internal capacitors in view of the effects of voltage division between the external capacitor and the interior of the chip. • If the output impedance of the external circuits is too high, the analog voltage sampling time may be insufficient. (sampling time = 3.00 µs at machine clock frequency 20 MHz) . < Reference Data > • Analog Input Circuit • Model analog input circuit Sample and hold circuit Analog input C0 Comparator RON1 RON2 RON3 RON4 C1 RON1 : approx. 5 kΩ RON2 : approx. 617 Ω RON3 : approx. 617 Ω RON4 : approx. 473 Ω C0 : approx. 35 pF C1 : approx. 2 pF Note : Values shown here are intended as guidelines. • A/D Operating Frequency Restrictions µs] Supply voltage A/D conversion time [µ Machine clock frequency 3.6 V ≥ AVCC ≥ 3.0 V 4.650 20 MHz 3.6 V ≥ AVCC ≥ 2.7 V 5.813 16 MHz 2.7 V > AVCC ≥ 2.6 V 6.643 14 MHz 2.6 V > AVCC ≥ 2.5 V 7.750 12 MHz 2.5 V > AVCC ≥ 2.4 V 8.455 11 MHz 2.4 V > AVCC ≥ 2.3 V 9.300 10 MHz 2.3 V > AVCC ≥ 2.2 V 11.63 8 MHz 2.2 V > AVCC ≥ 2.1 V 15.50 6 MHz 2.1 V > AVCC ≥ 2.0 V 23.25 4 MHz 2.0 V > AVCC ≥ 1.9 V 46.50 2 MHz 1.9 V > AVCC ≥ 1.8 V 93.00 1 MHz 109 MB90470 Series • Use of the X0/X1, X0A/X1A Pins In normal use (VCC = 2 V or higher) Pull-up resistance 1, 2 Damping resistance 1, 2 C1 to C4 Pull-up For all pins, consult regarding X1A resistance 2 manufacturer of oscillator. (Sample operation using VCC = 2 V, Damping f = 5 MHz or less) resistance 2 Pull-up resistance 1 = 5.1 kΩ Pull-up resistance 2 = 510 kΩ Damping resistance 1 = 0 Ω C4 Damping resistance 2 = 39 kΩ C1 = C2 = 22 pF C3 = C4 = 30 pF Use with a crystal oscillator Pull-up resistance 1 X1 X0 X0A Damping resistance 1 C2 C1 C3 • Sample use of external clock input X0 OPEN MB90470 series X1 6. Flash Memory Program/Erase Characteristics Parameter Conditions Sector erase time Chip erase time Word (16-bit) programming time 110 TA = + 25 °C VCC = 3.3 V Value Unit Remarks 15 s Excludes 00H programming prior erasure 7 s Excludes 00H programming prior erasure 16 3600 µs Excludes system-level overhead Min Typ Max 1 Erase/Program cycle 1000 cycle Data hold time 100000 h MB90470 Series ■ SAMPLE CHARACTERISTICS (1) “H” level output voltage (2) “L” level output voltage (VCC − VOH) − IOH 1.0 1.0 TA = +25 °C 0.8 0.8 0.7 0.7 0.6 0.5 VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V VCC = 3.9 V 0.4 0.3 0.2 0.1 0.0 −1 TA = +25 °C 0.9 VOL (V) VOH (V) 0.9 VOL − IOL −2 −3 IOH (mA) −4 0.6 0.5 0.4 0.3 0.2 0.1 0.0 −5 (3) “H” level input voltage/ “L” level input voltage (CMOS input) VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V VCC = 3.9 V 1 2 3 IOL (mA) 5 (4) “H” level input voltage/ “L” level input voltage (hysteresis input) VIN − VCC 2.5 4 VIN − VCC 2.5 TA = +25 °C TA = +25 °C 2.0 2.0 VIH VIL 1.5 VIN (V) VIN (V) VIH 1.5 VIL 1.0 1.0 0.5 0.5 0.0 2.7 3.0 3.3 VCC (V) 3.6 3.9 0.0 2.7 3.0 3.3 VCC (V) 3.6 3.9 111 MB90470 Series (5) Supply Current (fcp = internal stroke frequency) • MASK versions ICC − VCC ICCS − VCC 35 TA = +25 °C 80 70 ICC (mA) 60 fcp = 20 MHz 30 fcp = 16 MHz 25 50 fcp = 12.5 MHz 40 fcp = 10 MHz 30 fcp = 4 MHz fcp = 2 MHz fcp = 1 MHz 20 10 0 2.4 2.7 3.0 3.3 3.6 ICCS (mA) 90 fcp = 16 MHz fcp = 12.5 MHz 20 fcp = 10 MHz 15 10 fcp = 4 MHz fcp = 2 MHz fcp = 1 MHz 5 0 3.9 2.4 2.7 3.0 VCC (V) 1.8 35 1.6 ICCL (µA) ICCH (µA) 1.2 1.0 0.8 0.6 2.7 3.0 3.3 VCC (V) 3.6 3.9 ICCT − VCC TA = +25 °C 4.0 ICCT (µA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 112 25 20 15 5 0.2 0.0 2.4 TA = +25 °C 10 0.4 4.5 3.9 30 1.4 5.0 3.6 ICCL − VCC 40 TA = +25 °C 0.0 2.4 3.3 VCC (V) ICCH − VCC 2.0 fcp = 20 MHz TA = +25 °C 2.7 3.0 3.3 VCC (V) 3.6 3.9 0 2.4 2.7 3.0 3.3 VCC (V) 3.6 3.9 MB90470 Series • FLASH versions ICC − VCC 70 ICCS − VCC 25 TA = +25 °C fcp = 20 MHz 60 fcp = 10 MHz 30 fcp = 16 MHz ICCS (mA) ICC (mA) 40 fcp = 20 MHz 20 fcp = 16 MHz 50 TA = +25 °C 15 fcp = 10 MHz 10 20 fcp = 4 MHz fcp = 2 MHz 10 0 2.4 2.7 3.0 3.3 VCC (V) 3.6 fcp = 4 MHz fcp = 2 MHz 5 0 2.4 3.9 2.7 ICCH − VCC 1.0 30 3.9 TA = +25 °C 25 0.8 0.7 20 ICCHL (µA) ICCH (µA) 3.6 ICCL − VCC TA = +25 °C 0.9 3.0 3.3 VCC (V) 0.6 0.5 0.4 15 10 0.3 0.2 5 0.1 0.0 2.4 2.7 3.0 3.3 VCC (V) 3.6 3.9 0 2.4 2.7 3.0 3.3 VCC (V) 3.6 3.9 ICCT − VCC 5.0 4.5 TA = +25 °C 4.0 ICCT (µA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) (Continued) 113 MB90470 Series (Continued) IA − AVCC 3.0 IR − AVCC 100 TA = +25 °C 90 2.5 80 70 IR (mA) 2.0 IA (mA) TA = +25 °C 1.5 1.0 60 50 40 30 20 0.5 10 0.0 2.4 2.7 3.0 3.3 3.6 3.9 R − VCC R (kΩ) TA = +25 °C 100 10 2.4 2.7 3.0 VCC (V) 114 3.3 2.7 3.0 3.3 AVCC (V) AVCC (V) 1000 0 2.4 3.6 3.9 3.6 3.9 MB90470 Series ■ ORDERING INFORMATION Part number Package MB90473PF MB90474PF MB90477PF MB90478PF MB90F474LPF MB90F474HPF 100-pin plastic QFP (FPT-100P-M06) MB90473PFV MB90474PFV MB90477PFV MB90478PFV MB90F474LPFV MB90F474HPFV 100-pin plastic LQFP (FPT-100P-M05) Remarks 115 MB90470 Series ■ PACKAGE DIMENSIONS Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 100-pin plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 1 30 0.65(.026) "A" C 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 31 0.32±0.05 (.013±.002) 0.13(.005) M 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) MB90470 Series (Continued) 100-pin plastic LQFP (FPT-100P-M05) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ *14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 100 26 1 25 C 0.20±0.05 (.008±.002) 0.08(.003) M 0.10±0.10 (.004±.004) (Stand off) 0˚~8˚ "A" 0.50(.020) +.008 1.50 –0.10 .059 –.004 (Mounting height) INDEX 0.145±0.055 (.0057±.0022) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) 2003 FUJITSU LIMITED F100007S-c-4-6 Dimensions in mm (inches) Note : The values in parentheses are reference values. 117 MB90470 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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