HITACHI HD6433030TF

OMC942723169
Hitachi Microcomputer
H8/3032 Series
Hardware Manual
Preface
The H8/3032 Series is a series of high-performance single-chip microcontrollers that integrate
system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.*
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities.
The three operating modes offer a choice of expanded mode and single-chip mode, enabling the
H8/3032 Series to adapt quickly and flexibly to a variety of conditions.
This manual describes the H8/3032 Series hardware. For details of the instruction set, refer to the
H8/300H Programming Manual.
Note: * The H8/3032 Series has a maximum address space of 1 Mbyte.
Contents
Section 1
1.1
1.2
1.3
1.4
Overview ..................................................................................................... 1
Overview ........................................................................................................................ 1
Block Diagram................................................................................................................ 5
Pin Description ............................................................................................................... 6
1.3.1
Pin Arrangement............................................................................................. 6
1.3.2
Pin Functions .................................................................................................. 7
Pin Functions .................................................................................................................. 10
Section 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
CPU ...............................................................................................................
Overview ........................................................................................................................
2.1.1
Features...........................................................................................................
2.1.2
Differences from H8/300 CPU .......................................................................
CPU Operating Modes....................................................................................................
Address Space.................................................................................................................
Register Configuration....................................................................................................
2.4.1
Overview.........................................................................................................
2.4.2
General Registers............................................................................................
2.4.3
Control Registers ............................................................................................
2.4.4
Initial CPU Register Values ............................................................................
Data Formats...................................................................................................................
2.5.1
General Register Data Formats.......................................................................
2.5.2
Memory Data Formats....................................................................................
Instruction Set.................................................................................................................
2.6.1
Instruction Set Overview ................................................................................
2.6.2
Instructions and Addressing Modes................................................................
2.6.3
Tables of Instructions Classified by Function ................................................
2.6.4
Basic Instruction Formats ...............................................................................
2.6.5
Notes on Use of Bit Manipulation Instructions ..............................................
Addressing Modes and Effective Address Calculation ..................................................
2.7.1
Addressing Modes ..........................................................................................
2.7.2
Effective Address Calculation ........................................................................
Processing States ............................................................................................................
2.8.1
Overview.........................................................................................................
2.8.2
Program Execution State ................................................................................
2.8.3
Exception-Handling State...............................................................................
2.8.4
Exception-Handling Sequences ......................................................................
2.8.5
Reset State ......................................................................................................
2.8.6
Power-Down State ..........................................................................................
15
15
15
16
17
18
19
19
20
21
22
23
23
24
26
26
27
28
38
39
39
39
42
46
46
47
47
49
50
50
2.9
Basic Operational Timing...............................................................................................
2.9.1
Overview.........................................................................................................
2.9.2
On-Chip Memory Access Timing...................................................................
2.9.3
On-Chip Supporting Module Access Timing .................................................
2.9.4
Access to External Address Space..................................................................
Section 3
3.1
3.2
3.3
3.4
3.5
3.6
MCU Operating Modes ........................................................................... 55
Overview ........................................................................................................................
3.1.1
Operating Mode Selection ..............................................................................
3.1.2
Register Configuration....................................................................................
Mode Control Register (MDCR) ....................................................................................
System Control Register (SYSCR).................................................................................
Operating Mode Descriptions.........................................................................................
3.4.1
Mode 1 ............................................................................................................
3.4.2
Mode 2 ............................................................................................................
3.4.3
Mode 3 ............................................................................................................
Pin Functions in Each Operating Mode..........................................................................
Memory Map in Each Operating Mode..........................................................................
Section 4
4.1
4.2
4.3
4.4
4.5
4.6
Exception Handling ..................................................................................
Overview ........................................................................................................................
4.1.1
Exception Handling Types and Priority..........................................................
4.1.2
Exception Handling Operation .......................................................................
4.1.3
Exception Vector Table...................................................................................
Reset
........................................................................................................................
4.2.1
Overview.........................................................................................................
4.2.2
Reset Sequence ...............................................................................................
4.2.3
Interrupts after Reset.......................................................................................
Interrupts ........................................................................................................................
Trap Instruction...............................................................................................................
Stack Status after Exception Handling ...........................................................................
Notes on Stack Usage .....................................................................................................
Section 5
5.1
5.2
51
51
51
53
54
Interrupt Controller...................................................................................
Overview ........................................................................................................................
5.1.1
Features...........................................................................................................
5.1.2
Block Diagram................................................................................................
5.1.3
Pin Configuration............................................................................................
5.1.4
Register Configuration....................................................................................
Register Descriptions......................................................................................................
5.2.1
System Control Register (SYSCR).................................................................
55
55
56
57
58
60
60
60
60
61
61
65
65
65
65
66
67
67
67
69
70
71
72
73
75
75
75
76
77
77
78
78
5.3
5.4
5.5
5.2.2
Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 79
5.2.3
IRQ Status Register (ISR) .............................................................................. 85
5.2.4
IRQ Enable Register (IER)............................................................................. 86
5.2.5
IRQ Sense Control Register (ISCR) ............................................................... 87
Interrupt Sources............................................................................................................. 88
5.3.1
External Interrupts .......................................................................................... 88
5.3.2
Internal Interrupts ........................................................................................... 89
5.3.3
Interrupt Vector Table ..................................................................................... 89
Interrupt Operation ......................................................................................................... 92
5.4.1
Interrupt Handling Process ............................................................................. 92
5.4.2
Interrupt Sequence .......................................................................................... 97
5.4.3
Interrupt Response Time................................................................................. 98
Usage Notes .................................................................................................................... 99
5.5.1
Contention between Interrupt and Interrupt-Disabling Instruction ................ 99
5.5.2
Instructions that Inhibit Interrupts .................................................................. 100
5.5.3
Interrupts during EEPMOV Instruction Execution ........................................ 100
Section 6
6.1
6.2
6.3
6.4
Bus Controller ............................................................................................ 101
Overview ........................................................................................................................ 101
6.1.1
Features........................................................................................................... 101
6.1.2
Block Diagram................................................................................................ 102
6.1.3
Input/Output Pins............................................................................................ 103
6.1.4
Register Configuration.................................................................................... 103
Register Descriptions...................................................................................................... 104
6.2.1
Access State Control Register (ASTCR)........................................................ 104
6.2.2
Wait Control Register (WCR)......................................................................... 105
6.2.3
Wait State Controller Enable Register (WCER)............................................. 106
Operation ........................................................................................................................ 107
6.3.1
Area Division.................................................................................................. 107
6.3.2
Bus Control Signal Timing ............................................................................. 109
6.3.3
Wait Modes ..................................................................................................... 111
6.3.4
Interconnections with Memory (Example)..................................................... 117
Usage Notes .................................................................................................................... 118
6.4.1
Register Write Timing .................................................................................... 118
Section 7
7.1
7.2
I/O Ports ....................................................................................................... 119
Overview ........................................................................................................................ 119
Port 1
........................................................................................................................ 122
7.2.1
Overview......................................................................................................... 122
7.2.2
Register Descriptions...................................................................................... 123
7.2.3
Pin Functions in Each Mode........................................................................... 124
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
Port 2
7.3.1
7.3.2
7.3.3
7.3.4
Port 3
7.4.1
7.4.2
7.4.3
Port 5
7.5.1
7.5.2
7.5.3
7.5.4
Port 6
7.6.1
7.6.2
7.6.3
Port 7
7.7.1
7.7.2
Port 8
7.8.1
7.8.2
7.8.3
Port 9
7.9.1
7.9.2
7.9.3
Port A
7.10.1
7.10.2
7.10.3
Port B
7.11.1
7.11.2
7.11.3
........................................................................................................................ 126
Overview......................................................................................................... 126
Register Descriptions...................................................................................... 127
Pin Functions in Each Mode........................................................................... 128
Input Pull-Up Transistors................................................................................ 130
........................................................................................................................ 131
Overview......................................................................................................... 131
Register Descriptions...................................................................................... 131
Pin Functions in Each Mode........................................................................... 133
........................................................................................................................ 134
Overview......................................................................................................... 134
Register Descriptions...................................................................................... 134
Pin Functions in Each Mode........................................................................... 137
Input Pull-Up Transistors................................................................................ 138
........................................................................................................................ 139
Overview......................................................................................................... 139
Register Descriptions...................................................................................... 139
Pin Functions in Each Mode........................................................................... 141
........................................................................................................................ 144
Overview......................................................................................................... 144
Register Description ....................................................................................... 145
........................................................................................................................ 146
Overview......................................................................................................... 146
Register Descriptions...................................................................................... 147
Pin Functions .................................................................................................. 148
........................................................................................................................ 150
Overview......................................................................................................... 150
Register Descriptions...................................................................................... 150
Pin Functions .................................................................................................. 152
........................................................................................................................ 153
Overview......................................................................................................... 153
Register Descriptions...................................................................................... 154
Pin Functions ................................................................................................. 156
........................................................................................................................ 161
Overview......................................................................................................... 161
Register Descriptions...................................................................................... 161
Pin Functions .................................................................................................. 163
Section 8
8.1
8.2
8.3
8.4
8.5
8.6
16-Bit Integrated Timer Unit (ITU)..................................................... 169
Overview ........................................................................................................................ 169
8.1.1
Features........................................................................................................... 169
8.1.2
Block Diagrams .............................................................................................. 172
8.1.3
Input/Output Pins............................................................................................ 177
8.1.4
Register Configuration.................................................................................... 178
Register Descriptions...................................................................................................... 181
8.2.1
Timer Start Register (TSTR) .......................................................................... 181
8.2.2
Timer Synchro Register (TSNC) .................................................................... 182
8.2.3
Timer Mode Register (TMDR)....................................................................... 184
8.2.4
Timer Function Control Register (TFCR) ...................................................... 187
8.2.5
Timer Output Master Enable Register (TOER) .............................................. 189
8.2.6
Timer Output Control Register (TOCR)......................................................... 192
8.2.7
Timer Counters (TCNT) ................................................................................. 193
8.2.8
General Registers (GRA, GRB) ..................................................................... 194
8.2.9
Buffer Registers (BRA, BRB) ........................................................................ 195
8.2.10
Timer Control Registers (TCR) ...................................................................... 196
8.2.11
Timer I/O Control Register (TIOR)................................................................ 198
8.2.12
Timer Status Register (TSR)........................................................................... 200
8.2.13
Timer Interrupt Enable Register (TIER)......................................................... 203
CPU Interface ................................................................................................................. 205
8.3.1
16-Bit Accessible Registers............................................................................ 205
8.3.2
8-Bit Accessible Registers.............................................................................. 207
Operation ........................................................................................................................ 209
8.4.1
Overview......................................................................................................... 209
8.4.2
Basic Functions............................................................................................... 210
8.4.3
Synchronization .............................................................................................. 220
8.4.4
PWM Mode .................................................................................................... 222
8.4.5
Reset-Synchronized PWM Mode ................................................................... 226
8.4.6
Complementary PWM Mode.......................................................................... 229
8.4.7
Phase Counting Mode..................................................................................... 239
8.4.8
Buffering......................................................................................................... 241
8.4.9
ITU Output Timing......................................................................................... 248
Interrupts ........................................................................................................................ 250
8.5.1
Setting of Status Flags .................................................................................... 250
8.5.2
Clearing of Status Flags.................................................................................. 252
8.5.3
Interrupt Sources............................................................................................. 253
Usage Notes .................................................................................................................... 254
Section 9
9.1
9.2
9.3
9.4
Overview ........................................................................................................................ 269
9.1.1
Features........................................................................................................... 269
9.1.2
Block Diagram................................................................................................ 270
9.1.3
TPC Pins ......................................................................................................... 271
9.1.4
Registers ......................................................................................................... 272
Register Descriptions...................................................................................................... 273
9.2.1
Port A Data Direction Register (PADDR) ...................................................... 273
9.2.2
Port A Data Register (PADR) ......................................................................... 273
9.2.3
Port B Data Direction Register (PBDDR) ...................................................... 274
9.2.4
Port B Data Register (PBDR) ......................................................................... 274
9.2.5
Next Data Register A (NDRA)....................................................................... 275
9.2.6
Next Data Register B (NDRB) ....................................................................... 277
9.2.7
Next Data Enable Register A (NDERA) ........................................................ 279
9.2.8
Next Data Enable Register B (NDERB)......................................................... 280
9.2.9
TPC Output Control Register (TPCR)............................................................ 281
9.2.10
TPC Output Mode Register (TPMR).............................................................. 284
Operation ........................................................................................................................ 286
9.3.1
Overview......................................................................................................... 286
9.3.2
Output Timing................................................................................................. 287
9.3.3
Normal TPC Output........................................................................................ 288
9.3.4
Non-Overlapping TPC Output........................................................................ 290
9.3.5
TPC Output Triggering by Input Capture....................................................... 292
Usage Notes .................................................................................................................... 293
9.4.1
Operation of TPC Output Pins........................................................................ 293
9.4.2
Note on Non-Overlapping Output .................................................................. 293
Section 10
10.1
10.2
10.3
Programmable Timing Pattern Controller ......................................... 269
Watchdog Timer ........................................................................................ 295
Overview ........................................................................................................................ 295
10.1.1
Features........................................................................................................... 295
10.1.2
Block Diagram................................................................................................ 296
10.1.3
Pin Configuration............................................................................................ 296
10.1.4
Register Configuration.................................................................................... 297
Register Descriptions...................................................................................................... 298
10.2.1
Timer Counter (TCNT)................................................................................... 298
10.2.2
Timer Control/Status Register (TCSR)........................................................... 299
10.2.3
Reset Control/Status Register (RSTCSR) ...................................................... 301
10.2.4
Notes on Register Access ............................................................................... 303
Operation ........................................................................................................................ 305
10.3.1
Watchdog Timer Operation............................................................................. 305
10.3.2
Interval Timer Operation ................................................................................ 306
10.4
10.5
10.3.3
Timing of Setting of Overflow Flag (OVF).................................................... 307
10.3.4
Timing of Setting of Watchdog Timer Reset Bit (WRST) ............................. 308
Interrupts ........................................................................................................................ 309
Usage Notes .................................................................................................................... 309
Section 11
11.1
11.2
11.3
11.4
11.5
Serial Communication Interface ........................................................... 311
Overview ........................................................................................................................ 311
11.1.1
Features........................................................................................................... 311
11.1.2
Block Diagram................................................................................................ 313
11.1.3
Input/Output Pins............................................................................................ 314
11.1.4
Register Configuration.................................................................................... 314
Register Descriptions...................................................................................................... 315
11.2.1
Receive Shift Register (RSR) ......................................................................... 315
11.2.2
Receive Data Register (RDR)......................................................................... 315
11.2.3
Transmit Shift Register (TSR)........................................................................ 316
11.2.4
Transmit Data Register (TDR) ....................................................................... 316
11.2.5
Serial Mode Register (SMR) .......................................................................... 317
11.2.6
Serial Control Register (SCR) ........................................................................ 321
11.2.7
Serial Status Register (SSR) ........................................................................... 325
11.2.8
Bit Rate Register (BRR) ................................................................................. 329
Operation ........................................................................................................................ 338
11.3.1
Overview......................................................................................................... 338
11.3.2
Operation in Asynchronous Mode.................................................................. 340
11.3.3
Multiprocessor Communication ..................................................................... 349
11.3.4
Synchronous Operation .................................................................................. 356
SCI Interrupts.................................................................................................................. 365
Usage Notes .................................................................................................................... 366
Section 12
12.1
12.2
12.3
12.4
A/D Converter............................................................................................ 371
Overview ........................................................................................................................ 371
12.1.1
Features........................................................................................................... 371
12.1.2
Block Diagram................................................................................................ 372
12.1.3
Input Pins ........................................................................................................ 373
12.1.4
Register Configuration.................................................................................... 374
Register Descriptions...................................................................................................... 375
12.2.1
A/D Data Registers A to D (ADDRA to ADDRD)........................................ 375
12.2.2
A/D Control/Status Register (ADCSR) .......................................................... 376
12.2.3
A/D Control Register (ADCR) ....................................................................... 379
CPU Interface ................................................................................................................. 380
Operation ........................................................................................................................ 381
12.4.1
Single Mode (SCAN = 0) ............................................................................... 381
12.5
12.6
12.4.2
Scan Mode (SCAN = 1).................................................................................. 383
12.4.3
Input Sampling and A/D Conversion Time .................................................... 385
12.4.4
External Trigger Input Timing........................................................................ 386
Interrupts ........................................................................................................................ 387
Usage Notes .................................................................................................................... 387
Section 13
13.1
13.2
13.3
RAM ............................................................................................................. 389
Overview ........................................................................................................................ 389
13.1.1
Block Diagram................................................................................................ 389
13.1.2
Register Configuration.................................................................................... 390
System Control Register (SYSCR)................................................................................. 391
Operation ........................................................................................................................ 392
13.3.1
Mode 1 ............................................................................................................ 392
13.3.2
Modes 2 and 3................................................................................................. 392
Section 14
14.1
14.2
14.3
14.4
ROM ............................................................................................................. 393
Overview ........................................................................................................................ 393
14.1.1
Block Diagram................................................................................................ 393
PROM Mode................................................................................................................... 394
14.2.1
PROM Mode Setting ...................................................................................... 394
14.2.2
Socket Adapter and Memory Map.................................................................. 394
Programming .................................................................................................................. 397
14.3.1
Programming and Verification........................................................................ 397
14.3.2
Programming Precautions............................................................................... 402
Reliability of Programmed Data..................................................................................... 403
Section 15
15.1
15.2
15.3
15.4
Overview ........................................................................................................................ 405
15.1.1
Block Diagram................................................................................................ 405
Oscillator Circuit ............................................................................................................ 406
15.2.1
Connecting a Crystal Resonator ..................................................................... 406
15.2.2
External Clock Input....................................................................................... 408
Duty Adjustment Circuit................................................................................................. 410
Prescalers ........................................................................................................................ 410
Section 16
16.1
16.2
16.3
Clock Pulse Generator ............................................................................. 405
Power-Down State .................................................................................... 411
Overview ........................................................................................................................ 411
Register Configuration.................................................................................................... 412
16.2.1
System Control Register (SYSCR)................................................................. 412
Sleep Mode ..................................................................................................................... 414
16.3.1
Transition to Sleep Mode................................................................................ 414
16.4
16.5
16.3.2
Exit from Sleep Mode..................................................................................... 414
Software Standby Mode ................................................................................................. 415
16.4.1
Transition to Software Standby Mode ............................................................ 415
16.4.2
Exit from Software Standby Mode ................................................................. 415
16.4.3
Selection of Waiting Time for Exit from Software Standby Mode ................ 416
16.4.4
Sample Application of Software Standby Mode ............................................ 417
16.4.5
Note................................................................................................................. 417
Hardware Standby Mode ................................................................................................ 418
16.5.1
Transition to Hardware Standby Mode........................................................... 418
16.5.2
Exit from Hardware Standby Mode................................................................ 418
16.5.3
Timing for Hardware Standby Mode.............................................................. 418
Section 17
17.1
17.2
17.3
Electrical Characteristics ........................................................................ 419
Absolute Maximum Ratings ........................................................................................... 419
Electrical Characteristics ................................................................................................ 420
17.2.1
DC Characteristics .......................................................................................... 420
17.2.2
AC Characteristics .......................................................................................... 430
17.2.3
A/D Conversion Characteristics ..................................................................... 437
Operational Timing......................................................................................................... 438
17.3.1
Bus Timing ..................................................................................................... 438
17.3.2
Control Signal Timing .................................................................................... 442
17.3.3
Clock Timing .................................................................................................. 444
17.3.4
TPC and I/O Port Timing................................................................................ 444
17.3.5
ITU Timing ..................................................................................................... 445
17.3.6
SCI Input/Output Timing................................................................................ 446
Appendix A Instruction Set ............................................................................................ 447
A.1
A.2
A.3
Instruction List................................................................................................................ 447
Operating Code Maps ..................................................................................................... 462
Number of States Required for Execution...................................................................... 465
Appendix B Register Field ............................................................................................. 474
B.1
B.2
Register Addresses and Bit Names................................................................................. 474
Register Descriptions...................................................................................................... 482
Appendix C I/O Port Block Diagrams ........................................................................ 532
C.1
C.2
C.3
C.4
C.5
Port 1 Block Diagram .....................................................................................................
Port 2 Block Diagram .....................................................................................................
Port 3 Block Diagram .....................................................................................................
Port 5 Block Diagram .....................................................................................................
Port 6 Block Diagram .....................................................................................................
532
533
534
535
536
C.6
C.7
C.8
C.9
C.10
Port 7 Block Diagram .....................................................................................................
Port 8 Block Diagram .....................................................................................................
Port 9 Block Diagram .....................................................................................................
Port A Block Diagram ....................................................................................................
Port B Block Diagram ....................................................................................................
538
539
540
543
546
Appendix D Pin States ..................................................................................................... 550
D.1
D.2
Port States in Each Mode................................................................................................ 550
Pin States at Reset........................................................................................................... 552
Appendix E
Timing of Transition to and Recovery
from Hardware Standby Mode.............................................................. 555
Appendix F
Package Dimensions ................................................................................ 556
Section 1 Overview
1.1 Overview
The H8/3032 Series is a series of microcontrollers (MCUs) that integrate system supporting
functions together with an H8/300H CPU core having an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.*1 Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities.
The three members of the H8/3032 Series are the H8/3032, the H8/3031, and the H8/3030. The
H8/3032 has 64 kbytes of ROM and 2 kbytes of RAM. The H8/3031 has 32 kbytes of ROM and
1 kbyte of RAM. The H8/3030 has 16 kbytes of ROM and 512 bytes of RAM.
Three MCU operating modes offer a choice of data bus width and address space size. The modes
(modes 1 to 3) include a single-chip mode and expanded mode.
In addition to the masked-ROM versions of the H8/3032 Series, the H8/3032 has a ZTAT™*2
version with user-programmable on-chip PROM. This version enables users to respond quickly
and flexibly to changing application specifications, growing production volumes, and other
conditions.
Table 1-1 summarizes the features of the H8/3032 Series.
Notes: 1. The H8/3032 Series has a maximum address space of 1 Mbyte.
2. ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd.
1
Table 1-1 Features
Feature
Description
CPU
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also useable as sixteen 8-bit registers or eight 32-bit registers)
High-speed operation
• Maximum clock rate: 16 MHz
• Add/subtract: 125 ns
• Multiply/divide: 875 ns
Two CPU operating modes
• Normal mode (64-kbyte address space)
• Advanced mode (1-Mbyte address space)
Instruction features
•
•
•
•
•
Memory
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit positions
H8/3032
• ROM: 64 kbytes
• RAM: 2 kbytes
H8/3031
• ROM: 32 kbytes
• RAM: 1 kbyte
H8/3030
• ROM: 16 kbytes
• RAM: 512 bytes
Interrupt
controller
• Six external interrupt pins: NMI, IRQ0 to IRQ4
• 21 internal interrupts
• Three selectable interrupt priority levels
Bus controller
• Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
2
Table 1-1 Features (cont)
Feature
Description
16-bit integrated
timer unit (ITU)
• Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10
pulse inputs
• 16-bit timer counter (channels 0 to 4)
• Two multiplexed output compare/input capture pins (channels 0 to 4)
• Operation can be synchronized (channels 0 to 4)
• PWM mode available (channels 0 to 4)
• Phase counting mode available (channel 2)
• Buffering available (channels 3 and 4)
• Reset-synchronized PWM mode available (channels 3 and 4)
• Complementary PWM mode available (channels 3 and 4)
Programmable
timing pattern
controller (TPC)
• Maximum 16-bit pulse output, using ITU as time base
• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)
• Non-overlap mode available
Watchdog
timer (WDT),
1 channel
• Reset signal can be generated by overflow
• Reset signal can be output externally
• Usable as an interval timer
Serial
communication
interface (SCI),
2 channels
• Selection of asynchronous or synchronous mode
• Full duplex: can transmit and receive simultaneously
• On-chip baud-rate generator
A/D converter
•
•
•
•
•
I/O ports
• 55 input/output pins
• 8 input-only pins
Resolution: 10 bits
Eight channels, with selection of single or scan mode
Variable analog conversion voltage range
Sample-and-hold function
Can be externally triggered
3
Table 1-1 Features (cont)
Feature
Description
Operating modes Three MCU operating modes
Mode
Address
Space
Address
Pins
Bus
Width
Mode 1
1 Mbyte
A0 to A19
8 bits
Mode 2
64 kbytes
—
—
Mode 3
1 Mbyte
—
—
Power-down
state
• Sleep mode
• Software standby mode
• Hardware standby mode
Other features
• On-chip clock oscillator
Product lineup
Model
Package
ROM
HD6473032F
HD6473032TF
80-pin QFP (FP-80A)
80-pin TQFP (TFP-80C)
PROM
HD6433032F
HD6433032TF
80-pin QFP (FP-80A)
80-pin TQFP (TFP-80C)
Mask ROM
HD6433031F
HD6433031TF
80-pin QFP (FP-80A)
80-pin TQFP (TFP-80C)
Mask ROM
HD6433030F
HD6433030TF
80-pin QFP (FP-80A)
80-pin TQFP (TFP-80C)
Mask ROM
4
1.2 Block Diagram
VCC
VCC
VSS
VSS
VSS
P37/D7
P36/D6
P35/D5
P34/D4
P33/D3
P32/D2
P31/D1
P30/D0
Figure 1-1 shows an internal block diagram.
Port 3
Address bus
RAM
Watchdog
timer
(WDT)
16-bit
integrated
timer-pulse unit
(ITU)
Serial
communication
interface
(SCI) × 1 channel
Programmable
timing pattern
controller (TPC)
A/D converter
Port 7
P77/AN7
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
Port A
PB7/TP15/ADTRG
PB6/TP14
PB5/TP13/TOCXB4
PB4/TP12/TOCXA4
PB2/TP11/TIOCB4
PB2/TP10/TIOCA4
PB1/TP9/TIOCB3
PB0/TP8/TIOCA3
Port B
Port 5
Interrupt
controller
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
Port 9
PROM*
(or masked
ROM)
P53/A15
P52/A16
P51/A17
P50/A18
Port 2
Bus
controller
Clock osc.
Port 6
H8/300H CPU
PA7/TIOCB2
PA6/TIOCA2
PA5/TIOCB1
PA4/TIOCA1
PA3/TIOCB0/TKCKD
PA2/TIOCA0/TCLKC
PA1/TCLKB
PA0/TCLKA
Vref
AVCC
AVSS
P83/IRQ3
P82/IRQ2
P81/IRQ1
P80/IRQ0
Port 8
P65/WR
P64/RD
P63/AS
P60/WAIT
Data bus (lower)
Port 1
Data bus (upper)
MD1
MD0
EXTAL
XTAL
ø
STBY
RES
RESO
NMI
Note: PROM version is available only in the H8/3032 Series.
Figure 1-1 Block Diagram
5
P94/SCK/IRQ4
P92/RxD
P90/TxD
1.3 Pin Description
1.3.1 Pin Arrangement
VREF
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
65
64
63
62
61
AVCC
68
P77/AN7
P80/IRQ0
69
66
P81/IRQ1
70
67
P83/IRQ3
P82/IRQ2
71
PA0/TP0/TCLKA
72
73
PA3/TP3/IOCB0/TCLKD
76
PA2/TP2/TIOCA0/TCLKC
PA4/TP4/TIOCA1
77
PA1/TP1/TCLKB
PA5/TP5/TIOCB1
78
74
PA6/TP6/TIOCA2
79
75
PA7/TP7/TIOCB2
80
Figure 1-2 shows the pin arrangement of the H8/3032 Series, FP-80A and TFP-80C package.
PB0/TP8/TIOCA3
1
60
P71/AN1
P70/AN0
PB1/TP9/TIOCB3
2
59
PB2/TP10/TIOCA4
3
58
AVSS
PB3/TP11/TIOCB4
4
57
RESO
PB4/TP12/TOCXA4
5
56
P65/WR
PB5/TP13/TOCXB4
6
55
P64/RD
PB6/TP14
7
54
P63/AS
PB7/TP15/ADTRG
8
53
VCC
P90/TxD
9
52
XTAL
EXTAL
P92/RxD
10
Top view
51
P94/SCK/IRQ4
11
(FP-80A, TFP-80C)
50
VSS
VSS
12
49
NMI
31
32
33
34
35
36
37
38
39
40
P20/A8
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
P50/A16
P51/A17
P52/A18
P21/A9
41
30
20
VSS
P53/A19
P37/D7
29
P60/WAIT
42
P17/A7
43
19
28
18
P36/D6
P16/A6
P35/D5
27
MD0
P15/A5
44
26
17
P14/A4
MD1
P34/D4
25
45
P13/A3
16
24
ø
P33/D3
P12/A2
46
23
15
P11/A1
STBY
P32/D2
22
RES
47
P10/A0
48
14
21
13
VCC
P30/D0
P31/D1
Figure 1-2 Pin Arrangement (FP-80A, TFP-80C, Top View)
6
1.3.2 Pin Functions
Pin Assignments in Each Mode: Table 1-2 lists the FP-80A and TFP-80C pin assignments in
each mode.
Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode
Pin Name
Pin
No.
Mode 1
Mode 2
Mode 3
PROM Mode
1
PB0/TP8/TIOCA3
PB0/TP8/TIOCA3
PB0/TP8/TIOCA3
NC
2
PB1/TP9/TIOCB3
PB1/TP9/TIOCB3
PB1/TP9/TIOCB3
NC
3
PB2/TP10/TIOCA4
PB2/TP10/TIOCA4
PB2/TP10/TIOCA4
NC
4
PB3/TP11/TIOCB4
PB3/TP11/TIOCB4
PB3/TP11/TIOCB4
NC
5
PB4/TP12/TOCXA4
PB4/TP12/TOCXA4
PB4/TP12/TOCXA4
NC
6
PB5/TP13/TOCXB4
PB5/TP13/TOCXB4
PB5/TP13/TOCXB4
NC
7
PB6/TP14
PB6/TP14
PB6/TP14
NC
8
PB7/TP15/ADTRG
PB7/TP15/ADTRG
PB7/TP15/ADTRG
NC
9
P90/TxD
P90/TxD
P90/TxD
NC
10
P92/RxD
P92/RxD
P92/RxD
NC
11
P94/SCK/IRQ4
P94/SCK/IRQ4
P94/SCK/IRQ4
NC
12
VSS
VSS
VSS
VSS
13
D0
P30
P30
EO0
14
D1
P31
P31
EO1
15
D2
P32
P32
EO2
16
D3
P33
P33
EO3
17
D4
P34
P34
EO4
18
D5
P35
P35
EO5
19
D6
P36
P36
EO6
20
D7
P37
P37
EO7
21
VCC
VCC
VCC
VCC
22
P10/A0
P10
P10
EA0
23
P11/A1
P11
P11
EA1
24
P12/A2
P12
P12
EA2
25
P13/A3
P13
P13
EA3
26
P14/A4
P14
P14
EA4
Note: Pins marked NC should be left unconnected.
7
Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode (cont)
Pin Name
Pin
No.
Mode 1
Mode 2
Mode 3
PROM Mode
27
P15/A5
P15
P15
EA5
28
P16/A6
P16
P16
EA6
29
P17/A7
P17
P17
EA7
30
VSS
VSS
VSS
VSS
31
P20/A8
P20
P20
EA8
32
P21/A9
P21
P21
CE
33
P22/A10
P22
P22
EA10
34
P23/A11
P23
P23
EA11
35
P24/A12
P24
P24
EA12
36
P25/A13
P25
P25
EA13
37
P26/A14
P26
P26
EA14
38
P27/A15
P27
P27
CE
39
P50/A16
P50
P50
VCC
40
P51/A17
P51
P51
VCC
41
P52/A18
P52
P52
NC
42
P53/A19
P53
P53
NC
43
P60/WAIT
P54
P54
EA15
44
MD0
MD0
MD0
VSS
45
MD1
MD1
MD1
VSS
46
ø
ø
ø
NC
47
STBY
STBY
STBY
VSS
48
RES
RES
RES
NC
49
NMI
NMI
NMI
EA9
50
VSS
VSS
VSS
VSS
51
EXTAL
EXTAL
EXTAL
NC
52
XTAL
XTAL
XTAL
NC
53
VCC
VCC
VCC
VCC
8
Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode (cont)
Pin Name
Pin
No.
Mode 1
Mode 2
Mode 3
PROM Mode
54
AS
P63
P63
NC
55
RD
P64
P64
NC
56
WR
P65
P65
NC
57
RESO
RESO
RESO
VPP
58
AVSS
AVSS
AVSS
AVSS
59
P70/AN0
P70/AN0
P70/AN0
NC
60
P71/AN1
P71/AN1
P71/AN1
NC
61
P72/AN2
P72/AN2
P72/AN2
NC
62
P73/AN3
P73/AN3
P73/AN3
NC
63
P74/AN4
P74/AN4
P74/AN4
NC
64
P75/AN5
P75/AN5
P75/AN5
NC
65
P76/AN6
P76/AN6
P76/AN6
NC
66
P77/AN7
P77/AN7
P77/AN7
NC
67
VREF
VREF
VREF
VCC
68
AVCC
AVCC
AVCC
VCC
69
P80/IRQ0
P80/IRQ0
P80/IRQ0
EA16
70
P81/IRQ1
P81/IRQ1
P81/IRQ1
PGM
71
P82/IRQ2
P82/IRQ2
P82/IRQ2
NC
72
P83/IRQ3
P83/IRQ3
P83/IRQ3
NC
73
PA0/TP0/TCLKA
PA0/TP0/TCLKA
PA0/TP0/TCLKA
NC
74
PA1/TP1/TCLKB
PA1/TP1/TCLKB
PA1/TP1/TCLKB
NC
75
PA2/TP2/TIOCA0/TCLKC
PA2/TP2/TIOCA0/TCLKC
PA2/TP2/TIOCA0/TCLKC
NC
76
PA3/TP3/TIOCB0/TCLKD
PA3/TP3/TIOCB0/TCLKD
PA3/TP3/TIOCB0/TCLKD
NC
77
PA4/TP4/TIOCA1
PA4/TP4/TIOCA1
PA4/TP4/TIOCA1/A23
NC
78
PA5/TP5/TIOCB1
PA5/TP5/TIOCB1
PA5/TP5/TIOCB1/A22
NC
79
PA6/TP6/TIOCA2
PA6/TP6/TIOCA2
PA6/TP6/TIOCA2/A21
NC
80
PA7/TP7/TIOCB2
PA7/TP7/TIOCB2
PA7/TP7/TIOCB2/A20
NC
9
1.4 Pin Functions
Table 1-3 summarizes the pin functions.
Table 1-3 Pin Functions
Type
Symbol
Pin No.
I/O
Name and Function
Power
VCC
21, 53
Input
Power: For connection to the power supply
(+5 V). Connect all VCC pins to the +5-V system
power supply.
VSS
12, 30, 50
Input
Ground: For connection to ground (0 V).
Connect all VSS pins to the 0-V system power
supply.
XTAL
52
Input
For connection to a crystal resonator.
For examples of crystal resonator and external
clock input, see section 15, Clock Pulse
Generator.
EXTAL
51
Input
For connection to a crystal resonator or input of
an external clock signal. For examples of
crystal resonator and external clock input, see
section 15, Clock Pulse Generator.
ø
46
Output System clock: Supplies the system clock to
external devices
MD1,
MD0
45, 44
Input
Clock
Operating
mode control
System control RES
Mode 1 and mode 0: For setting the operating
mode, as follows
MD1
MD0
Operating Mode
0
0
—
0
1
Mode 1
01
0
Mode 2
1
1
Mode 3
48
Input
Reset input: When driven low, this pin resets
the H8/3032
RESO
57
Output Reset output: Outputs a reset signal to
external devices
STBY
47
Input
Standby: When driven low, this pin forces
a transition to hardware standby mode
10
Table 1-3 Pin Functions (cont)
Type
Symbol
Pin No.
I/O
Name and Function
Interrupts
NMI
49
Input
Nonmaskable interrupt: Requests a
nonmaskable interrupt
IRQ4 to
IRQ0
11,
72 to 69
Input
Interrupt request 4 to 0: Maskable interrupt
request pins
Address bus
A19 to A8,
A7 to A0
42 to 31,
29 to 22
Output Address bus: Outputs address signals
Data bus
D7 to D0
20 to 13
Input/
output
Bus control
AS
54
Output Address strobe: Goes low to indicate valid
address output on the address bus
RD
55
Output Read: Goes low to indicate reading from the
external address space
WR
56
Output High write: Goes low to indicate writing to the
external address space; indicates valid data on
the data bus.
WAIT
43
Input
Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
TCLKD to
TCLKA
76 to 73
Input
Clock input A to D: External clock inputs
TIOCA4 to
TIOCA0
3, 1, 79,
77, 75
Input/
output
Input capture/output compare A4 to A0:
GRA4 to GRA0 output compare or input
capture, or PWM output
TIOCB4 to
TIOCB0
4, 2, 80,
78, 76
Input/
output
Input capture/output compare B4 to B0:
GRB4 to GRB0 output compare or input
capture, or PWM output
TOCXA4
5
Output Output compare XA4: PWM output
TOCXB4
6
Output Output compare XB4: PWM output
8 to 1,
80 to 73
Output TPC output 15 to 0: Pulse output
16-bit
integrated
time unit
(ITU)
Programmable TP15 to
timing pattern TP0
controller (TPC)
11
Data bus: Bidirectional data bus
Table 1-3 Pin Functions (cont)
Type
Symbol
Pin No.
I/O
Serial communication
interface (SCI)
TxD
9
Output Transmit data: SCI data output
RxD
10
Input
Receive data: SCI data input
SCK
11
Input/
output
Serial clock: SCI clock input/output
AN7 to AN0 66 to 59
Input
Analog 7 to 0: Analog input pins
ADTRG
8
Input
A/D trigger: External trigger input for starting
A/D conversion
AVCC
68
Input
Power supply pin for the A/D converter.
Connect to the system power supply (+5 V)
when not using the A/D converter.
AVSS
58
Input
Ground pin for the A/D converter. Connect to
system ground (0 V) when not using the A/D
converter.
VREF
67
Input
Reference voltage input pin for the A/D
converter. Connect to the system power supply
(+5 V) when not using the A/D converter.
P17 to P10
29 to 22
Input/
output
Port 1: Eight input/output pins. The direction
of each pin can be selected in the port 1 data
direction register (P1DDR).
P27 to P20
38 to 31
Input/
output
Port 2: Eight input/output pins. The direction
of each pin can be selected in the port 2 data
direction register (P2DDR).
P37 to P30
20 to 13
Input/
output
Port 3: Eight input/output pins. The direction
of each pin can be selected in the port 3 data
direction register (P3DDR).
P53 to P50
42 to 39
Input/
output
Port 5: Four input/output pins. The direction of
each pin can be selected in the port 5 data
direction register (P5DDR).
P65 to P63, 56 to 54,
P60
43
Input/
output
Port 6: Four input/output pins. The direction
of each pin can be selected in the port 6 data
direction register (P6DDR).
P77 to P70
66 to 59
Input
Port 7: Eight input pins
P83 to P80
72 to 69
Input/
output
Port 8: Four input/output pins. The direction of
each pin can be selected in the port 8 data
direction register (P8DDR).
A/D
converter
I/O ports
Name and Function
12
Table 1-3 Pin Functions (cont)
Type
Symbol
Pin No.
I/O
Name and Function
I/O ports
P94, P92,
P90
11 to 9
Input/
output
Port 9: Three input/output pins. The direction
of each pin can be selected in the port 9 data
direction register (P9DDR).
PA7 to PA0
80 to 73
Input/
output
Port A: Eight input/output pins. The direction of
each pin can be selected in the port A data
direction register (PADDR).
Input/
output
Port B: Eight input/output pins. The direction of
each pin can be selected in the port B data
direction register (PBDDR).
PB7 to PB0 8 to 1
13
14
Section 2 CPU
2.1 Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1 Features
The H8/300H CPU has the following features.
•
Upward compatibility with H8/300 CPU
Can execute H8/300 series object programs without alteration
•
General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
•
Sixty-two basic instructions
— 8/16/32-bit arithmetic and logic instructions
— Multiply and divide instructions
— Powerful bit-manipulation instructions
•
Eight addressing modes
—
—
—
—
—
—
—
—
•
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, or @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8, PC) or @(d:16, PC)]
Memory indirect [@@aa:8]
1-Mbyte* linear address space
Note: * The CPU, if used alone, can access a maximum address space of 16 Mbytes. However,
the maximum address space of the H8/3032 Series is 1 Mbyte.
15
•
High-speed operation
—
—
—
—
—
—
—
•
All frequently-used instructions execute in two to four states
Maximum clock frequency:
16 MHz
8/16/32-bit register-register add/subtract: 125 ns
8 × 8-bit register-register multiply:
875 ns
16 ÷ 8-bit register-register divide:
875 ns
16 × 16-bit register-register multiply:
1.375 µs
32 ÷ 16-bit register-register divide:
1.375 µs
Two CPU operating modes
— Normal mode
— Advanced mode
•
Low-power mode
Transition to power-down state by SLEEP instruction
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
•
More general registers
Eight 16-bit registers have been added.
•
Expanded address space
— Advanced mode supports a maximum 1-Mbyte address space.
— Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
•
Enhanced addressing
The addressing modes have been enhanced to make effective use of the 1-Mbyte address
space.
•
Enhanced instructions
— Data transfer, arithmetic, and logic instructions can operate on 32-bit data.
— Signed multiply/divide instructions and other instructions have been added.
16
2.2 CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports up to 1 Mbytes. See figure 2-1.
Normal mode
Maximum 64 kbytes, program
and data areas combined
CPU operating modes
Advanced mode
Maximum 1 Mbyte, program
and data areas combined
Figure 2-1 CPU Operating Modes
17
2.3 Address Space
Figure 2-2 shows a simple memory map for the H8/3032 Series. The H8/300H CPU can address a
linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in
advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.
The 1-Mbyte operating mode uses 20-bit addressing. The upper 4 bits of effective addresses are
ignored.
H'00000
H'000000
H'FFFFF
H'FFFFFF
a. 1-Mbyte mode
b. 16-Mbyte mode
Figure 2-2 Memory Map
18
2.4 Register Configuration
2.4.1 Overview
The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers:
general registers and control registers.
General Registers (ERn)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7
E7
R7H
R7L
(SP)
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
Legend
SP: Stack pointer
PC: Program counter
CCR: Condition code register
Interrupt mask bit
I:
User bit or interrupt mask bit
UI:
Half-carry flag
H:
User bit
U:
Negative flag
N:
Zero flag
Z:
Overflow flag
V:
Carry flag
C:
Figure 2-3 CPU Registers
19
2.4.2 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
Figure 2-4 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers
(extended registers)
E0 to E7
RH registers
R0H to R7H
ER registers
ER0 to ER7
R registers
R0 to R7
RL registers
R0L to R7L
Figure 2-4 Usage of General Registers
20
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the
stack.
Free area
SP (ER7)
Stack area
Figure 2-5 Stack
2.4.3 Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register
(CCR).
Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU
will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so
the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is
regarded as 0.
Condition Code Register (CCR): This 8-bit register contains internal CPU status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted
regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details see section 5, Interrupt Controller.
21
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC,
and XORC instructions.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
•
•
•
Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and
UI bits, see section 5, Interrupt Controller.
2.4.4 Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit
in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular,
the stack pointer (ER7) is not initialized. The stack pointer must therefore be initialized by an
MOV.L instruction executed immediately after a reset.
22
2.5 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1,
2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as
two digits of 4-bit BCD data.
2.5.1 General Register Data Formats
Figures 2-6 and 2-7 show the data formats in general registers.
Data Type
General
Register
Data Format
7
1-bit data
RnH
0
7 6 5 4 3 2 1 0
Don’t care
7
1-bit data
Don’t care
RnL
7
4-bit BCD data
RnH
4 3
7 6 5 4 3 2 1 0
0
Don’t care
Upper digit Lower digit
7
4-bit BCD data
Byte data
Byte data
Don’t care
RnL
0
4 3
0
Upper digit Lower digit
7
0
MSB
LSB
Don’t care
RnH
7
0
MSB
LSB
Don’t care
RnL
Figure 2-6 General Register Data Formats (1)
23
Data Type
General
Register
Word data
Rn
Word data
Data Format
15
0
MSB
LSB
15
0
MSB
LSB
En
31
16 15
0
Longword data ERn
MSB
LSB
Legend
ERn: General register
En:
General register E
Rn:
General register R
RnH: General register RH
RnL: General register RL
MSB: Most significant bit
LSB: Least significant bit
Figure 2-7 General Register Data Formats (2)
2.5.2 Memory Data Formats
Figure 2-8 shows the data formats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, no address error occurs but
the least significant bit of the address is regarded as 0, so the access starts at the preceding
address. This also applies to instruction fetches.
24
Data Type
Address
Data Format
7
1-bit data
Address
7
Byte data
Address
MSB
Word data
Address 2m
MSB
0
6
5
4
Address 2m + 1
2
1
0
LSB
LSB
Address 2n
Longword data
3
MSB
Address 2n + 1
Address 2n + 2
Address 2n + 3
LSB
Figure 2-8 Memory Data Formats
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
25
2.6 Instruction Set
2.6.1 Instruction Set Overview
The H8/300H CPU has 62 types of instructions, which are classified in table 2-1.
Table 2-1 Instruction Classification
Function
Instruction
PUSH*1,
Types
POP*1,
MOVTPE*2,
MOVFPE*2
3
Data transfer
MOV,
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS,
MULXU, DIVXU, MULXS, DIVXS, CMP, NEG, EXTS, EXTU
18
Logic operations
AND, OR, XOR, NOT
4
Shift operations
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR,
BIXOR, BLD, BILD, BST, BIST
14
Branch
Bcc*3, JMP, BSR, JSR, RTS
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
9
Block data transfer
EEPMOV
1
Total 62 types
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
POP.L ERn is identical to MOV.L @SP+, Rn.
PUSH.L ERn is identical to MOV.L Rn, @–SP.
2. They are not available on H8/3032.
3. Bcc is a generic branching instruction.
26
2.6.2 Instructions and Addressing Modes
Table 2-2 indicates the instructions available in the H8/300H CPU.
Table 2-2 Instructions and Addressing Modes
Addressing Modes
Rn
@
@
(d:16, (d:24, @ERn+/ @
@ERn ERn) ERn) @–ERn aa:8
Function
Instruction
#xx
Data
transfer
MOV
BWL BWL BWL
BWL
BWL
BWL
B
@
aa:16
@
@
(d:8,
aa:24 PC)
@
(d:16, @@
PC)
aa:8
Implied
BWL
BWL
—
—
—
—
POP, PUSH
—
—
—
—
—
—
—
—
—
—
—
—
WL
MOVFPE,
MOVTPE
—
—
—
—
—
—
—
B
—
—
—
—
—
Arithmetic ADD, CMP
operations SUB
BWL BWL —
—
—
—
—
—
—
—
—
—
—
WL
—
—
—
—
—
—
—
—
—
—
BWL —
ADDX, SUBX B
B
—
—
—
—
—
—
—
—
—
—
—
ADDS, SUBS —
L
—
—
—
—
—
—
—
—
—
—
—
INC, DEC
—
BWL —
—
—
—
—
—
—
—
—
—
—
DAA, DAS
—
B
—
—
—
—
—
—
—
—
—
—
—
DIVXU,
MULXS,
MULXU,
DIVXS
—
BW
—
—
—
—
—
—
—
—
—
—
—
NEG
—
BWL —
—
—
—
—
—
—
—
—
—
—
EXTU, EXTS
—
WL
—
—
—
—
—
—
—
—
—
—
—
BWL BWL —
—
—
—
—
—
—
—
—
—
—
—
Logic
AND, OR,
operations XOR
NOT
—
BWL —
—
—
—
—
—
—
—
—
—
Shift instructions
—
BWL —
—
—
—
—
—
—
—
—
—
—
Bit manipulation
—
B
—
—
—
B
—
—
—
—
—
—
Branch
System
control
B
Bcc, BSR
—
—
—
—
—
—
—
—
—
o
o
—
—
JMP, JSR
—
—
o
—
—
—
—
—
o
—
—
o
—
RTS
—
—
—
—
—
—
—
—
—
—
—
—
o
TRAPA
—
—
—
—
—
—
—
—
—
—
—
—
o
RTE
—
—
—
—
—
—
—
—
—
—
—
—
o
SLEEP
—
—
—
—
—
—
—
—
—
—
—
—
o
LDC
B
B
W
W
W
W
—
W
W
—
—
—
—
STC
—
B
W
W
W
W
—
W
W
—
—
—
—
ANDC, ORC, B
XORC
—
—
—
—
—
—
—
—
—
—
—
—
NOP
—
—
—
—
—
—
—
—
—
—
—
—
o
—
—
—
—
—
—
—
—
—
—
—
—
BW
Block data transfer
Legend
B: Byte
W: Word
L: Longword
27
2.6.3 Tables of Instructions Classified by Function
Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation
used in these tables is defined next.
Operation Notation
Rd
General register (destination)*
Rs
General register (source)*
Rn
General register*
ERn
General register (32-bit register or address register)
(EAd)
Destination operand
(EAs)
Source operand
CCR
Condition code register
N
N (negative) flag of CCR
Z
Z (zero) flag of CCR
V
V (overflow) flag of CCR
C
C (carry) flag of CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
AND logical
∨
OR logical
⊕
Exclusive OR logical
→
Move
¬
NOT (logical complement)
:3/:8/:16/:24
3-, 8-, 16-, or 24-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
28
Table 2-3 Data Transfer Instructions
Instruction Size*
Function
MOV
(EAs) → Rd, Rs → (EAd)
B/W/L
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
(EAs) → Rd
Cannot be used in the H8/3032.
MOVTPE
B
Rs → (EAs)
Cannot be used in the H8/3032.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W
Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
29
Table 2-4 Arithmetic Operation Instructions
Instruction Size*
Function
ADD,
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
ADDX,
SUBX
B
INC,
DEC
B/W/L
ADDS,
SUBS
L
DAA,
DAS
B
MULXU
B/W
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data cannot
be subtracted from data in a general register. Use the SUBX or ADD
instruction.)
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on data in two general
registers, or on immediate data and data in a general register.
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands can
be incremented or decremented by 1 only.)
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
30
Table 2-4 Arithmetic Operation Instructions (cont)
Instruction Size*
Function
DIVXU
Rd ÷ Rs → Rd
B/W
Performs unsigned division on data in two general registers: either
16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either
16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register or
with immediate data, and sets CCR according to the result.
NEG
B/W/L
0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a general
register.
EXTS
W/L
Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by extending the sign bit.
EXTU
W/L
Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by padding with zeros.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
31
Table 2-5 Logic Operation Instructions
Instruction Size*
Function
AND
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
B/W/L
Performs a logical AND operation on a general register and another general
register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another general
register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and another
general register or immediate data.
NOT
B/W/L
¬ Rd → Rd
Takes the one’s complement of general register contents.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2-6 Shift Instructions
Instruction Size*
Function
SHAL,
SHAR
B/W/L
Rd (shift) → Rd
SHLL,
SHLR
B/W/L
ROTL,
ROTR
B/W/L
ROTXL,
ROTXR
B/W/L
Performs an arithmetic shift on general register contents.
Rd (shift) → Rd
Performs a logical shift on general register contents.
Rd (rotate) → Rd
Rotates general register contents.
Rd (rotate) → Rd
Rotates general register contents through the carry bit.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
32
Table 2-7 Bit Manipulation Instructions
Instruction Size*
Function
BSET
1 → (<bit-No.> of <EAd>)
B
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit immediate
data or the lower 3 bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND
B
C ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
33
Table 2-7 Bit Manipulation Instructions (cont)
Instruction Size*
Function
BOR
C ∨ (<bit-No.> of <EAd>) → C
B
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR
B
C ∨ [¬ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIXOR
B
C ⊕ [¬ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
C → ¬ (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
34
Table 2-8 Branching Instructions
Instruction Size
Function
Bcc
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
—
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
Bcc (BHS)
Carry clear (high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address
BSR
—
Branches to a subroutine at a specified address
JSR
—
Branches to a subroutine at a specified address
RTS
—
Returns from a subroutine
35
Table 2-9 System Control Instructions
Instruction Size*
Function
TRAPA
—
Starts trap-instruction exception handling
RTE
—
Returns from an exception-handling routine
SLEEP
—
Causes a transition to the power-down state
LDC
B/W
(EAs) → CCR
Moves the source operand contents to the condition code register. The
condition code register size is one byte, but in transfer from memory, data is
read by word access.
STC
B/W
CCR → (EAd)
Transfers the CCR contents to a destination location. The condition code
register size is one byte, but in transfer to memory, data is written by word
access.
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data.
XORC
B
CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate data.
NOP
—
PC + 2 → PC
Only increments the program counter.
Note: * Size refers to the operand size.
B: Byte
W: Word
36
Table 2-10 Block Transfer Instruction
Instruction Size
Function
EEPMOV.B —
if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L – 1 → R4L
until
R4L = 0
else next;
EEPMOV.W —
if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 – 1 → R4
until
R4 = 0
else next;
Transfers a data block according to parameters set in general registers R4L
or R4, ER5, and ER6.
R4L or R4: Size of block (bytes)
ER5:
Starting source address
ER6:
Starting destination address
Execution of the next instruction begins as soon as the transfer is
completed.
37
2.6.4 Basic Instruction Formats
The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data
registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register
field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2-9 shows examples of instruction formats.
Operation field only
op
NOP, RTS, etc.
Operation field and register fields
op
rn
rm
ADD.B Rn, Rm, etc.
Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm
EA (disp)
Operation field, effective address extension, and condition field
op
cc
EA (disp)
Figure 2-9 Instruction Formats
38
BRA d:8
2.6.5 Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling
routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag
ahead of time.
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2-11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2-11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16, ERn)/@d:24, ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8, PC)/@(d:16, PC)
8
Memory indirect
@@aa:8
39
1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit
register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit
registers.
2 Register Indirect—@ERn: The register field of the instruction code specifies an address
register (ERn), the lower 24 bits of which contain the address of the operand.
3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit
displacement contained in the instruction code is added to the contents of an address register
(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the
address of a memory operand. A 16-bit displacement is sign-extended when added.
4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
•
Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
•
Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result become the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the
resulting register value should be even.
5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A
24-bit absolute address can access the entire address space. Table 2-12 indicates the accessible
address ranges.
40
Table 2-12 Absolute Address Access Ranges
Absolute
Address
1-Mbyte Modes
64-kbyte Modes
8 bits (@aa:8)
H'FFF00 to H'FFFFF
(1048320 to 1048575)
H'FF00 to H'FFFF
(65280 to 65535)
16 bits (@aa:16)
H'00000 to H'07FFF,
H'F8000 to H'FFFFF
(0 to 32767, 1015808 to 1048575)
H'0000 to H'FFFF
(0 to 65535)
24 bits (@aa:24)
H'00000 to H'FFFFF
(0 to 1048575)
H'000000 to H'00FFFF
(0 to 65535)
6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.
The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.
7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is signextended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The memory operand is accessed by longword access. The
first byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2-10.
The upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is
0 to 255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector
area. For further details see section 5, Interrupt Controller.
41
Reserved
Specified by @aa:8
Branch address
Figure 2-10 Memory-Indirect Branch Address Specification
When a word-size or longword-size memory operand is specified, or when a branch address is
specified, if the specified memory address is odd, the least significant bit is regarded as 0. The
accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,
Memory Data Formats.
2.7.2 Effective Address Calculation
Table 2-13 explains how an effective address is calculated in each addressing mode. In the
1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to
generate a 20-bit effective address.
42
Table 2-13 Effective Address Calculation
No.
Addressing Mode and
Instruction Format
1
Register direct (Rn)
op
2
Effective Address Calculation
Effective Address
Operand is general
register contents
rm rn
Register indirect (@ERn)
31
0
23
0
23
0
23
0
23
0
General register contents
op
3
r
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
31
0
General register contents
43
op
4
r
disp
Sign extension
disp
Register indirect with post-increment
or pre-decrement
Register indirect with post-increment
@ERn+
op
r
0
General register contents
r
Register indirect with pre-decrement
@–ERn
op
31
1, 2, or 4
31
0
General register contents
1, 2, or 4
1 for a byte operand, 2 for a word
operand, 4 for a longword operand
Table 2-13 Effective Address Calculation (cont)
No.
5
Addressing Mode and
Instruction Format
Effective Address Calculation
Effective Address
23
Absolute address
@aa:8
op
8 7
0
H'FFFF
abs
23
16 15
0
Sign
extension
@aa:16
op
abs
23
0
@aa:24
44
op
abs
6
Immediate
#xx:8, #xx:16, or #xx:32
op
7
Operand is immediate data
IMM
Program-counter relative
@(d:8, PC) or @(d:16, PC)
23
0
PC contents
Sign
extension
op
disp
disp
23
0
Table 2-13 Effective Address Calculation (cont)
No.
8
Addressing Mode and
Instruction Format
Effective Address Calculation
Effective Address
Memory indirect
@@aa:8
Normal mode
op
abs
23
8 7
0
abs
H'0000
15
0
Memory contents
23 16 15
H'00
0
23
0
Advanced mode
op
abs
45
23
8 7
H'0000
31
0
Memory contents
Legend
r, rm, rn:
op:
disp:
IMM:
abs:
Register field
Operation field
Displacement
Immediate data
Absolute address
0
abs
2.8 Processing States
2.8.1 Overview
The H8/300H CPU has five processing states: the program execution state, exception-handling
state, power-down state, reset state, and bus-released state. The power-down state includes sleep
mode, software standby mode, and hardware standby mode. Figure 2-11 classifies the processing
states. Figure 2-13 indicates the state transitions.
Processing states
Program execution state
The CPU executes program instructions in sequence
Exception-handling state
A transient state in which the CPU executes a hardware sequence
(saving PC and CCR, fetching a vector, etc.) in response to a reset,
interrupt, or other exception
Reset state
The CPU and all on-chip supporting modules are initialized and halted
Sleep mode
Power-down state
The CPU is halted to conserve power
Software standby mode
Hardware standby mode
Figure 2-11 Processing States
46
2.8.2 Program Execution State
In this state the CPU executes program instructions in normal sequence.
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2-14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2-14 Exception Handling Types and Priority
Priority Type of Exception Detection Timing
Start of Exception Handling
High
Low
Reset
Synchronized with clock
Exception handling starts immediately
when RES changes from low to high
Interrupt
End of instruction
execution or end of
exception handling*
When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence
Trap instruction
When TRAPA instruction
is executed
Exception handling starts when a trap
(TRAPA) instruction is executed
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or
immediately after reset exception handling.
Figure 2-12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
47
Reset
External interrupts
Exception
sources
Interrupt
Internal interrupts (from on-chip supporting modules)
Trap instruction
Figure 2-12 Classification of Exception Sources
Program execution state
SLEEP
instruction
with SSBY = 0
End of
exception
handling
Exception
Sleep mode
SLEEP instruction
with SSBY = 1
Interrupt
Exception-handling state
NMI, IRQ 0 , IRQ 1,
or IRQ 2 interrupt
Software standby mode
RES = 1
STBY = 1, RES = 0
Reset state*1
*2
Hardware standby mode
Power-down state
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
Figure 2-13 State Transitions
48
2.8.4 Exception-Handling Sequences
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
the CPU fetches a start address from the exception vector table and execution branches to that
address.
Figure 2-14 shows the stack after the exception-handling sequence.
SP–4
SP (ER7)
SP–3
SP+1
SP–2
SP+2
SP–1
SP+3
SP (ER7)
Stack area
Before exception
handling starts
CCR
PC
SP+4
Pushed on stack
Even
address
After exception
handling ends
Legend
CCR: Condition code register
SP:
Stack pointer
Notes: 1. PC is the address of the first instruction executed after the return from the
exception-handling routine.
2. Registers must be saved and restored by word access or longword access,
starting at an even address.
Figure 2-14 Stack Structure after Exception Handling
49
2.8.5 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The
I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details see section 10,
Watchdog Timer.
2.8.6 Power-Down State
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep
mode, software standby mode, and hardware standby mode.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop
immediately after execution of the SLEEP instruction, but the contents of CPU registers are
retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all
on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long
as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
The I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input
goes low. As in software standby mode, the CPU and clock halt and the on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
For further information see section 16, Power-Down State.
50
2.9 Basic Operational Timing
2.9.1 Overview
The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the
system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.
2.9.2 On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and
word access. Figure 2-15 shows the on-chip memory access cycle. Figure 2-16 indicates the pin
states.
Bus cycle
T1 state
T2 state
ø
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2-15 On-Chip Memory Access Cycle
51
T1
T2
ø
Address bus
AS , RD, WR
Address
High
High impedance
D7 to D0
Figure 2-16 Pin States during On-Chip Memory Access
52
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the register being accessed. Figure 2-17 shows the on-chip supporting module
access timing. Figure 2-18 indicates the pin states.
Bus cycle
T1 state
T2 state
T3 state
ø
Address
Address bus
Read
access
Internal read signal
Internal data bus
Read data
Internal write signal
Write
access
Internal data bus
Write data
Figure 2-17 Access Cycle for On-Chip Supporting Modules
53
T1
T2
T3
ø
Address bus
AS , RD, HWR , LWR
Address
High
High impedance
D7 to D0
Figure 2-18 Pin States during Access to On-Chip Supporting Modules
2.9.4 Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in
two or three states. For details see section 6, Bus Controller.
54
Section 3 MCU Operating Modes
3.1 Overview
3.1.1 Operating Mode Selection
The H8/3032 Series has three operating modes (modes 1 to 3) that are selected by the mode pins
(MD1 and MD0) as indicated in table 3-1. The input at these pins determines expanded mode or
single-chip mode.
Table 3-1 Operating Mode Selection
Mode Pins
Description
Operating Mode
MD1
MD0
Address Space
Initial Bus Width*1
On-Chip RAM
—
0
0
—
—
—
Mode 1
0
1
1 Mbyte
8 bits
Enabled*1
Mode 2
1
0
64 kbytes
—
Enabled*2
Mode 3
1
1
1 Mbyte
—
Enabled*2
Notes: 1. In mode 1, if the RAM enable bit (RAME) in the system control register (SYSCR) is
cleared to 0, these addresses become external addresses.
2. In modes 2 and 3, clearing bit RAME of SYSCR to 0 and reading the on-chip RAM
always returns H’FF, and write access is ignored. For details, see section 13.3,
Operation.
For the address space size there are two choices: 64 kbytes or 1 Mbyte.
Modes 1 and 3 support a maximum address space of 1 Mbyte. Mode 2 supports a maximum
address space of 64 kbytes.
The H8/3032 Series can only be used in modes 1 to 3. The inputs at the mode pins must select one
of these three modes. The inputs at the mode pins must not be changed during operation.
55
3.1.2 Register Configuration
The H8/3032 Series has a mode control register (MDCR) that indicates the inputs at the mode
pins (MD2 to MD0), and a system control register (SYSCR). Table 3-2 summarizes these registers.
Table 3-2 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFF1
Mode control register
MDCR
R
Undetermined
H'FFF2
System control register
SYSCR
R/W
H'0B
Note: * The lower 16 bits of the address are indicated.
56
3.2 Mode Control Register (MDCR)
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3032
Series.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
MDS1
MDS0
Initial value
1
1
0
0
0
1
—*
—*
Read/Write
—
—
—
—
—
—
R
R
Reserved bits
Mode select 1 and 0
Bits indicating the current
operating mode
Note: * Determined by pins MD 1 and MD 0 .
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bits 5 to 3—Reserved: Read-only bits, always read as 0.
Bit 2—Reserved: Read-only bit, always read as 1.
Bits 1 and 0—Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the logic levels at
pins MD1 and MD0 (the current operating mode). MDS1 and MDS0 correspond to MD1 and
MD0. MDS1 and MDS0 are read-only bits. The mode pin (MD1 and MD0) levels are latched
when MDCR is read.
57
3.3 System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3032 Series.
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
—
RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
Enables or
disables
on-chip RAM
Reserved bit
NMI edge select
Selects the valid edge
of the NMI input
User bit enable
Selects whether to use UI bit in CCR 6
as a user bit or an interrupt mask bit
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
Software standby
Enables transition to software standby mode
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 16, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit 7
SSBY
Description
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
58
(Initial value)
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the internal clock oscillator to settle when software
standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at
least 8 ms at the system clock rate. For further information about waiting time selection, see
section 19.4.3, Selection of Oscillator Waiting Time after Exit from Software Standby Mode.
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Waiting time = 8192 states
0
0
1
Waiting time = 16384 states
0
1
0
Waiting time = 32768 states
0
1
1
Waiting time = 65536 states
1
0
—
Waiting time = 131072 states
1
1
—
Illegal setting
(Initial value)
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3
UE
Description
0
UI bit in CCR is used as an interrupt mask bit
1
UI bit in CCR is used as a user bit
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG
Description
0
An interrupt is requested at the falling edge of NMI
1
An interrupt is requested at the rising edge of NMI
(Initial value)
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
(Initial value)
59
3.4 Operating Mode Descriptions
3.4.1 Mode 1
1-Mbyte address space can be accessed including the on-chip ROM addresses. Port 3 pins
function as data pins D7 to D0 and port 1, 2, and 5 pins function as address pins A19 to A0. The
address bus width can be selected by setting DDR of ports 1, 2, and 5.
3.4.2 Mode 2
This mode is a normal mode with a 64-kbyte address space which operates using the on-chip
ROM, RAM, and registers. External addresses cannot be accessed. The vector area and stack area
can be saved.
3.4.3 Mode 3
This mode is an advanced mode with a 1-Mbyte address space which operates using the on-chip
ROM, RAM, and registers. External addresses cannot be accessed.
60
3.5 Pin Functions in Each Operating Mode
The pin functions of ports 1, 2, 3, 5, and 6 vary depending on the operating mode. Table 3-3
indicates their functions in each operating mode.
Table 3-3 Pin Functions in Each Mode
Port
Mode 1
Modes 2, 3
Port 1
P17 to P10*1
P17 to P10
Port 2
P27 to P20*1
P27 to P20
Port 3
D7 to D0
P37 to P30
Port 5
P53 to P50*1
P53 to P50
Port 6
WR, RD, AS, P66/WAIT*2
P65 to P63, P60
Notes: 1. Initial state. These pins function as an address bus by setting the corresponding DDR
bit to 1.
2. The functions of these pins vary depending on the settings in the wait state controller
enable register (WCER), wait control register (WCR), and port data direction register.
3.6 Memory Map in Each Operating Mode
Figure 3-1 shows a memory map of the H8/3032. Figure 3-2 shows a memory map of the
H8/3031. Figure 3-3 shows a memory map of the H8/3030. The address space is divided into
eight areas.
61
Vector table
H'00FF
H'00000
Vector table
H'000FF
On-chip ROM
On-chip ROM
H'07FFF
16-bit absolute addresses
(first half)
On-chip ROM
H'0000
Mode 3
(single-chip advanced mode)
8-bit memoryindirect addresses
H'000FF
Mode 2
(single-chip normal mode)
8-bit memoryindirect addresses
Vector table
16-bit absolute addresses
(first half)
H'00000
8-bit memoryindirect addresses
Mode 1
(expanded mode with on-chip ROM)
H'07FFF
H'0FFFF
H'10000
H'0FFFF
H'F70F
H'F710
Area 0
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
Area 2
Area 3
External
addresses
Area 4
H'FF00
H'FF0F
H'FF1C
Area 5
On-chip registers
Area 6
8-bit absolute
addresses
H'FFFF
Area 7
H'F8000
H'F8000
H'FF70F
H'FF710
External
addresses
H'FFF1B
H'FFF1C
On-chip register
On-chip RAM
16-bit absolute addresses
(second half)
H'FFF00
H'FFF0F
H'FFF10
8-bit absolute addresses
On-chip RAM*
H'FFF00
H'FFF0F
H'FFF1C
On-chip registers
H'FFFFF
H'FFFFF
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3-1 H8/3032 Memory Map in Each Operating Mode
62
16-bit absolute addresses
(second half)
H'FF710
8-bit absolute addresses
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
On-chip RAM
Area 1
Vector table
H'00FF
H'00000
Vector table
H'000FF
On-chip ROM
On-chip ROM
16-bit absolute addresses
(first half)
On-chip ROM
H'0000
Mode 3
(single-chip advanced mode)
8-bit memoryindirect addresses
H'000FF
Mode 2
(single-chip normal mode)
8-bit memoryindirect addresses
Vector table
16-bit absolute addresses
(first half)
H'00000
8-bit memoryindirect addresses
Mode 1
(expanded mode with on-chip ROM)
H'07FFF
H'07FFF
Reserved
H'0FFFF
H'10000
H'7FFF
Area 0
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
On-chip RAM
Area 2
Area 3
External
addresses
Area 4
H'FF00
H'FF0F
H'FF1C
Area 5
On-chip registers
Area 6
H'FFFF
Area 7
H'F8000
H'F8000
H'FF710
H'FFB0F
8-bit absolute
addresses
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'FB10
Area 1
Reserved
H'FFB10
H'FFF1B
H'FFF1C
On-chip register
H'FFF00
H'FFF0F
H'FFF1C
On-chip registers
H'FFFFF
H'FFFFF
Notes: 1. External addresses can be accessed by disabling on-chip ROM.
2. Do not accessed reserved areas.
Figure 3-2 H8/3031 Memory Map in Each Operating Mode
63
8-bit absolute addresses
External
addresses
On-chip RAM
16-bit absolute addresses
(second half)
H'FFF00
H'FFF0F
H'FFF10
8-bit absolute addresses
On-chip RAM*1
16-bit absolute addresses
(second half)
H'FFB10
H'00FF
H'00000
Vector table
H'000FF
On-chip ROM
On-chip ROM
16-bit absolute addresses
(first half)
On-chip ROM
Vector table
Mode 3
(single-chip advanced mode)
8-bit memoryindirect addresses
H'000FF
H'0000
8-bit memoryindirect addresses
Vector table
16-bit absolute addresses
(first half)
H'00000
Mode 2
(single-chip normal mode)
8-bit memoryindirect addresses
Mode 1
(with on-chip ROM)
H'03FFF
H'03FFF
Reserved
H'0FFFF
H'10000
H'3FFF
Area 0
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
On-chip RAM
Area 2
Area 3
External
addresses
Area 4
H'FF00
H'FF0F
H'FF1C
Area 5
On-chip registers
Area 6
H'FFFF
Area 7
H'F8000
H'F8000
H'FF710
H'FFD0F
8-bit absolute
addresses
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'FD10
Area 1
Reserved
H'FFD10
H'FFF1B
H'FFF1C
On-chip register
H'FFF00
H'FFF0F
H'FFF1C
On-chip registers
H'FFFFF
H'FFFFF
Notes: 1. External addresses can be accessed by disabling on-chip ROM.
2. Do not accessed reserved areas.
Figure 3-3 H8/3030 Memory Map in Each Operating Mode
64
16-bit absolute addresses
(second half)
External
addresses
On-chip RAM
8-bit absolute addresses
H'FFF00
H'FFF0F
H'FFF10
8-bit absolute addresses
On-chip RAM*1
16-bit absolute addresses
(second half)
H'FFD10
Section 4 Exception Handling
4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.
Table 4-1 Exception Types and Priority
Priority Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES pin
Interrupt
Interrupt requests are handled when execution of the current
instruction or handling of the current exception is completed
Low
Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA)
4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.
1.
The program counter (PC) and condition code register (CCR) are pushed onto the stack.
2.
The CCR interrupt mask bit is set to 1.
3.
A vector address corresponding to the exception source is generated, and program execution
starts from the address indicated in the vector address.
For a reset exception, steps 2 and 3 above are carried out.
65
4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4-1. Different vectors are assigned to
different exception sources. Table 4-2 lists the exception sources and their vector addresses.
• Reset
External interrupts: NMI, IRQ 0 to IRQ4
Exception
sources
• Interrupts
• Trap instruction
Internal interrupts: 21 interrupts from on-chip
supporting modules
Figure 4-1 Exception Sources
Table 4-2 Exception Vector Table
Vector Address*1
Advanced Mode
Normal Mode
H'0000 to H'0003
H'0000 to H'0001
H'0004 to H'0007
H'0002 to H'0003
H'0008 to H'000B
H'0004 to H'0005
H'000C to H'000F
H'0006 to H'0007
H'0010 to H'0013
H'0008 to H'0009
H'0014 to H'0017
H'000A to H'000B
H'0018 to H'001B
H'000C to H'000D
H'001C to H'001F
H'000E to H'000F
H'0020 to H'0023
H'0010 to H'0011
H'0024 to H'0027
H'0012 to H'0013
H'0028 to H'002B
H'0014 to H'0015
H'002C to H'002F
H'0016 to H'0017
H'0030 to H'0033
H'0018 to H'0019
H'0034 to H'0037
H'001A to H'001B
H'0038 to H'003B
H'001C to H'001D
H'003C to H'003F
H'001E to H'001F
H'0040 to H'0043
H'0020 to H'0021
H'0044 to H'0047
H'0022 to H'0023
H'0048 to H'004B
H'0024 to H'0025
H'004C to H'004F
H'0026 to H'0027
H'0050 to H'0053
H'0028 to H'0029
to
H'00F0 to H'00F3
H'0078 to H'0079
Exception Source
Reset
Reserved for system use
Vector Number
0
1
2
3
4
5
6
External interrupt (NMI)
7
Trap instruction (4 sources)
8
9
10
11
External interrupt
IRQ0
12
IRQ1
13
IRQ2
14
IRQ3
15
IRQ4
16
Reserved for system use
17
18
19
Internal interrupts*2
20
to
60
Notes: 1. Lower 16 bits of the address.
2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table.
66
4.2 Reset
4.2.1 Overview
A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the
H8/3032 Series enters the reset state. A reset initializes the internal state of the CPU and the
registers of the on-chip supporting modules. Reset exception handling begins when the RES pin
changes from low to high.
The H8/3032 Series can also be reset by overflow of the watchdog timer. For details see section
10, Watchdog Timer.
4.2.2 Reset Sequence
The H8/3032 Series enters the reset state when the RES pin goes low.
To ensure that the H8/3032 Series is reset, hold the RES pin low for at least 20 ms at power-up. To
reset the H8/3032 Series during operation, hold the RES pin low for at least 10 system clock (ø)
cycles. See appendix D.2, Pin States at Reset, for the states of the pins in the reset state.
When the RES pin goes high after being held low for the necessary time, the H8/3032 Series starts
reset exception handling as follows.
•
The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
•
The contents of the reset vector address (H'0000 to H'0003 in advanced mode, H'0000 to
H'0001 in normal mode) are read, and program execution starts from the address indicated in
the vector address.
Figure 4-2 shows the reset sequence in modes 1 and 3. Figure 4-3 shows the reset sequence in
mode 2.
67
Internal
processing
Vector fetch
Prefetch of
first program
instruction
ø
68
Figure 4-2 Reset Sequence (Modes 1 and 3)
RES
Address
bus
(1)
(3)
(5)
Internal read
signal
Internal write
signal
On chip data
(1), (3)
(2), (4)
(5)
(6)
(2)
(4)
Address of reset vector: (1) = H'00000, (3) = H'00002
Start address (contents of reset vector)
Start address
First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
(6)
Internal
processing
Vector fetch
Prefetch of first
program instruction
ø
RES
Address bus
(1)
(3)
(5)
RD
WR
High
(2)
D15 to D0
(1), (3)
(2), (4)
(5)
(6)
(4)
(6)
Address of reset vector: (1) = H'00000, (3) = H'00002
Start address (contents of reset vector)
Start address
First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Figure 4-3 Reset Sequence (Mode 2)
4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR
will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. The first instruction of the program is
always executed immediately after the reset state ends. This instruction should initialize the stack
pointer (example: MOV.L #xx:32, SP).
69
4.3 Interrupts
Interrupt exception handling can be requested by nine external sources (NMI, IRQ0 to IRQ4) and
21 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit
integrated timer unit (ITU), serial communication interface (SCI), and A/D converter. Each
interrupt source has a separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
External interrupts
NMI (1)
IRQ 0 to IRQ 4 (5)
Internal interrupts
WDT* (1)
ITU (15)
SCI (4)
A/D converter (1)
Interrupts
Note: Numbers in parentheses are the number of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
Figure 4-4 Interrupt Sources and Number of Interrupts
70
4.4 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
71
4.5 Stack Status after Exception Handling
Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP-4
SP-3
SP-2
SP-1
SP (ER7) →
SP (ER7) →
SP+1
SP+2
SP+3
SP+4
Stack area
Before exception handling
CCR
CCR *
PC H
PC L
Even address
After exception handling
Save on stack
a. Normal mode
SP-4
SP-3
SP-2
SP-1
SP (ER7) →
SP (ER7) →
SP+1
SP+2
SP+3
SP+4
Stack area
Before exception handling
CCR
PC E
PC H
PC L
Even address
After exception handling
Save on stack
b. Advanced mode
Legend
PCE: Bits 23 to 16 of program counter (PC)
PCH: Bits 15 to 8 of program counter (PC)
PCL: Bits 7 to 0 of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: * Ignored upon return.
1. This is the address of the first instruction executed after return.
2. Saving and restoring of registers must be conducted at even addresses in word-size
or longword-size units.
Figure 4-5 Stack after Completion of Exception Handling
72
4.6 Notes on Stack Usage
When accessing word data or longword data, the H8/3032 Series regards the lowest address bit as
0. The stack should always be accessed by word access or longword access, and the value of the
stack pointer (SP, ER7) should always be kept even. Use the following instructions to save
registers:
PUSH.W Rn (or MOV.W Rn, @–SP)
PUSH.L ERn (or MOV.L ERn, @–SP)
Use the following instructions to restore registers:
POP.W Rn
POP.L ERn
(or MOV.W @SP+, Rn)
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4-6 shows an example of what
happens when the SP value is odd.
CCR
SP
RIL
SP
H'FFFEFA
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFF
SP
TRAPA instruction executed
SP set to H'FFFEFF
MOV. B RIL, @-ER7
Data saved above SP
CCR contents lost
Legend
CCR: Condition code register
PC: Program counter
R1L: General register R1L
SP: Stack pointer
Note: The diagram illustrates modes 1 and 3.
Figure 4-6 Operation when SP Value is Odd
73
74
Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
•
Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
•
Three-level masking by the I and UI bits in the CPU condition code register (CCR)
•
Independent vector addresses
All interrupts are independently vectored; the interrupt service routine does not have to
identify the interrupt source.
•
Six external interrupt pins
NMI has the highest priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ0 to IRQ4, sensing of the falling edge or level sensing can be
selected independently.
75
5.1.2 Block Diagram
Figure 5-1 shows a block diagram of the interrupt controller.
CPU
ISCR
IER
IPRA, IPRB
NMI
input
IRQ input
section ISR
IRQ input
OVF
TME
.
.
.
.
.
.
.
ADI
ADIE
Priority
decision logic
Interrupt
request
Vector
number
.
.
.
I
UI
Interrupt controller
UE
SYSCR
Legend
I:
IER:
IPRA:
IPRB:
ISCR:
ISR:
SYSCR:
UE:
UI:
Interrupt mask bit
IRQ enable register
Interrupt priority register A
Interrupt priority register B
IRQ sense control register
IRQ status register
System control register
User bit enable
User bit/interrupt mask bit
Figure 5-1 Interrupt Controller Block Diagram
76
CCR
5.1.3 Pin Configuration
Table 5-1 lists the interrupt pins.
Table 5-1 Interrupt Pins
Name
Abbreviation
I/O
Function
Nonmaskable interrupt
NMI
Input
Nonmaskable interrupt, rising edge or
falling edge selectable
Input
Maskable interrupts, falling edge or
level sensing selectable
External interrupt request 4 to 0 IRQ4 to IRQ0
5.1.4 Register Configuration
Table 5-2 lists the registers of the interrupt controller.
Table 5-2 Interrupt Controller Registers
Address*1
Name
Abbreviation
R/W
Initial Value
H'FFF2
System control register
SYSCR
R/W
H'0B
H'FFF4
IRQ sense control register
ISCR
R/W
H'00
H'FFF5
IRQ enable register
IER
R/W
H'00
H'FFF6
IRQ status register
ISR
R/(W)*2
H'00
H'FFF8
Interrupt priority register A
IPRA
R/W
H'00
H'FFF9
Interrupt priority register B
IPRB
R/W
H'00
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
77
5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
—
RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAM enable
Reserved bit
Standby timer
select 2 to 0
Software standby
NMI edge select
Selects the NMI input edge
User bit enable
Selects whether to use CCR bit 6
as a user bit or interrupt mask bit
78
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE
Description
0
UI bit in CCR is used as interrupt mask bit
1
UI bit in CCR is used as user bit
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2
NMIEG
Description
0
Interrupt is requested at falling edge of NMI input
1
Interrupt is requested at rising edge of NMI input
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)
IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
79
(Initial value)
Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
7
6
5
4
3
2
1
0
IPRA7
IPRA6
IPRA5
IPRA4
IPRA3
IPRA2
IPRA1
IPRA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Priority
level A0
Selects the
priority level
of ITU
channel 2
interrupt
requests
Priority level A1
Selects the priority level
of ITU channel 1
interrupt requests
Priority level A2
Selects the priority level of
ITU channel 0 interrupt requests
Priority level A3
Selects the priority level of WDT
interrupt requests
Priority level A4
Selects the priority level of IRQ4
interrupt requests
Priority level A5
Selects the priority level of IRQ 2 and IRQ 3 interrupt requests
Priority level A6
Selects the priority level of IRQ1 interrupt requests
Priority level A7
Selects the priority level of IRQ 0 interrupt requests
IPRA is initialized to H'00 by a reset and in hardware standby mode.
80
Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests.
Bit 7
IPRA7
Description
0
IRQ0 interrupt requests have priority level 0 (low priority)
1
IRQ0 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests.
Bit 6
IPRA6
Description
0
IRQ1 interrupt requests have priority level 0 (low priority)
1
IRQ1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 5—Priority Level A5 (IPRA5): Selects the priority level of IRQ2 and IRQ3 interrupt
requests.
Bit 5
IPRA5
Description
0
IRQ2 and IRQ3 interrupt requests have priority level 0 (low priority)
1
IRQ2 and IRQ3 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ4 interrupt requests.
Bit 4
IPRA4
Description
0
IRQ4 interrupt requests have priority level 0 (low priority)
1
IRQ4 interrupt requests have priority level 1 (high priority)
81
(Initial value)
Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT interrupt requests.
Bit 3
IPRA3
Description
0
WDT interrupt requests have priority level 0 (low priority)
1
WDT interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests.
Bit 2
IPRA2
Description
0
ITU channel 0 interrupt requests have priority level 0 (low priority)
1
ITU channel 0 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 1—Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests.
Bit 1
IPRA1
Description
0
ITU channel 1 interrupt requests have priority level 0 (low priority)
1
ITU channel 1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 0—Priority Level A0 (IPRA0): Selects the priority level of ITU channel 2 interrupt requests.
Bit 0
IPRA0
Description
0
ITU channel 2 interrupt requests have priority level 0 (low priority)
1
ITU channel 2 interrupt requests have priority level 1 (high priority)
82
(Initial value)
Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
7
6
5
4
3
2
1
0
IPRB7
IPRB6
—
—
IPRB3
—
IPRB1
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bit
Priority level B1
Selects the priority level
of A/D converter
interrupt request
Reserved bit
Priority level B3
Selects the priority level of SCI
channel 0 interrupt requests
Reserved bits
Priority level B6
Selects the priority level of ITU channel 4 interrupt requests
Priority level B7
Selects the priority level of ITU channel 3 interrupt requests
IPRB is initialized to H'00 by a reset and in hardware standby mode.
83
Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests.
Bit 7
IPRB7
Description
0
ITU channel 3 interrupt requests have priority level 0 (low priority)
1
ITU channel 3 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 6—Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests.
Bit 6
IPRB6
Description
0
ITU channel 4 interrupt requests have priority level 0 (low priority)
1
ITU channel 4 interrupt requests have priority level 1 (high priority)
(Initial value)
Bits 5 and 4—Reserved: These bits can be written and read, but it does not affect interrupt
priority.
Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI interrupt requests.
Bit 3
IPRB3
Description
0
SCI interrupt requests have priority level 0 (low priority)
1
SCI interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 2—Reserved: This bit can be written and read, but it does not affect interrupt priority.
Bit 1—Priority Level B1 (IPRB1): Selects the priority level of A/D converter interrupt requests.
Bit 1
IPRB1
Description
0
A/D converter interrupt requests have priority level 0 (low priority)
1
A/D converter interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 0—Reserved: This bit can be written and read, but it does not affect interrupt priority.
84
5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ4 interrupt
requests.
Bit
7
6
5
4
3
2
1
0
—
—
—
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Reserved bits
IRQ 4 to IRQ0 flags
These bits indicate IRQ4 to IRQ0
interrupt request status
Note: * Only 0 can be written, to clear flags.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 0.
Bits 4 to 0—IRQ4 to IRQ0 Flags (IRQ4F to IRQ0F): These bits indicate the status of IRQ4 to
IRQ0 interrupt requests.
Bits 4 to 0
IRQ4F to IRQ0F
Description
0
[Clearing conditions]
(Initial value)
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
1
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 4 to 0
85
5.2.4 IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ0 to IRQ4 interrupt requests.
Bit
7
6
5
4
3
2
1
0
—
—
—
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
IRQ 4 to IRQ0 enable
These bits enable or disable
IRQ4 to IRQ0 interrupts
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 5—Reserved: These bits can be written and read, but they do not enable or disable
interrupts.
Bits 4 to 0—IRQ4 to IRQ0 Enable (IRQ7E to IRQ0E): These bits enable or disable IRQ4 to
IRQ0 interrupts.
Bits 4 to 0
IRQ4E to IRQ0E
Description
0
IRQ4 to IRQ0 interrupts are disabled
1
IRQ4 to IRQ0 interrupts are enabled
86
(Initial value)
5.2.5 IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs at pins IRQ4 to IRQ0.
Bit
7
6
5
—
—
—
4
3
2
1
0
IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bit
IRQ 4 to IRQ0 sense control
These bits select level sensing or falling-edge
sensing for IRQ4 to IRQ0 interrupts
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 5—Reserved: These bits can be written and read, but they do not select level or fallingedge sensing.
Bits 4 to 0—IRQ4 to IRQ0 Sense Control (IRQ4SC to IRQ0SC): These bits selects whether
interrupts IRQ4 to IRQ0 are requested by level sensing of pins IRQ4 to IRQ0, or by falling-edge
sensing.
Bits 4 to 0
IRQ4SC to IRQ0SC
Description
0
Interrupts are requested when IRQ4 to IRQ0 inputs are low
1
Interrupts are requested by falling-edge input at IRQ4 to IRQ0
87
(Initial value)
5.3 Interrupt Sources
The interrupt sources include external interrupts (NMI, IRQ0 to IRQ4) and 21 internal interrupts.
5.3.1 External Interrupts
There are six external interrupts: NMI, and IRQ0 to IRQ4. Of these, NMI, IRQ0, IRQ1, and IRQ2
can be used to exit software standby mode.
NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the
I and UI bits in CCR. The NMIEG bit in SYSCR selects whether an interrupt is requested by the
rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector
number 7.
IRQ0 to IRQ4 Interrupts: These interrupts are requested by input signals at pins IRQ0 to IRQ4.
The IRQ0 to IRQ4 interrupts have the following features.
•
ISCR settings can select whether an interrupt is requested by the low level of the input at pins
IRQ0 to IRQ4, or by the falling edge.
•
IER settings can enable or disable the IRQ0 to IRQ4 interrupts. Interrupt priority levels can be
assigned by four bits in IPRA (IPRA7 to IPRA4).
•
The status of IRQ0 to IRQ4 interrupt requests is indicated in ISR. The ISR flags can be
cleared to 0 by software.
Figure 5-2 shows a block diagram of interrupts IRQ0 to IRQ4.
IRQnSC
IRQnE
IRQnF
Edge/level
sense circuit
S
Q
R
IRQn input
Clear signal
Note: n = 4 to 0
Figure 5-2 Block Diagram of Interrupts IRQ0 to IRQ4
88
IRQn interrupt
request
Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF).
ø
IRQn
input pin
IRQnF
Figure 5-3 Timing of Setting of IRQnF
Interrupts IRQ0 to IRQ4 have vector numbers 12 to 16. These interrupts are detected regardless of
whether the corresponding pin is set for input or output. When using a pin for external interrupt
input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, or SCI
input or output.
5.3.2 Internal Interrupts
Twenty-one internal interrupts are requested from the on-chip supporting modules.
•
Each on-chip supporting module has status flags for indicating interrupt status, and enable
bits for enabling or disabling interrupts.
•
Interrupt priority levels can be assigned in IPRA and IPRB.
5.3.3 Interrupt Vector Table
Table 5-3 lists the interrupt sources, their vector addresses, and their default priority order. In the
default priority order, smaller vector numbers have higher priority. The priority of interrupts other
than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order
shown in table 5-3.
89
Table 5-3 Interrupt Sources, Vector Addresses, and Priority
Vector Address*
Interrupt Source
Origin
Vector
Number
Advanced Mode
Normal Mode
NMI
External pins
7
H'001C to H'001F
H'000E to H'000F —
IRQ0
12
H'0030 to H'0033
H'0018 to H'0019
IRQ1
13
H'0034 to H0037
H'001A to H'001B IPRA6
IRQ2
14
H'0038 to H'003B
H'001C to H'001D IPRA5
IRQ3
15
H'003C to H'003F
H'001E to H'001F
IRQ4
Reserved
—
16
H'0040 to H'0043
H'0020 to H'0021
17
H'0044 to H'0047
H'0022 to H'0023
18
H'0048 to H'004B
H'0024 to H'0025
19
H'004C to H'004F
H'0026 to H'0027
WOVI (interval timer)
Watchdog timer 20
H'0050 to H'0053
H'0028 to H'0029
Reserved
—
21
H'0054 to H'0057
H'002A to H'002B
22
H'0058 to H'005B
H'002C to H'002D
23
H'005C to H'005F
H'002E to H'002F
24
H'0060 to H'0063
H'0030 to H'0031
25
H'0064 to H'0067
H'0032 to H'0033
IMIA0 (compare match/
input capture A0)
ITU channel 0
IMIB0 (compare match/
input capture B0)
OVI0 (overflow 0)
26
H'0068 to H'006B
H'0034 to H'0035
Reserved
—
27
H'006C to H'006F
H'0036 to H'0037
IMIA1 (compare match/
input capture A1)
ITU channel 1
28
H'0070 to H'0073
H'0038 to H'0039
29
H'0074 to H'0077
H'003A to H'003B
IMIB1 (compare match/
input capture B1)
OVI1 (overflow 1)
30
H'0078 to H'007B
H'003C to H'003D
Reserved
—
31
H'007C to H'007F
H'003E to H'003F
IMIA2 (compare match/
input capture A2)
ITU channel 2
32
H'0080 to H'0083
H'0040 to H'0041
33
H'0084 to H'0087
H'0042 to H'0043
IMIB2 (compare match/
input capture B2)
OVI2 (overflow 2)
Reserved
—
34
H'0088 to H'008B
H'0044 to H'0045
35
H'008C to H'008F
H'0046 to H'0047
Note: * Lower 16 bits of the address.
90
IPR
IPRA7
IPRA4
IPRA3
IPRA2
IPRA1
IPRA0
Priority
High
Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont)
Vector Address*
Interrupt Source
Origin
Vector
Number
Advanced Mode
Normal Mode
IPR
IMIA3 (compare match/
input capture A3)
ITU channel 3
36
H'0090 to H'0093
H'0048 to H'0049
IPRB7
IMIB3 (compare match/
input capture B3)
37
H'0094 to H'0097
H'004A to H'004B
OVI3 (overflow 3)
38
H'0098 to H'009B
H'004C to H'004D
Reserved
—
39
H'009C to H'009F
H'004E to H'004F
IMIA4 (compare match/
input capture A4)
ITU channel 4
40
H'00A0 to H'00A3
H'0050 to H'0051
IMIB4 (compare match/
input capture B4)
41
H'00A4 to H'00A7
H'0052 to H'0053
OVI4 (overflow 4)
42
H'00A8 to H'00AB
H'0054 to H'0055
Reserved
—
43
H'00AC to H'00AF H'0056 to H'0057
Reserved
—
44
H'00B0 to H'00B3
H'0058 to H'0059
45
H'00B4 to H'00B7
H'005A to H'005B
46
H'00B8 to H'00BB
H'005C to H'005D
47
H'00BC to H'00BF H'005E to H'005F
48
H'00C0 to H'00C3
H'0060 to H'0061
49
H'00C4 to H'00C7
H'0062 to H'0063
50
H'00C8 to H'00CB H'0064 to H'0065
51
H'00CC to H'00CF H'0066 to H'0067
52
H'00D0 to H'00D3
H'0068 to H'0069
RXI0 (receive data
full)
53
H'00D4 to H'00D7
H'006A to H'006B
TXI0 (transmit data
empty)
54
H'00D8 to H'00DB H'006C to H'006D
ERI0 (receive error)
SCI
TEI0 (transmit end)
Reserved
ADI (A/D end)
—
A/D
55
H'00DC to H'00DF H'006E to H'006F
56
H'00E0 to H'00E3
H'0070 to H'0071
57
H'00E4 to H'00E7
H'0072 to H'0073
58
H'00E8 to H'00EB
H'0074 to H'0075
59
H'00EC to H'00EF H'0076 to H'0077
60
H'00F0 to H'00F3
Note: * Lower 16 bits of the address.
91
H'0078 to H'0079
Priority
IPRB6
—
IPRB3
IPRB2
IPRB1 Low
5.4 Interrupt Operation
5.4.1 Interrupt Handling Process
The H8/3032 Series handles interrupts differently depending on the setting of the UE bit. When
UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and
UI bits. Table 5-4 indicates how interrupts are handled for all setting combinations of the UE, I,
and UI bits.
NMI interrupts are always accepted except in the reset and hardware standby states. IRQ
interrupts and interrupts from the on-chip supporting modules have their own enable bits.
Interrupt requests are ignored when the enable bits are cleared to 0.
Table 5-4 UE, I, and UI Bit Settings and Interrupt Handling
SYSCR
CCR
UE
I
UI
Description
1
0
—
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1
—
No interrupts are accepted except NMI.
0
—
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
1
0
NMI and interrupts with priority level 1 are accepted.
1
No interrupts are accepted except NMI.
0
UE = 1: Interrupts IRQ0 to IRQ4 and interrupts from the on-chip supporting modules can all be
masked by the I bit in the CPU’s CCR. Interrupts are masked when the I bit is set to 1, and
unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority.
Figure 5-4 is a flowchart showing how interrupts are accepted when UE = 1.
92
Program execution state
No
Interrupt requested?
Yes
Yes
NMI
No
No
Pending
Priority level 1?
Yes
IRQ 0
No
Yes
IRQ 1
IRQ 0
No
Yes
No
IRQ 1
Yes
No
Yes
ADI
ADI
Yes
Yes
No
I=0
Yes
Save PC and CCR
I ←1
Read vector address
Branch to interrupt
service routine
Figure 5-4 Process Up to Interrupt Acceptance when UE = 1
93
•
If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
•
When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests
pending. If two or more interrupts with the same IPR setting are requested simultaneously, the
interrupt controller follows the priority order shown in table 5-3.
•
The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt
request is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are
held pending.
•
When an interrupt request is accepted, interrupt exception handling starts after execution of
the current instruction has been completed.
•
In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from
the interrupt service routine.
•
Next the I bit is set to 1 in CCR, masking all interrupts except NMI.
•
The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
UE = 0: The I and UI bits in the CPU’s CCR and the IPR bits enable three-level masking of IRQ0
to IRQ4 interrupts and interrupts from the on-chip supporting modules.
•
Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked
when the I bit is cleared to 0.
•
Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1,
and are unmasked when either the I bit or the UI bit is cleared to 0.
For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to
H'20, and IPRB is set to H'00 (giving IRQ2 and IRQ3 interrupt requests priority over other
interrupts), interrupts are masked as follows:
a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ2 > IRQ3 >IRQ0 …).
b. If I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 are unmasked.
c. If I = 1 and UI = 1, all interrupts are masked except NMI.
94
Figure 5-5 shows the transitions among the above states.
I←0
a. All interrupts are
unmasked
I←0
b. Only NMI, IRQ 2 , and
IRQ 3 are unmasked
I ← 1, UI ← 0
Exception handling,
or I ← 1, UI ← 1
UI ← 0
Exception handling,
or UI ← 1
c. All interrupts are
masked except NMI
Figure 5-5 Interrupt Masking State Transitions (Example)
Figure 5-6 is a flowchart showing how interrupts are accepted when UE = 0.
•
If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
•
When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests
pending. If two or more interrupts with the same IPR setting are requested simultaneously, the
interrupt controller follows the priority order shown in table 5-3.
•
The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt
request is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set
to 1 and the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted;
interrupt requests with priority level 0 are held pending. If the I bit and UI bit are both set to
1, only NMI is accepted; all other interrupt requests are held pending.
•
When an interrupt request is accepted, interrupt exception handling starts after execution of
the current instruction has been completed.
•
In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
saved indicates the address of the first instruction that will be executed after the return from
the interrupt service routine.
•
The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.
•
The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
95
Program execution state
No
Interrupt requested?
Yes
Yes
NMI
No
No
Pending
Priority level 1?
Yes
IRQ 0
No
IRQ 0
Yes
IRQ 1
No
Yes
No
IRQ 1
Yes
No
Yes
ADI
ADI
Yes
Yes
No
I=0
No
I=0
Yes
Yes
No
UI = 0
Yes
Save PC and CCR
I ← 1, UI ← 1
Read vector address
Branch to interrupt
service routine
Figure 5-6 Process Up to Interrupt Acceptance when UE = 0
96
Instruction Internal
prefetch
processing
Stack
Vector fetch
Prefetch of
interrupt
Internal
service routine
processing instruction
ø
Interrupt
request
signal
A19 to A 0
(1)
(3)
(5)
(7)
(9)
(11)
(13)
Internal
read signal
Internal
write signal
On-chip
data
(1)
High
(2)
(4)
Instruction prefetch address (not executed;
return address, same as PC contents)
(2), (4) Instruction code (not executed)
(3)
Instruction prefetch address (not executed)
(5)
SP – 2
(7)
SP – 4
(6)
(8)
(10)
(12)
(14)
(6), (8)
PC and CCR saved to stack
(9), (11) Vector address
(10), (12) Starting address of interrupt service routine (contents of
vector address)
(13)
Starting address of interrupt service routine; (13) = (10), (12)
(14)
First instruction of interrupt service routine
Note: Mode 1, with program code and stack in on-chip memory area.
5.4.2 Interrupt Sequence
97
Figure 5-7 Interrupt Sequence (Mode 2, Stack in External Memory)
Interrupt level
decision and wait
for end of instruction
Figure 5-7 shows the interrupt sequence in mode 1 when the program code and stack are in an
on-chip memory area.
Interrupt accepted
5.4.3 Interrupt Response Time
Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until
the first instruction of the interrupt service routine is executed.
Table 5-5 Interrupt Response Time
External Memory
8-Bit Bus
Item
On-Chip
Memory
2 States
3 States
1
Interrupt priority decision
2*1
2*1
2*1
2
Maximum number of states
until end of current instruction
1 to 23
1 to 27
1 to 31*4
3
Saving PC and CCR to stack
4
8
12*4
4
Vector fetch
4
8
12*4
5
Instruction prefetch*2
4
8
12*4
6
Internal processing*3
4
4
4
19 to 41
31 to 57
43 to 73
No.
Total
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt
service routine.
3. Internal processing after the interrupt is accepted and internal processing after prefetch.
4. The number of states increases if wait states are inserted in external memory access.
98
5.5 Usage Notes
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction
When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not
disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR,
MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant
when execution of the instruction ends the interrupt is still enabled, so its interrupt exception
handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception
handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.
This also applies to the clearing of an interrupt flag.
Figure 5-8 shows an example in which an IMIEA bit is cleared to 0 in the ITU.
TIER write cycle by CPU
IMIA exception handling
ø
Internal
address bus
TIER address
Internal
write signal
IMIEA
IMIA
IMFA interrupt
signal
Figure 5-8 Contention between Interrupt and Interrupt-Disabling Instruction
This type of contention will not occur if the interrupt is masked when the interrupt enable bit or
flag is cleared to 0.
99
5.5.2 Instructions that Inhibit Interrupts
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs,
after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the
CPU is currently executing one of these interrupt-inhibiting instructions, however, when the
instruction is completed the CPU always continues by executing the next instruction.
5.5.3 Interrupts during EEPMOV Instruction Execution
The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.
When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the
transfer is completed, not even NMI.
When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at
a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.
Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
100
Section 6 Bus Controller
6.1 Overview
The H8/3032 Series has an on-chip bus controller that divides the external address space into eight
areas and can assign different bus specifications to each. This enables different types of memory
to be connected easily.
A bus arbitration function of the bus controller controls the operation of the DMA controller
(DMAC) and refresh controller. The bus controller can also release the bus to an external device.
6.1.1 Features
Features of the bus controller are listed below.
•
Independent settings for address areas 0 to 7
— 128-kbyte areas in 1-Mbyte mode.
— Areas can be designated for two-state or three-state access.
•
Four wait modes
— Programmable wait mode, pin auto-wait mode, and pin wait modes 0 and 1 can be
selected.
— Zero to three wait states can be inserted automatically.
101
6.1.2 Block Diagram
Figure 6-1 shows a block diagram of the bus controller.
ASTCR
Area
decoder
WCER
Bus control
circuit
WAIT
Internal signals
Internal data bus
Internal
address bus
Access state control signal
Wait request signal
Wait-state
controller
WCR
Legend
ASTCR: Access state control register
WCER: Wait state controller enable register
WCR:
Wait control register
Figure 6-1 Block Diagram of Bus Controller
102
6.1.3 Input/Output Pins
Table 6-1 summarizes the bus controller’s input/output pins.
Table 6-1 Bus Controller Pins
Name
Abbreviation
I/O
Function
Address strobe
AS
Output
Strobe signal indicating valid address output on the
address bus
Read
RD
Output
Strobe signal indicating reading from the external
address space
Write
WR
Output
Strobe signal indicating writing to the external
address space, with valid data on the data bus
Wait
WAIT
Input
Wait request signal for access to external threestate-access areas
6.1.4 Register Configuration
Table 6-2 summarizes the bus controller’s registers.
Table 6-2 Bus Controller Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFED
Access state control register
ASTCR
R/W
H'FF
H'FFEE
Wait control register
WCR
R/W
H'F3
H'FFEF
Wait state controller enable register
WCER
R/W
H'FF
Note: * Lower 16 bits of the address.
103
6.2 Register Descriptions
6.2.1 Access State Control Register (ASTCR)
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
Bit
7
6
5
4
3
2
1
0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits selecting number of states for access to each area
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0
AST7 to AST0
Description
0
Areas 7 to 0 are accessed in two states
1
Areas 7 to 0 are accessed in three states
(Initial value)
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
registers are accessed in a fixed number of states that does not depend on ASTCR settings.
104
6.2.2 Wait Control Register (WCR)
WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller
(WSC) and specifies the number of wait states.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
WMS1
WMS2
WC1
WC0
Initial value
1
1
1
1
0
0
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Wait count 1/0
These bits select the
number of wait states
inserted
Wait mode select 1/0
These bits select the wait mode
WCR is initialized to H'F3 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode.
Bit 3
WMS1
Bit 2
WMS0
Description
0
0
Programmable wait mode
1
No wait states inserted by wait-state controller
0
Pin wait mode 1
1
Pin auto-wait mode
1
(Initial value)
105
Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted
in access to external three-state-access areas.
Bit 1
WC1
Bit 0
WC0
Description
0
0
No wait states inserted by wait-state controller
1
1 state inserted
0
2 states inserted
1
3 states inserted
1
(Initial value)
6.2.3 Wait State Controller Enable Register (WCER)
WCER is an 8-bit readable/writable register that enables or disables wait-state control of external
three-state-access areas by the wait-state controller.
Bit
7
6
5
4
3
2
1
0
WCE7
WCE6
WCE5
WCE4
WCE3
WCE2
WCE1
WCE0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Wait state controller enable 7 to 0
These bits enable or disable wait-state control
WCER is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Wait-State Controller Enable 7 to 0 (WCE7 to WCE0): These bits enable or
disable wait-state control of external three-state-access areas.
Bits 7 to 0
WCE7 to WCE0
Description
0
Wait-state control disabled (pin wait mode 0)
1
Wait-state control enabled
(Initial value)
106
6.3 Operation
6.3.1 Area Division
The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the
1-Mbyte mode. Figure 6-2 shows a general view of the memory map.
H'00000
On-chip ROM*1
H'1FFFF
Area 0 (128 kbytes)
H'20000
Area 1 (128 kbytes)
H'3FFFF
H'40000
Area 2 (128 kbytes)
H'5FFFF
H'60000
Area 3 (128 kbytes)
H'7FFFF
H'80000
Area 4 (128 kbytes)
H'9FFFF
H'A0000
Area 5 (128 kbytes)
H'BFFFF
H'C0000
Area 6 (128 kbytes)
H'DFFFF
H'E0000
Area 7 (128 kbytes)
On-chip RAM*1, *2
External address space*3
H'FFFFF
On-chip I/O registers*1
1-Mbyte mode (mode 1)
Notes: There is no area division in modes 2 and 3.
1. The number of access states to on-chip ROM, on-chip RAM, and on-chip I/O registers is fixed.
2. This area follows area 7 specifications when the RAME bit in SYSCR is 0.
3. This area follows area 7 specifications.
Figure 6-2 Access Area Map
107
The bus specifications for each area can be selected in ASTCR, WCER, and WCR as shown in
table 6-3.
Table 6-3 Bus Specifications
ASTCR
WCER
WCR
ASTn
WCEn
WMS1
WMS0
Bus
Width
Access
States
Wait Mode
0
—
—
—
8
2
Disabled
1
0
—
—
8
3
Pin wait mode 0
1
0
0
8
3
Programmable wait mode
1
8
3
Disabled
0
8
3
Pin wait mode 1
1
8
3
Pin auto-wait mode
1
Bus Specifications
Note: n = 0 to 7
108
6.3.2 Bus Control Signal Timing
8-Bit, Three-State-Access Areas: Figure 6-3 shows the timing of bus control signals for an 8-bit,
three-state-access area. Wait states can be inserted.
Bus cycle
T2
T1
T3
ø
Address bus
External address
AS
RD
Read
access
Valid
D7 to D0
WR
Write
access
Valid
D7 to D0
Figure 6-3 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
109
8-Bit, Two-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit,
two-state-access area. Wait status cannot be inserted.
Bus cycle
T1
T2
ø
Address bus
External address
AS
RD
Read
access
D7 to D0
Valid
WR
Write
access
D7 to D0
Valid
Figure 6-4 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
110
6.3.3 Wait Modes
Four wait modes can be selected for each area as shown in table 6-4.
Table 6-4 Wait Mode Selection
ASTCR
WCER
WCR
ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control
Wait Mode
0
—
—
—
Disabled
No wait states
1
0
—
—
Disabled
Pin wait mode 0
1
0
0
Enabled
Programmable wait mode
1
Enabled
No wait states
0
Enabled
Pin wait mode 1
1
Enabled
Pin auto-wait mode
1
Note: n = 7 to 0
The ASTn and WCEn bits can be set independently for each area. Bits WMS1 and WMS0 apply
to all areas. All areas for which WSC control is enabled operate in the same wait mode.
111
Pin Wait Mode 0: The wait state controller is disabled. Wait states can only be inserted by WAIT
pin control. During access to an external three-state-access area, if the WAIT pin is low at the fall
of the system clock (ø) in the T2 state, a wait state (TW) is inserted. If the WAIT pin remains low,
wait states continue to be inserted until the WAIT signal goes high. Figure 6-5 shows the timing.
Inserted by WAIT signal
T1
ø
T2
TW
*
*
TW
T3
*
WAIT pin
Address bus
External address
AS
RD
Read
access
Read data
Data bus
WR
Write
access
Data bus
Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6-5 Pin Wait Mode 0
112
Pin Wait Mode 1: In all accesses to external three-state-access areas, the number of wait states
(TW) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system
clock (ø) in the last of these wait states, an additional wait state is inserted. If the WAIT pin
remains low, wait states continue to be inserted until the WAIT signal goes high.
Pin wait mode 1 is useful for inserting four or more wait states, or for inserting different numbers
of wait states for different external devices.
If the wait count is 0, this mode operates in the same way as pin wait mode 0.
Figure 6-6 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional
wait state is inserted by WAIT input.
T1
Inserted by
wait count
Inserted by
WAIT signal
TW
TW
T2
ø
*
T3
*
WAIT pin
Address bus
External address
AS
Read
access
RD
Read data
Data bus
WR
Write
access
Data bus
Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6-6 Pin Wait Mode 1
113
Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (TW) selected by bits
WC1 and WC0 are inserted.
In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the T2 state,
the number of wait states (TW) selected by bits WC1 and WC0 are inserted. No additional wait
states are inserted even if the WAIT pin remains low.
Figure 6-7 shows the timing when the wait count is 1.
T1
ø
T2
T3
*
T1
T2
TW
T3
*
WAIT
Address bus
External address
External address
AS
RD
Read
access
Read data
Read data
Data bus
WR
Write
access
Data bus
Write data
Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6-7 Pin Auto-Wait Mode
114
Programmable Wait Mode: The number of wait states (TW) selected by bits WC1 and WC0 are
inserted in all accesses to external three-state-access areas. Figure 6-8 shows the timing when the
wait count is 1 (WC1 = 0, WC0 = 1).
T1
T2
TW
T3
ø
Address bus
External address
AS
RD
Read
access
Read data
Data bus
WR
Write
access
Write data
Data bus
Figure 6-8 Programmable Wait Mode
115
Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and
WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can
select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings.
Figure 6-9 shows an example of wait mode settings.
Area 0
3-state-access area,
programmable wait mode
Area 1
3-state-access area,
programmable wait mode
Area 2
3-state-access area,
pin wait mode 0
Area 3
3-state-access area,
pin wait mode 0
Area 4
2-state-access area,
no wait states inserted
Area 5
2-state-access area,
no wait states inserted
Area 6
2-state-access area,
no wait states inserted
Area 7
2-state-access area,
no wait states inserted
Bit:
ASTCR H'0F:
7
0
6
0
5
0
4
0
3
1
2
1
1
1
0
1
WCER H'33:
0
0
1
1
0
0
1
1
WCR H'F3:
—
—
—
—
0
0
1
1
Note: Wait states cannot be inserted in areas designated for two-state access by ASTCR.
Figure 6-9 Wait Mode Settings (Example)
116
6.3.4 Interconnections with Memory (Example)
For each area, the bus controller can select two- or three-state access. In three-state-access areas,
wait states can be inserted in a variety of modes, simplifying the connection of both high-speed
and low-speed devices.
Figure 6-10 shows an example of interconnections between the H8/3032 Series and memory.
Figure 6-10 shows a memory map for this example.
A 32-kword × 8-bit EPROM is connected to area 0. This device is accessed in three states via a 8bit bus.
Two 32-kword × 8-bit SRAM devices (SRAM1 and SRAM2) are connected to area 1. These
devices are accessed in two states via a 8-bit bus.
One 32-kword × 8-bit SRAM (SRAM3) is connected to area 7. This device is accessed via an
8-bit bus, using three-state access with an additional wait state inserted in pin auto-wait mode.
H'00000
On-chip ROM
H'0FFFF
H'10000
H'17FFF
H'18000
Area 0
8-bit, three-state-access area
EPROM
Not used
H'1FFFF
H'20000
SRAM1, 2
Area 1
8-bit, two-state-access area
H'2FFFF
H'30000
Not used
H'3FFFF
H'E0000
Area 7
8-bit, three-state-access area
(one auto-wait state)
SRAM3
H'E7FFF
Not used
On-chip RAM
H'FFFFF
On-chip I/O registers
Note: The bus width and the number of access states of the on-chip memories and registers
are fixed; they cannot be changed by register setting.
Figure 6-10 Memory Map (Example)
117
6.4 Usage Notes
6.4.1 Register Write Timing
ASTCR and WCER Write Timing: Data written to ASTCR or WCER takes effect starting from
the next bus cycle. Figure 6-11 shows the timing when an instruction fetched from area 0 changes
area 0 from three-state access to two-state access.
T1
T2
T3
T1
T2
T3
T1
T2
ø
ASTCR address
Address
3-state access to area 0
2-state access
to area 0
Figure 6-11 ASTCR Write Timing
118
Section 7 I/O Ports
7.1 Overview
The H8/3032 Series has nine input/output ports (ports 1, 2, 3, 5, 6, 8, 9, A, and B) and one input
port (port 7). Table 7-1 summarizes the port functions. The pins in each port are multiplexed as
shown in table 7-1.
Each port has a data direction register (DDR) for selecting input or output, and a data register (DR)
for storing output data. In addition to these registers, ports 2, and 5 have an input pull-up control
register (PCR) for switching input pull-up transistors on and off.
Ports 1 to 3 and ports 5, 6, and 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A,
and B can drive one TTL load and a 30-pF capacitive load. Ports 1 to 3 and ports 5, 6, 8, 9, A, and
B can drive a darlington pair. Ports 1, 2, 5, and B can drive LEDs (with 10-mA current sink). Pins
P82 to P80, PA7 to PA0, and PB3 to PB0 have Schmitt-trigger input circuits.
For block diagrams of the ports see appendix C, I/O Port Block Diagrams.
119
Table 7-1 Port Functions (1)
Port
Description
Pins
Mode 1
Mode 2
Port 1
• 8-bit I/O port
• Can drive LEDs
P17 to P10/
A7 to A0
Address output (A7 to
A0) and generic input
DDR = 0:
generic input
DDR = 1:
address output
Generic input/output
Mode 3
Port 2
• 8-bit I/O port
• Input pull-up
• Can drive LEDs
P27 to P20/
A15 to A8
Address output (A15 to
A8) and generic input
DDR = 0:
generic input
DDR = 1:
address output
Generic input/output
Port 3
• 8-bit I/O port
P37 to P30/
D7 to D0
Data input/output (D15
to D8)
Generic input/output
Port 5
• 4-bit I/O port
• Input pull-up
• Can drive LEDs
P53 to P50/
A19 to A16
Address output (A19 to
A16) and generic input
DDR = 0:
generic input
DDR = 1:
address output
Generic input/output
Port 6
• 4-bit I/O port
P65/WR,
P64/RD,
P63/AS
Bus control signal
output (WR, RD, AS)
Generic input/output
P60/WAIT
Bus control signal
output (WAIT) and
1-bit generic input/
output
Port 7
• 8-bit input port
P77 to P70/
AN7 to AN0
Analog input (AN7 to AN0) to A/D converter, and generic input
Port 8
• 4-bit I/O port
• P82 to P80 have
Schmitt inputs
P83/IRQ3,
P82/IRQ2,
P81/IRQ1
P80/IRQ0
IRQ3 to IRQ0 input and 4-bit generic input/output
Port 9
• 3-bit I/O port
P94/SCK/IRQ4
Input and output (SCK) for serial communication interface
(SCI), IRQ4 input, and 1-bit generic input/output
P92/RxD,
P90/TxD
Input and output (RxD and Txd) for SCI and 2-bit generic
input/output
120
Table 7-1 Port Functions (1)
Port
Pins
Mode 1
Port A • 8-bit I/O port
• Schmitt inputs
Description
PA7/TP7/TIOCB2/,
PA6/TP6/TIOCA2,
PA5/TP5/TIOCB1,
PA4/TP4//TIOCA1,
PA3/TP3/TIOCB0/
TCLKD,
PA2/TP2/TIOCA0/
TCLKC,
PA1/TP1/TCLKB,
PA0/TP0/TCLKA
TPC output (TP8 to TP0), ITU input and output (TCLKD,
TCLKC, TCLKB, TCLKA, TIOCB2, TIOCA2, TIOCB1, TIOCA1),
and generic input/output
Port B • 8-bit I/O port
• Can drive LEDs
• PB3 to PB0
have Schmitt
inputs
PB7/TP15/ADTRG,
TPC output (TP15), trigger input (ADTRG) to A/D converter,
and 1-bit generic input/output
PB6/TP14
TPC output (TP14) and 1-bit generic input/output
PB5/TP13/TOCXB4,
PB4/TP12/TOCXA4,
PB3/TP11/TIOCB4,
PB2/TP10/TIOCA4,
PB1/TP9/TIOCB3,
PB0/TP8/TIOCA3
TPC output (TP13 to TP8), ITU input and output (TOCXB4,
TOCXA4, TIOCB4, TIOCA4, TIOCB3, TIOCA3), and TOCXA4,
TIOCB4, TIOCA4, TIOCB3, TIOCA3), and 6-bit generic
input/output
121
Mode 2
Mode 3
7.2 Port 1
7.2.1 Overview
Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7-1. The pin functions
differ depending on the operating mode. In mode 1, they are address bus output pins (A7 to A0).
In modes 2 and 3, port 1 is a generic input/output port.
Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington
transistor pair.
Port 1 pins
Port 1
Modes 1
Modes 2 and 3
P17 /A 7
P17 (input)/A 7 (output)
P17 (input/output)
P16 /A 6
P16 (input)/A 6 (output)
P16 (input/output)
P15 /A 5
P15 (input)/A 5 (output)
P15 (input/output)
P14 /A 4
P14 (input)/A 4 (output)
P14 (input/output)
P13 /A 3
P13 (input)/A 3 (output)
P13 (input/output)
P12 /A 2
P12 (input)/A 2 (output)
P12 (input/output)
P11 /A 1
P11 (input)/A 1 (output)
P11 (input/output)
P10 /A 0
P10 (input)/A 0 (output)
P10 (input/output)
Figure 7-1 Port 1 Pin Configuration
122
7.2.2 Register Descriptions
Table 7-2 summarizes the registers of port 1.
Table 7-2 Port 1 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFC0
Port 1 data direction register
P1DDR
W
H'00
H'FFC2
Port 1 data register
P1DR
R/W
H'00
Note: * Lower 16 bits of the address.
Port 1 Data Direction Register (P1DDR): P1DDR is an 8-bit write-only register that can select
input or output for each pin in port 1.
Bit
7
6
5
4
3
2
1
0
P1 7 DDR P1 6 DDR P1 5 DDR P1 4 DDR P1 3 DDR P1 2 DDR P1 1 DDR P1 0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 1 data direction 7 to 0
These bits select input or
output for port 1 pins
Mode 1: A pin in port 1 becomes an address output pin if the corresponding P1DDR bit is set to 1,
and a generic input pin if this bit is cleared to 0.
Modes 2 and 3 (Single-Chip Modes): Port 1 functions as an input/output port. A pin in port 1
becomes an output pin if the corresponding P1DDR bit is set to 1, and an input pin if this bit is
cleared to 0.
P1DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting. If a P1DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
123
Port 1 Data Register (P1DR): P1DR is an 8-bit readable/writable register that stores data for pins
P17 to P10.
Bit
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 1 data 7 to 0
These bits store data for port 1 pins
When a bit in P1DDR is set to 1, if port 1 is read the value of the corresponding P1DR bit is
returned directly, regardless of the actual state of the pin. When a bit in P1DDR is cleared to 0, if
port 1 is read the corresponding pin level is read.
P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
7.2.3 Pin Functions in Each Mode
The pin functions of port 1 differ between mode 1 and modes 2 and 3 (single-chip modes). The pin
functions in each mode are described below.
124
Mode 1: Address output or generic input can be selected for each pin in port 1. A pin becomes an
address output pin if the corresponding P1DDR bit is set to 1, and a generic input pin if this bit is
cleared to 0. Following a reset, all pins are input pins. To use a pin for address output, its P1DDR
bit must be set to 1. Figure 7-2 shows the pin functions in mode 1.
Port 1
When P1DDR = 1
When P1DDR = 0
A 7 (output)
P17 (input)
A 6 (output)
P16 (input)
A 5 (output)
P15 (input)
A 4 (output)
P14 (input)
A 3 (output)
P13 (input)
A 2 (output)
P12 (input)
A 1 (output)
P11 (input)
A 0 (output)
P10 (input)
Figure 7-2 Pin Functions in Mode 1 (Port 1)
Modes 2 and 3 (Single-Chip Modes): Input or output can be selected separately for each pin in
port 1. A pin becomes an output pin if the corresponding P1DDR bit is set to 1, and an input pin if
this bit is cleared to 0. Figure 7-3 shows the pin functions in modes 2 and 3.
P17 (input/output)
P16 (input/output)
P15 (input/output)
P14 (input/output)
Port 1
P13 (input/output)
P12 (input/output)
P11 (input/output)
P10 (input/output)
Figure 7-3 Pin Functions in Modes 2 and 3 (Port 1)
125
7.3 Port 2
7.3.1 Overview
Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7-4.
The pin functions differ depending on the operating mode. In mode 1, settings in the port 1 data
direction register (P1DDR) can designate pins for address bus output (A15 to A8) or generic input.
In modes 2 and 3, port 2 is a generic input/output port.
Port 2 has software-programmable built-in pull-up transistors. Pins in port 2 can drive one TTL
load and a 90-pF capacitive load. They can also drive a darlington transistor pair.
Port 2 pins
Port 2
Mode 1
Modes 2 and 3
P27 /A 15
P27 (input)/A15 (output)
P27 (input/output)
P26 /A 14
P26 (input)/A14 (output)
P26 (input/output)
P25 /A 13
P25 (input)/A13 (output)
P25 (input/output)
P24 /A 12
P24 (input)/A12 (output)
P24 (input/output)
P23 /A 11
P23 (input)/A11 (output)
P23 (input/output)
P22 /A 10
P22 (input)/A10 (output)
P22 (input/output)
P21 /A 9
P21 (input)/A9 (output)
P21 (input/output)
P20 /A 8
P20 (input)/A8 (output)
P20 (input/output)
Figure 7-4 Port 2 Pin Configuration
126
7.3.2 Register Descriptions
Table 7-3 summarizes the registers of port 2.
Table 7-3 Port 2 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFC1
Port 2 data direction register
P2DDR
W
H'00
H'FFC3
Port 2 data register
P2DR
R/W
H'00
H'FFD8
Port 2 input pull-up control register
P2PCR
R/W
H'00
Note: * Lower 16 bits of the address.
Port 2 Data Direction Register (P2DDR): P2DDR is an 8-bit write-only register that can select
input or output for each pin in port 2.
Bit
7
6
5
4
3
2
1
0
P2 7 DDR P2 6 DDR P2 5 DDR P2 4 DDR P2 3 DDR P2 2 DDR P2 1 DDR P2 0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 2 data direction 7 to 0
These bits select input or
output for port 2 pins
Mode 1: A pin in port 2 becomes an address output pin if the corresponding P2DDR bit is set to 1,
and a generic input pin if this bit is cleared to 0.
Modes 2 and 3: Port 2 functions as an input/output port. A pin in port 2 becomes an output pin if
the corresponding P2DDR bit is set to 1, and an input pin if this bit is cleared to 0.
P2DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting. If a P2DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
127
Port 2 Data Register (P2DR): P2DR is an 8-bit readable/writable register that stores data for pins
P27 to P20.
Bit
7
6
5
4
3
2
1
0
P2 7
P2 6
P2 5
P2 4
P2 3
P2 2
P2 1
P2 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 2 data 7 to 0
These bits store data for port 2 pins
When a bit in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is
returned directly, regardless of the actual state of the pin. When a bit in P2DDR is cleared to 0, if
port 2 is read the corresponding pin level is read.
P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 2 Input Pull-Up Control Register (P2PCR): P2PCR is an 8-bit readable/writable register
that controls the MOS input pull-up transistors in port 2.
Bit
7
6
5
4
3
2
1
0
P2 7 PCR P2 6 PCR P2 5 PCR P2 4 PCR P2 3 PCR P2 2 PCR P2 1 PCR P2 0 PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 2 input pull-up control 7 to 0
These bits control input pull-up
transistors built into port 2
When a P2DDR bit is cleared to 0 (selecting generic input), if the corresponding bit from P27PCR
to P20PCR is set to 1, the input pull-up transistor is turned on.
P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
7.3.3 Pin Functions in Each Mode
The pin functions of port 2 differ between mode 1 and modes 2 and 3. The pin functions in each
mode are described below.
128
Mode 1: Address output or generic input can be selected for each pin in port 2. A pin becomes an
address output pin if the corresponding P2DDR bit is set to 1, and a generic input pin if this bit is
cleared to 0. Following a reset, all pins are input pins. To use a pin for address output, its P2DDR
bit must be set to 1. Figure 7-5 shows the pin functions in mode 1.
Port 2
When P2DDR = 1
When P2DDR = 0
A 15 (output)
P27 (input)
A 14 (output)
P26 (input)
A 13 (output)
P25 (input)
A 12 (output)
P24 (input)
A 11 (output)
P23 (input)
A 10 (output)
P22 (input)
A 9 (output)
P21 (input)
A 8 (output)
P20 (input)
Figure 7-5 Pin Functions in Mode 1 (Port 2)
Modes 2 and 3: Input or output can be selected separately for each pin in port 2. A pin becomes an
output pin if the corresponding P2DDR bit is set to 1, and an input pin if this bit is cleared to 0.
Figure 7-6 shows the pin functions in modes 2 and 3.
P27 (input/output)
P26 (input/output)
P25 (input/output)
Port 2
P24 (input/output)
P23 (input/output)
P22 (input/output)
P21 (input/output)
P20 (input/output)
Figure 7-6 Pin Functions in Modes 2 and 3 (Port 2)
129
7.3.4 Input Pull-Up Transistors
Port 2 has built-in MOS input pull-up transistors that can be controlled by software. These input
pull-up transistors can be turned on and off individually.
When a P2PCR bit is set to 1 and the corresponding P2DDR bit is cleared to 0, the input pull-up
transistor is turned on.
The input pull-up transistors are turned off by a reset and in hardware standby mode. In software
standby mode they retain their previous state.
Table 7-4 summarizes the states of the input pull-up transistors in each mode.
Table 7-4 Input Pull-Up Transistor States (Port 2)
Mode
Reset
Hardware Standby Mode
Software Standby Mode
Other Modes
1
2
3
Off
Off
On/off
On/off
Legend
Off:
The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0. Otherwise, it is off.
130
7.4 Port 3
7.4.1 Overview
Port 3 is an 8-bit input/output port with the pin configuration shown in figure 7-7. Port 3 is a data
bus in mode 1 and a generic input/output port in modes 2 and 3.
Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington
transistor pair.
Port 3
Port 3 pins
Mode 1
Modes 2 and 3
P37 /D7
D7 (input/output)
P37 (input/output)
P36 /D6
D6 (input/output)
P36 (input/output)
P35 /D5
D5 (input/output)
P35 (input/output)
P34 /D4
D4 (input/output)
P34 (input/output)
P33 /D3
D3 (input/output)
P33 (input/output)
P32 /D2
D2 (input/output)
P32 (input/output)
P31 /D1
D1 (input/output)
P31 (input/output)
P30 /D0
D0 (input/output)
P30 (input/output)
Figure 7-7 Port 3 Pin Configuration
7.4.2 Register Descriptions
Table 7-5 summarizes the registers of port 3.
Table 7-5 Port 3 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFC4
Port 3 data direction register
P3DDR
W
H'00
H'FFC6
Port 3 data register
P3DR
R/W
H'00
Note: * Lower 16 bits of the address.
131
Port 3 Data Direction Register (P3DDR): P3DDR is an 8-bit write-only register that can select
input or output for each pin in port 3.
Bit
7
6
5
4
3
2
1
0
P3 7 DDR P3 6 DDR P3 5 DDR P3 4 DDR P3 3 DDR P3 2 DDR P3 1 DDR P3 0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 3 data direction 7 to 0
These bits select input or output for port 3 pins
Mode 1: Port 3 functions as a data bus. P3DDR is ignored.
Modes 2 and 3: Port 3 functions as an input/output port. A pin in port 3 becomes an output pin if
the corresponding P3DDR bit is set to 1, and an input pin if this bit is cleared to 0.
P3DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting. If a P3DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port 3 Data Register (P3DR): P3DR is an 8-bit readable/writable register that stores data for pins
P37 to P30.
Bit
7
6
5
4
3
2
1
0
P3 7
P3 6
P3 5
P3 4
P3 3
P3 2
P3 1
P3 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 3 data 7 to 0
These bits store data for port 3 pins
When a bit in P3DDR is set to 1, if port 3 is read the value of the corresponding P3DR bit is
returned directly, regardless of the actual state of the pin. When a bit in P3DDR is cleared to 0, if
port 3 is read the corresponding pin level is read.
P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
132
7.4.3 Pin Functions in Each Mode
The pin functions of port 3 differ between modes 1 and modes 2 and 3. The pin functions in each
mode are described below.
Mode 1: All pins of port 3 automatically become data input/output pins. Figure 7-8 shows the pin
functions in mode 1.
D7 (input/output)
D6 (input/output)
D5 (input/output)
Port 3
D4 (input/output)
D3 (input/output)
D2 (input/output)
D1 (input/output)
D0 (input/output)
Figure 7-8 Pin Functions in Mode 1 (Port 3)
Modes 2 and 3: Input or output can be selected separately for each pin in port 3. A pin becomes an
output pin if the corresponding P3DDR bit is set to 1, and an input pin if this bit is cleared to 0.
Figure 7-9 shows the pin functions in modes 2 and 3.
P3 7 (input/output)
P3 6 (input/output)
P3 5 (input/output)
P3 4 (input/output)
Port 3
P3 3 (input/output)
P3 2 (input/output)
P3 1 (input/output)
P3 0 (input/output)
Figure 7-9 Pin Functions in Modes 2 and 3 (Port 3)
133
7.5 Port 5
7.5.1 Overview
Port 5 is a 4-bit input/output port with the pin configuration shown in figure 7-10. The pin functions
differ depending on the operating mode.
In mode 1, settings in the port 5 data direction register (P5DDR) designate pins for address bus
output (A19 to A16) or generic input. In modes 2 and 3, port 5 is a generic input/output port.
Port 5 has software-programmable built-in pull-up transistors.
Pins in port 5 can drive one TTL load and a 90-pF capacitive load. They can also drive a LED or a
darlington transistor pair.
Port 5
Port 5
pins
Mode 1
Modes 2 and 3
P53 /A 19
P5 3 (input)/A19 (output)
P5 3 (input/output)
P52 /A 18
P5 2 (input)/A18 (output)
P5 2 (input/output)
P51 /A 17
P5 1 (input)/A17 (output)
P5 1 (input/output)
P50 /A 16
P5 0 (input)/A16 (output)
P5 0 (input/output)
Figure 7-10 Port 5 Pin Configuration
7.5.2 Register Descriptions
Table 7-6 summarizes the registers of port 5.
Table 7-6 Port 5 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFC8
Port 5 data direction register
P5DDR
W
H'F0
H'FFCA
Port 5 data register
P5DR
R/W
H'F0
H'FFDB
Port 5 input pull-up control register
P5PCR
R/W
H'F0
Note: * Lower 16 bits of the address.
134
Port 5 Data Direction Register (P5DDR): P5DDR is an 8-bit write-only register that can select
input or output for each pin in port 5.
2
1
0
7
6
5
4
Bit
—
—
—
—
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
W
W
W
W
3
P5 3 DDR P5 2 DDR P5 1 DDR P5 0 DDR
Reserved bits
Port 5 data direction 3 to 0
These bits select input or
output for port 5 pins
Mode 1: A pin in port 5 becomes an address output pin if the corresponding P5DDR bit is set to 1,
and a generic input pin if this bit is cleared to 0.
Modes 2 and 3: Port 5 functions as an input/output port. A pin in port 5 becomes an output pin if
the corresponding P5DDR bit is set to 1, and an input pin if this bit is cleared to 0.
P5DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P5DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting. If a P5DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port 5 Data Register (P5DR): P5DR is an 8-bit readable/writable register that stores data for pins
P53 to P50.
When a bit in P5DDR is set to 1, if port 5 is read the value of the corresponding P5DR bit is
Bit
7
6
5
4
3
2
1
0
—
—
—
—
P5 3
P5 2
P5 1
P5 0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Port 5 data 3 to 0
These bits store data
for port 5 pins
returned directly, regardless of the actual state of the pin. When a bit in P5DDR is cleared to 0, if
port 5 is read the corresponding pin level is read.
135
Bits P57 to P54 are reserved. They can be written and read, but they cannot be used for port input or
output.
P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 5 Input Pull-Up Control Register (P5PCR): P5PCR is an 8-bit readable/writable register
that controls the MOS input pull-up transistors in port 5.
Bit
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
3
2
1
0
P5 3 PCR P5 2 PCR P5 1 PCR P5 0 PCR
Port 5 input pull-up control 3 to 0
These bits control input pull-up
transistors built into port 5
When a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding bit from P53PCR
to P50PCR is set to 1, the input pull-up transistor is turned on.
P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
136
7.5.3 Pin Functions in Each Mode
The functions of port 5 differ depending on the operating mode. The pin functions in each mode are
described below.
Mode 1: Address output or generic input can be selected for each pin in port 5. A pin becomes an
address output pin if the corresponding P5DDR bit is set to 1, and a generic input pin if this bit is
cleared to 0. Following a reset, all pins are input pins. To use a pin for address output, its P5DDR
must be set to 1. Figure 7-11 shows the pin functions in mode 1.
Port 5
When P5DDR = 1
When P5DDR = 0
A 19 (output)
P5 3 (input)
A 18 (output)
P5 2 (input)
A 17 (output)
P5 1 (input)
A 16 (output)
P5 0 (input)
Figure 7-11 Pin Functions in Mode 1 (Port 5)
Modes 2 and 3: Input or output can be selected separately for each pin in port 5. A pin becomes an
output pin if the corresponding P5DDR bit is set to 1, and an input pin if this bit is cleared to 0.
Figure 7-12 shows the pin functions in modes 2 and 3.
P5 3 (input/output)
Port 5
P5 2 (input/output)
P5 1 (input/output)
P5 0 (input/output)
Figure 7-12 Pin Functions in Modes 2 and 3 (Port 5)
137
7.5.4 Input Pull-Up Transistors
Port 5 has built-in MOS pull-up transistors that can be controlled by software. These input pull-up
transistors can be turned on and off individually.
When a P5PCR bit is set to 1 and the corresponding P5DDR bit is cleared to 0, the input pull-up
transistor is turned on.
The input pull-up transistors are turned off by a reset and in hardware standby mode. In software
standby mode they retain their previous state.
Table 7-7 summarizes the states of the input pull-up transistors in each mode.
Table 7-7 Input Pull-Up Transistor States (Port 5)
Mode
Reset
Hardware Standby Mode
Software Standby Mode
Other Modes
1
2
3
Off
Off
On/off
On/off
Legend
Off:
The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P5PCR = 1 and P5DDR = 0. Otherwise, it is off.
138
7.6 Port 6
7.6.1 Overview
Port 6 is a 4-bit input/output port that is also used for input and output of bus control signals (WR,
RD, AS, and WAIT).
Figure 7-13 shows the pin configuration of port 6. In mode 1, the pin functions are WR, RD, AS,
and P60/WAIT. In modes 2 and 3, port 6 is a generic input/output port.
Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington
transistor pair.
Port 6
Port 6 pins
Modes 1
Modes 2 and 3
P6 5 / WR
WR (output)
P6 5 (input/output)
P6 4 / RD
RD (output)
P6 4 (input/output)
P6 3 / AS
AS (output)
P6 3 (input/output)
P6 0 / WAIT
P6 (input/output)/WAIT (input)
P6 0 (input/output)
Figure 7-13 Port 6 Pin Configuration
7.6.2 Register Descriptions
Table 7-8 summarizes the registers of port 6.
Table 7-8 Port 6 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFC9
Port 6 data direction register
P6DDR
W
H'80
H'FFCB
Port 6 data register
P6DR
R/W
H'80
Note: * Lower 16 bits of the address.
139
Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select
input or output for each pin in port 6.
Bit
7
6
—
—
Initial value
1
0
Read/Write
—
W
4
2
1
0
P6 5 DDR P6 4 DDR P6 3 DDR
—
—
P6 0 DDR
0
0
0
0
0
0
W
W
W
W
W
W
5
Reserved bit
3
Port 6 data direction 6 to 0
These bits select input or output for port 6 pins
Mode 1: Pins P65 to P63 function as bus control output pins (WR, RD, AS). P60 functions as an
input/output pin. When P60DDR is set to 1, P60 is an output pin, and when P60DDR is 0, P60 is an
input pin. The P65DDR to P63DDR bit settings are ignored.
Modes 2 and 3: Port 6 is a generic input/output port. A pin in port 6 becomes an output pin if the
corresponding P6DDR bit is set to 1, and an input pin if this bit is cleared to 0. Bits 7, 6, 2, and 1
are reserved.
P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting. If a P6DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores data for pins
P65 to P63 and P60.
Bit
7
6
5
4
3
2
1
0
—
—
P6 5
P6 4
P6 3
—
—
P6 0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bit
Port 6 data 5 to 3, 0
These bits store data for port 6 pins
140
When a bit in P6DDR is set to 1, if port 6 is read the value of the corresponding P6DR bit is
returned directly. When a bit in P6DDR is cleared to 0, if port 6 is read the corresponding pin level
is read. Bits 7, 6, 2, and 1 are reserved. Bit 7 cannot be modified and always reads 1. Bits 6, 2, and
1 can be written and read, but cannot be used as ports. If bit 6, 2, or 1 in P6DDR is read while its
value is 1, the value of the corresponding bit in P6DR will be read. If bit 6, 2, or 1 in P6DDR is
read while its value is 0, if will always read 1.
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
7.6.3 Pin Functions in Each Mode
Mode 1: P65 to P63 function as bus control output pins. P60 is either a bus control input pin or
generic input/output pin, functioning as an output pin when bit P60DDR is set to 1 and an input pin
when this bit is cleared to 0. Figure 7-14 and table 7-9 indicate the pin functions in mode 1.
WR (output)
RD (output)
Port 6
AS (output)
P60 (input/output)/WAIT (input)
Figure 7-14 Pin Functions in Mode 1 (Port 6)
141
Table 7-9 Port 6 Pin Functions in Mode 1
Pin
Pin Functions and Selection Method
P65/WR
Functions as follows regardless of P65DDR
P65DDR
0
1
WR output
Pin function
P64/RD
Functions as follows regardless of P64DDR
P64DDR
0
1
RD output
Pin function
P63/AS
Functions as follows regardless of P63DDR
P63DDR
0
1
AS output
Pin function
P60/WAIT
Bits WCE7 to WCE0 in WCER, bit WMS1 in WCR, and bit P60DDR select the
pin function as follows
WCER
All 1s
WMS1
P60DDR
Pin function
Not all 1s
0
0
1
P60 input
P60 output
Note: * Do not set bit P60DDR to 1.
142
1
—
0*
0*
WAIT input
Modes 2 and 3: Input or output can be selected separately for each pin in port 6. A pin becomes an
output pin if the corresponding P6DDR bit is set to 1, and an input pin if this bit is cleared to 0.
Figure 7-15 shows the pin functions in modes 2 and 3.
P6 5 (input/output)
P6 4 (input/output)
Port 6
P6 3 (input/output)
P6 0 (input/output)
Figure 7-15 Pin Functions in Modes 2 and 3 (Port 6)
143
7.7 Port 7
7.7.1 Overview
Port 7 is an 8-bit input port that is also used for analog input to the A/D converter. The pin
functions are the same in all operating modes. Figure 7-16 shows the pin configuration of port 7.
Port 7 pins
P77 (input)/AN 7 (input)
P76 (input)/AN 6 (input)
P75 (input)/AN 5 (input)
Port 7
P74 (input)/AN 4 (input)
P73 (input)/AN 3 (input)
P72 (input)/AN 2 (input)
P71 (input)/AN 1 (input)
P70 (input)/AN 0 (input)
Figure 7-16 Port 7 Pin Configuration
144
7.7.2 Register Description
Table 7-10 summarizes the port 7 register. Port 7 is an input-only port, so it has no data direction
register.
Table 7-10 Port 7 Data Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FFCE
Port 7 data register
P7DR
R
Undetermined
Note: * Lower 16 bits of the address.
Port 7 Data Register (P7DR)
Bit
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Note: * Determined by pins P7 7 to P70 .
When port 7 is read, the pin levels are always read.
145
7.8 Port 8
7.8.1 Overview
Port 8 is a 4-bit input/output port that is also used for IRQ3 to IRQ0 input. Figure 7-17 shows the
pin configuration of port 8.
Pin P80 functions as input/output pin or as an IRQ0 input pin. Pins P83 to P81 function as either
input pins or IRQ3 to IRQ1 input pins in mode 1, and as input/output pins or IRQ3 to IRQ1 input
pins in modes 2 and 3.
Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington
transistor pair. Pins P82 to P80 have Schmitt-trigger inputs.
Port 8
Port 8 pins
Mode 1
Modes 2 and 3
P83/IRQ3
P83 (input)/IRQ3 (input)
P83 (input/output)/IRQ3 (input)
P82/IRQ2
P82 (input)/IRQ2 (input)
P82 (input/output)/IRQ2 (input)
P81/IRQ1
P81 (input)/IRQ1 (input)
P81 (input/output)/IRQ1 (input)
P80/IRQ0
P80 (input/output)/IRQ0 (input) P80 (input/output)/IRQ0 (input)
Figure 7-17 Port 8 Pin Configuration
146
7.8.2 Register Descriptions
Table 7-11 summarizes the registers of port 8.
Table 7-11 Port 8 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFCD
Port 8 data direction
register
P8DDR
W
H'E0
H'FFCF
Port 8 data register
P8DR
R/W
H'E0
Note: * Lower 16 bits of the address.
Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select
input or output for each pin in port 8.
Bit
7
6
5
4
—
—
—
—
1
0
P8 3 DDR P8 2 DDR P8 1 DDR P8 0 DDR
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
W
W
W
W
W
Reserved bits
•
2
3
Port 8 data direction 3 to 0
These bits select input or
output for port 8 pins
Mode 1
Pins P83 to P81 function as input pins. Do not set P83DDR to P81DDR to 1. Pin P80 functions
as an output pin when P80DDR is set to 1, and as input pin when P80DDR is cleared to 0.
•
Modes 2 and 3
Port 8 is a generic input/output port. A pin port 8 becomes an output pin if the corresponding
P8DDR bit is set to 1, and an input pin if this bit is cleared to 0.
Bits 7 to 4 are reserved bits. P8DDR is a write-only register. Its value cannot be read. All bits return
1 when read.
P8DDR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting. If a P8DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
147
Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores data for pins
P83 to P80.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
P8 3
P8 2
P8 1
P8 0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 8 data 4 to 0
These bits store data
for port 8 pins
When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is
returned directly. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin level
is read.
Bits 7 to 4 are reserved. Bits 7 to 5 cannot be modified and always read 1. Bit 4 can be written and
read, but it cannot be used for port input or output. If bit 4 of P8DDR is read while its value is 1, bit
4 of P8DR is read directly. If bit 4 of P8DDR is read while its value is 0, it always reads 1.
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
7.8.3 Pin Functions
The port 8 pins are also used for IRQ3 to IRQ0. Table 7-12 describes the selection of pin functions.
148
Table 7-12 Port 8 Pin Functions
Pin
Pin Functions and Selection Method
P83/IRQ3
Bit P83DDR selects the pin function as follows
P83DDR
Pin function
0
1
P83 input
Mode 1
Modes 2 and 3
Illegal setting
P83 output
IRQ3 input
P82/IRQ2
Bit P82DDR selects the pin function as follows
P82DDR
Pin function
0
1
P82 input
Mode 1
Modes 2 and 3
Illegal setting
P82 output
IRQ2 input
P81/IRQ1
Bit P81DDR selects the pin function as follows
P81DDR
Pin function
0
1
P81 input
Mode 1
Modes 2 and 3
Illegal setting
P81 output
IRQ1 input
P80/IRQ0
Bit P80DDR selects the pin function as follows
P80DDR
Pin function
0
1
P80 input
P80 output
IRQ0 input
149
7.9 Port 9
7.9.1 Overview
Port 9 is a 3-bit input/output port that is also used for input and output (TxD, RxD, SCK) by serial
communication interface (SCI), and for IRQ4 input. Port 9 has the same set of pin functions in all
operating modes. Figure 7-18 shows the pin configuration of port 9.
Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington
transistor pair.
Port 9 pins
P94 (input/output)/SCK (input/output)/IRQ4 (input)
Port 9
P92 (input/output)/RxD (input)
P90 (input/output)/TxD (output)
Figure 7-18 Port 9 Pin Configuration
7.9.2 Register Descriptions
Table 7-13 summarizes the registers of port 9.
Table 7-13 Port 9 Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFD0
Port 9 data direction register
P9DDR
W
H'C0
H'FFD2
Port 9 data register
P9DR
R/W
H'C0
Note: * Lower 16 bits of the address.
150
Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select
input or output for each pin in port 9.
Bit
7
6
5
4
3
2
1
0
—
—
—
P9 4 DDR
—
P9 2 DDR
—
P9 0 DDR
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
W
W
W
W
W
W
Reserved bits
Port 9 data direction 4, 2, 0
These bits select input or
output for port 9 pins
A pin in port 9 becomes an output pin if the corresponding P9DDR bit is set to 1, and an input pin
if this bit is cleared to 0.
P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting. If a P9DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores data for pins
P94, P92, and P90.
Bit
7
6
5
4
3
2
1
0
—
—
—
P9 4
—
P9 2
—
P9 0
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 9 data 4, 2, 0
These bits store data
for port 9 pins
When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is
returned directly. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin level
is read.
151
Bits 7 to 5, 3 and 1 are reserved. Bits 7 and 6 cannot be modified and always read 1. Bits 5, 3, and 1
can be written and read, but they cannot be used for port input or output. If bit 5, 3, or 1 in P9DDR
is read while its value is 1, the corresponding bit in P9DR is read directly. If bit 5, 3, or 1 in P9DDR
is read while its value is 0, it always reads 1.
P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
7.9.3 Pin Functions
The port 9 pins are also used for SCI input and output (TxD, RxD, SCK), and for IRQ4 input. Table
7-14 describes the selection of pin functions.
Table 7-14 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P94/SCK/IRQ4
Bit C/A in SMR of SCI, bits CKE0 and CKE1 in SCR of SCI, and bit P94DDR
select the pin function as follows
CKE1
0
C/A
0
CKE0
P94DDR
Pin function
1
0
0
1
P94
P94
input output
1
—
1
—
—
—
—
—
SCK output
SCK output
SCK input
IRQ4 input
P92/RxD
Bit RE in SCR of SCI and bit P92DDR select the pin function as follows
RE
P92DDR
Pin function
P90/TxD
0
1
0
1
—
P92 input
P92 output
RxD input
Bit TE in SCR of SCI and bit P90DDR select the pin function as follows
TE
P90DDR
Pin function
0
1
0
1
—
P90 input
P90 output
TxD output
152
7.10 Port A
7.10.1 Overview
Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the programmable
timing pattern controller (TPC) and input and output (TIOCB2, TIOCA2, TIOCB1, TIOCA1,
TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit integrated timer unit (ITU),
Figure 7-19 shows the pin configuration of port A.
Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington
transistor pair. Port A has Schmitt-trigger inputs.
Port A pins
PA 7/TP7 /TIOCB2
PA 6/TP6 /TIOCA2
PA 5/TP5 /TIOCB1
PA 4/TP4 /TIOCA1
Port A
PA 3/TP3 /TIOCB 0 /TCLKD
PA 2/TP2 /TIOCA 0 /TCLKC
PA 1/TP1 /TEND1 /TCLKB
PA 0/TP0 /TEND0 /TCLKA
Figure 7-19 Port A Pin Configuration
153
7.10.2 Register Descriptions
Table 7-15 summarizes the registers of port A.
Table 7-15 Port A Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFD1
Port A data direction register
PADDR
W
H'00
H'FFD3
Port A data register
PADR
R/W
H'00
Note: * Lower 16 bits of the address.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A.
7
Bit
6
5
4
3
2
1
0
PA7 DDR PA6 DDR PA5 DDR PA4 DDR PA3 DDR PA2 DDR PA1 DDR PA0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input pin
if this bit is cleared to 0.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting. If a PADDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
154
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores data for
pins PA7 to PA0.
Bit
7
6
5
4
3
2
1
0
PA 7
PA 6
PA 5
PA 4
PA 3
PA 2
PA 1
PA 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port A data 7 to 0
These bits store data for port A pins
When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is
returned directly. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level
is read.
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
When port A pins are used for TPC output, PADR stores output data for TPC output groups 0 and
1. If a bit in the next data enable register (NDERA) is set to 1, the corresponding PADR bit cannot
be written. In this case, PADR can be updated only when data is transferred from NDRA.
155
7.10.3 Pin Functions
The port A pins are also used for TPC output (TP7 to TP0), ITU input/output (TIOCB2 to TIOCB0,
TIOCA2 to TIOCA0), and input (TCLKD, TCLKC, TCLKB, TCLKA). Table 7-16 describes the
selection of pin functions.
Table 7-16 Port A Pin Functions
Pin
Pin Functions and Selection Method
PA7/TP7/
TIOCB2
ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to IOB0 in TIOR2), bit
NDER7 in NDERA, and bit PA7DDR in PADDR select the pin function as follows
ITU channel 2
settings
1 in table below
2 in table below
PA7DDR
—
0
1
1
NDER7
—
—
0
1
TIOCB2 output
PA7
input
PA7
output
TP7
output
Pin function
TIOCB2 input*
Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0.
ITU channel 2
settings
2
IOB2
1
2
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
156
Table 7-16 Port A Pin Functions (cont)
Pin
Pin Functions and Selection Method
PA6/TP6/
TIOCA2
ITU channel 2 settings (bit PWM2 in TMDR and bits IOA2 to IOA0 in TIOR2), bit NDER6
in NDERA, and bit PA6DDR in PADDR select the pin function as follows
ITU channel 2
settings
1 in table below
PA6DDR
2 in table below
—
NDER6
Pin function
0
1
1
—
—
0
1
TIOCA2 output
PA6 input
PA6 output
TP6 output
TIOCA2 input*
Note: * TIOCA2 input when IOA2 = 1.
ITU channel 2
settings
2
1
PWM2
1
1
—
0
IOA2
PA5/TP5/
TIOCB1
2
1
0
IOA1
0
0
1
—
—
IOA0
0
1
—
—
—
ITU channel 1 settings (bit PWM1 in TMDR and bits IOB2 to IOB0 in TIOR1), bit NDER5
in NDERA, and bit PA5DDR in PADDR select the pin function as follows
ITU channel 1
settings
1 in table below
2 in table below
PA5DDR
—
0
1
1
NDER5
—
—
0
1
TIOCB1 output
PA5 input
PA5 output
TP5 output
Pin function
TIOCB1 input*
Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0.
ITU channel 1
settings
2
IOB2
1
2
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
157
Table 7-16 Port A Pin Functions (cont)
Pin
Pin Functions and Selection Method
PA4/TP4/
TIOCA1
ITU channel 1 settings (bit PWM1 in TMDR and bits IOA2 to IOA0 in TIOR1), bit NDER4
in NDERA, and bit PA4DDR in PADDR select the pin function as follows
ITU channel 1
settings
1 in table below
PA4DDR
2 in table below
—
NDER4
Pin function
0
1
1
—
—
0
1
TIOCA1 output
PA4 input
PA4 output
TP4 output
TIOCA1 input*
Note: * TIOCA1 input when IOA2 = 1.
ITU channel 1
settings
2
1
PWM1
1
1
—
0
IOA2
PA3/TP3/
TIOCB0/
TCLKD
2
1
0
IOA1
0
0
1
—
—
IOA0
0
1
—
—
—
ITU channel 0 settings (bit PWM0 in TMDR and bits IOB2 to IOB0 in TIOR0), bits TPSC2
to TPSC0 in TCR4 to TCR0, bit NDER3 in NDERA, and bit PA3DDR in PADDR select
the pin function as follows
ITU
channel 0
settings
1 in table below
2 in table below
PA3DDR
—
0
1
1
NDER3
—
—
0
1
TIOCB0 output
PA3 input
Pin function
PA3 output TP3 output
TIOCB0 input*1
TCLKD input*2
Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0.
2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of TCR4 to TCR0.
ITU channel 0
settings
2
IOB2
1
2
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
158
Table 7-16 Port A Pin Functions (cont)
Pin
Pin Functions and Selection Method
PA2/TP2/
TIOCA0/
TCLKC
ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits TPSC2
to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit PA2DDR in PADDR select
the pin function as follows
ITU
channel 0
settings
1 in table below
PA2DDR
—
NDER2
Pin function
2 in table below
0
—
—
TIOCA0 output
PA2 input
1
1
0
1
PA2 output TP2 output
TIOCA0 input*1
TCLKC input*2
Notes: 1. TIOCA0 input when IOA2 = 1.
2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of TCR4 to
TCR0.
ITU channel 0
settings
2
1
PWM0
2
0
IOA2
1
1
1
—
IOA1
0
0
0
1
—
—
IOA0
0
1
—
—
—
159
Table 7-16 Port A Pin Functions (cont)
Pin
Pin Functions and Selection Method
PA1/TP1/
TCLKB
Bit NDER1 in NDERA and bit PA1DDR in PADDR select the pin function as follows
PA1DDR
0
1
1
NDER1
—
0
1
PA1 output
TP1 output
Pin function
PA1 input
TCLKB input*
Note: * TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0, and
TPSC0 = 1 in any of TCR4 to TCR0.
PA0/TP0/
TCLKA
Bit NDER0 in NDERA and bit PA0DDR in PADDR select the pin function as follows
PA0DDR
0
1
1
NDER0
—
0
1
PA0 output
TP0 output
Pin function
PA0 input
TCLKA input*
Note: * TCLKA input when MDF = 1 in TMDR, or when TPSC2 = 1 and TPSC1 = 0 in any
of TCR4 to TCR0.
160
7.11 Port B
7.11.1 Overview
Port B is an 8-bit input/output port that is also used for TPC output (TP15 to TP8), ITU input/output
(TIOCB4, TIOCB3, TIOCA4, TIOCA3) and ITU output (TOCXB4, TOCXA4), and ADTRG input
to the A/D converter. Port B has the same set of pin functions in all operating modes. Figure 7-20
shows the pin configuration of port B.
Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington
transistor pair. Pins PB3 to PB0 have Schmitt-trigger inputs.
Port B pins
PB 7 (input/output)/TP15 (output)/ADTRG (input)
PB 6 (input/output)/TP14 (output)
PB 5 (input/output)/TP13 (output)/TOCXB 4 (output)
PB 4 (input/output)/TP12 (output)/TOCXA 4 (output)
Port B
PB 3 (input/output)/TP11 (output)/TIOCB 4 (input/output)
PB 2 (input/output)/TP10 (output)/TIOCA 4 (input/output)
PB 1 (input/output)/TP9 (output)/TIOCB 3 (input/output)
PB 0 (input/output)/TP8 (output)/TIOCA 3 (input/output)
Figure 7-20 Port B Pin Configuration
7.11.2 Register Descriptions
Table 7-17 summarizes the registers of port B.
Table 7-17 Port B Registers
Address*
Name
Abbreviation
R/W
Initial Value
H'FFD4
Port B data direction register
PBDDR
W
H'00
H'FFD6
Port B data register
PBDR
R/W
H'00
Note: * Lower 16 bits of the address.
161
Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B.
Bit
7
6
5
4
3
2
1
0
PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port B data direction 7 to 0
These bits select input or output for port B pins
A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input pin
if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting. If a PBDDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores data for pins
PB7 to PB0.
Bit
7
6
5
4
3
2
1
0
PB 7
PB 6
PB 5
PB 4
PB 3
PB 2
PB 1
PB 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port B data 7 to 0
These bits store data for port B pins
When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is
returned directly. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin level
is read.
PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
When port B pins are used for TPC output, PBDR stores output data for TPC output groups 2 and
3. If a bit in the next data enable register (NDERB) is set to 1, the corresponding PBDR bit cannot
be written. In this case, PBDR can be updated only when data is transferred from NDRB.
162
7.11.3 Pin Functions
The port B pins are also used for TPC output (TP15 to TP8), ITU input/output (TIOCB4, TIOCB3,
TIOCA4, TIOCA3) and output (TOCXB4, TOCXA4), and ADTRG input. Table 7-18 describes the
selection of pin functions.
Table 7-18 Port B Pin Functions
Pin
Pin Functions and Selection Method
PB7/
TP15/
ADTRG
Bit TRGE in ADCR, bit NDER15 in NDERB and bit PB7DDR in PBDDR select the
pin function as follows
PB7DDR
0
NDER15
Pin function
1
1
—
0
1
PB7 input
PB7 output
TP15 output
ADTRG input*
Notes: * ADTRG input when TRGE = 1.
PB6/
TP14/
Bit NDER14 in NDERB and bit PB6DDR in PBDDR select the pin function as follows
PB6DDR
0
1
1
NDER14
—
0
1
PB6 input
PB6 output
TP14 output
Pin function
PB5/
TP13/
TOCXB4
ITU channel 4 settings (bit CMD1 in TFCR and bit EXB4 in TOER), bit NDER13 in
NDERB, and bit PB5DDR in PBDDR select the pin function as follows
EXB4,
CMD1
PB5DDR
NDER13
Pin function
PB4/
TP12/
TOCXA4
Not both 1
0
—
PB5 input
Both 1
1
1
0
1
PB5 output TP13 output
—
—
TOCXB4 output
ITU channel 4 settings (bit CMD1 in TFCR and bit EXA4 in TOER), bit NDER12 in
NDERB, and bit PB4DDR in PBDDR select the pin function as follows
EXA4,
CMD1
Not both 1
Both 1
PB4DDR
0
1
1
—
NDER12
—
0
1
—
Pin function
PB4 input
PB4 output TP12 output
163
TOCXA4 output
Table 7-18 Port B Pin Functions (cont)
Pin
Pin Functions and Selection Method
PB3/
TP11/
TIOCB4
ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and
bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB3DDR in PBDDR select
the pin function as follows
ITU
channel 4
settings
1 in table below
PB3DDR
—
NDER11
2 in table below
—
TIOCB4 output
Pin function
0
1
1
—
0
1
PB3 input PB3 output TP11 output
TIOCB4 input*
Note: * TIOCB4 input when CMD1 = PWM4 = 0 and IOB2 = 1.
ITU
channel 4
settings
2
EB4
0
2
1
2
1
1
—
1
CMD1
—
IOB2
—
0
0
0
IOB1
—
0
0
1
—
—
IOB0
—
0
1
—
—
—
164
1
0
Table 7-18 Port B Pin Functions (cont)
Pin
Pin Functions and Selection Method
PB2/
TP10/
TIOCA4
ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and
bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB2DDR in PBDDR select
the pin function as follows
ITU
channel 4
settings
1 in table below
PB2DDR
—
NDER10
2 in table below
—
TIOCA4 output
Pin function
0
1
1
—
0
1
PB2 input PB2 output TP10 output
TIOCA4 input*
Note: * TIOCA4 input when CMD1 = PWM4 = 0 and IOA2 = 1.
DMAC
channel 4
settings
2
EA4
0
2
1
2
1
1
CMD1
—
PWM4
—
0
1
IOA2
—
0
0
0
IOA1
—
0
0
1
IOA0
—
0
1
—
—
0
165
1
—
1
—
—
—
—
—
—
—
Table 7-18 Port B Pin Functions (cont)
Pin
Pin Functions and Selection Method
PB1/TP9/ ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and
TIOCB3
bits IOB2 to IOB0 in TIOR3), bit NDER9 in NDERB, and bit PB1DDR in PBDDR select
the pin function as follows
ITU
channel 3
settings
1 in table below
PB1DDR
—
NDER9
2 in table below
—
TIOCB3 output
Pin function
0
1
1
—
0
1
PB1 input PB1 output TP9 output
TIOCB3 input*
Note: * TIOCB3 input when CMD1 = PWM3 = 0 and IOB2 = 1.
ITU
channel 3
settings
2
EB3
0
2
1
2
1
1
—
1
CMD1
—
IOB2
—
0
0
0
IOB1
—
0
0
1
—
—
IOB0
—
0
1
—
—
—
166
1
0
Table 7-18 Port B Pin Functions (cont)
Pin
Pin Functions and Selection Method
PB0/TP8/ ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, and
TIOCA3
bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB0DDR in PBDDR select
the pin function as follows
ITU
channel 3
settings
1 in table below
PB0DDR
—
NDER8
2 in table below
—
TIOCA3 output
Pin function
0
1
1
—
0
1
PB0 input PB0 output TP8 output
TIOCA3 input*
Note: * TIOCA3 input when CMD1 = PWM3 = 0 and IOA2 = 1.
ITU
channel 3
settings
2
EA3
0
2
1
2
1
1
CMD1
—
PWM3
—
0
1
IOA2
—
0
0
0
IOA1
—
0
0
1
IOA0
—
0
1
—
—
0
167
1
—
1
—
—
—
—
—
—
—
168
Section 8 16-Bit Integrated Timer Unit (ITU)
8.1 Overview
The H8/3032 Series has a built-in 16-bit integrated timer-pulse unit (ITU) with five 16-bit timer
channels.
8.1.1 Features
ITU features are listed below.
•
Capability to process up to 12 pulse outputs or 10 pulse inputs
•
Ten general registers (GRs, two per channel) with independently-assignable output compare
or input capture functions
•
Selection of eight counter clock sources for each channel:
Internal clocks: ø, ø/2, ø/4, ø/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD
•
Five operating modes selectable in all channels:
— Waveform output by compare match
Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)
— Input capture function
Rising edge, falling edge, or both edges (selectable)
— Counter clearing function
Counters can be cleared by compare match or input capture
— Synchronization
Two or more timer counters (TCNTs) can be preset simultaneously, or cleared
simultaneously by compare match or input capture. Counter synchronization enables
synchronous register input and output.
169
— PWM mode
PWM output can be provided with an arbitrary duty cycle. With synchronization, up to
five-phase PWM output is possible
•
Phase counting mode selectable in channel 2
Two-phase encoder output can be counted automatically.
•
Three additional modes selectable in channels 3 and 4
— Reset-synchronized PWM mode
If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of
complementary waveforms.
— Complementary PWM mode
If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of
non-overlapping complementary waveforms.
— Buffering
Input capture registers can be double-buffered. Output compare registers can be updated
automatically.
•
High-speed access via internal 16-bit bus
The 16-bit timer counters, general registers, and buffer registers can be accessed at high speed
via a 16-bit bus.
•
Fifteen interrupt sources
Each channel has two compare match/input capture interrupts and an overflow interrupt. All
interrupts can be requested independently.
•
Output triggering of programmable pattern controller (TPC)
Compare match/input capture signals from channels 0 to 3 can be used as TPC output
triggers.
170
Table 8-1 summarizes the ITU functions.
Table 8-1 ITU Functions
Item
Channel 0
Clock sources
Internal clocks: ø, ø/2, ø/4, ø/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently
General registers
(output compare/input
capture registers)
GRA0, GRB0
GRA1, GRB1
GRA2, GRB2
GRA3, GRB3
Buffer registers
—
—
—
BRA3, BRB3
BRA4, BRB4
Input/output pins
TIOCA0,
TIOCB0
TIOCA1,
TIOCB1
TIOCA2,
TIOCB2
TIOCA3,
TIOCB3
TIOCA4,
TIOCB4
Output pins
—
—
—
—
TOCXA4,
TOCXB4
Counter clearing function
GRA0/GRB0
compare
match or
input capture
GRA1/GRB1
compare
match or
input capture
GRA2/GRB2
compare
match or
input capture
GRA3/GRB3
compare
match or
input capture
GRA4/GRB4
compare
match or
input capture
0
oo
oo
o
1
oo
oo
o
Toggle
oo
—
oo
Input capture function
oo
oo
o
Synchronization
oo
oo
o
PWM mode
oo
oo
o
Reset-synchronized
PWM mode
—
—
—
oo
Complementary PWM
mode
—
—
—
oo
Phase counting mode
—
—
o—
—
Buffering
—
—
—
oo
Interrupt sources
Three sources
Three sources
Three sources
Three sources
Three sources
• Compare
match/input
capture A0
• Compare
match/input
capture A1
• Compare
match/input
capture A2
• Compare
match/input
capture A3
• Compare
match/input
capture A4
• Compare
match/input
capture B0
• Compare
match/input
capture B1
• Compare
match/input
capture B2
• Compare
match/input
capture B3
• Compare
match/input
capture B4
• Overflow
• Overflow
• Overflow
• Overflow
• Overflow
Compare
match output
Channel 1
Legend
o: Available
—: Not available
171
Channel 2
Channel 3
Channel 4
GRA4, GRB4
8.1.2 Block Diagrams
ITU Block Diagram (overall): Figure 8-1 is a block diagram of the ITU.
TCLKA to TCLKD
Clock selector
IMIA0 to IMIA4
IMIB0 to IMIB4
OVI0 to OVI4
Control logic
ø, ø/2, ø/4, ø/8
Counter control and
pulse I/O control unit
TOCXA4, TOCXB4
TIOCA0 to TIOCA4
TIOCB0 to TIOCB4
TSTR
TSNC
TMDR
TFCR
Module data bus
Legend
TOER:
TOCR:
TSTR:
TSNC:
TMDR:
TFCR:
Timer output master enable register (8 bits)
Timer output control register (8 bits)
Timer start register (8 bits)
Timer synchro register (8 bits)
Timer mode register (8 bits)
Timer function control register (8 bits)
Figure 8-1 ITU Block Diagram (Overall)
172
On-chip data bus
TOCR
Bus interface
16-bit timer channel 0
16-bit timer channel 1
16-bit timer channel 2
16-bit timer channel 3
16-bit timer channel 4
TODR
Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have
the structure shown in figure 8-2.
TCLKA to TCLKD
TIOCA0
TIOCB0
Clock selector
ø, ø/2, ø/4, ø/8
IMIA0
IMIB0
OVI0
TSR
TIER
TCR
TIOR
Control logic
GRB
GRA
TCNT
Comparator
Module data bus
Legend
TCNT:
GRA, GRB:
TCR:
TIOR:
TIER:
TSR:
Timer counter (16 bits)
General registers A and B (input capture/output compare registers) (16 bits × 2)
Timer control register (8 bits)
Timer I/O control register (8 bits)
Timer interrupt enable register (8 bits)
Timer status register (8 bits)
Figure 8-2 Block Diagram of Channels 0 and 1 (for Channel 0)
173
Block Diagram of Channel 2: Figure 8-3 is a block diagram of channel 2. This is the channel
that provides only 0 output and 1 output.
TCLKA to TCLKD
TIOCA2
TIOCB2
Clock selector
ø, ø/2, ø/4, ø/8
IMIA2
IMIB2
OVI2
TSR2
TIER2
TCR2
TIOR2
Control logic
GRB2
GRA2
TCNT2
Comparator
Module data bus
Legend
Timer counter 2 (16 bits)
TCNT2:
GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers)
(16 bits × 2)
Timer control register 2 (8 bits)
TCR2:
Timer I/O control register 2 (8 bits)
TIOR2:
Timer interrupt enable register 2 (8 bits)
TIER2:
Timer status register 2 (8 bits)
TSR2:
Figure 8-3 Block Diagram of Channel 2
174
Block Diagrams of Channels 3 and 4: Figure 8-4 is a block diagram of channel 3. Figure 8-5 is a
block diagram of channel 4.
TCLKA to
TCLKD
ø, ø/2,
ø/4, ø/8
TIOCA3
TIOCB3
Clock selector
IMIA3
IMIB3
OVI3
TSR3
TIER3
TIOR3
TCR3
GRB3
Control logic
BRB3
GRA3
BRA3
TCNT3
Comparator
Module data bus
Legend
Timer counter 3 (16 bits)
TCNT3:
GRA3, GRB3: General registers A3 and B3 (input capture/output compare registers)
(16 bits × 2)
BRA3, BRB3: Buffer registers A3 and B3 (input capture/output compare buffer registers)
(16 bits × 2)
Timer control register 3 (8 bits)
TCR3:
TIOR3:
Timer I/O control register 3 (8 bits)
TIER3:
Timer interrupt enable register 3 (8 bits)
TSR3:
Timer status register 3 (8 bits)
Figure 8-4 Block Diagram of Channel 3
175
TCLKA to
TCLKD
ø, ø/2,
ø/4, ø/8
TOCXA4
TOCXB4
TIOCA4
TIOCB4
IMIA4
IMIB4
OVI4
Clock selector
TSR4
TIER4
TIOR4
TCR4
GRB4
Control logic
BRB4
GRA4
BRA4
TCNT4
Comparator
Module data bus
Legend
Timer counter 4 (16 bits)
TCNT4:
GRA4, GRB4: General registers A4 and B4 (input capture/output compare registers)
(16 bits × 2)
BRA4, BRB4: Buffer registers A4 and B4 (input capture/output compare buffer registers)
(16 bits × 2)
Timer control register 4 (8 bits)
TCR4:
Timer I/O control register 4 (8 bits)
TIOR4:
Timer interrupt enable register 4 (8 bits)
TIER4:
Timer status register 4 (8 bits)
TSR4:
Figure 8-5 Block Diagram of Channel 4
176
8.1.3 Input/Output Pins
Table 8-2 summarizes the ITU pins.
Table 8-2 ITU Pins
Abbreviation
Input/
Output
Common Clock input A
TCLKA
Input
External clock A input pin
(phase-A input pin in phase counting mode)
Clock input B
TCLKB
Input
External clock B input pin
(phase-B input pin in phase counting mode)
Clock input C
TCLKC
Input
External clock C input pin
Clock input D
TCLKD
Input
External clock D input pin
Input capture/output
compare A0
TIOCA0
Input/
output
GRA0 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B0
TIOCB0
Input/
output
GRB0 output compare or input capture pin
Input capture/output
compare A1
TIOCA1
Input/
output
GRA1 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B1
TIOCB1
Input/
output
GRB1 output compare or input capture pin
Input capture/output
compare A2
TIOCA2
Input/
output
GRA2 output compare or input capture pin
PWM output pin in PWM mode
Input capture/output
compare B2
TIOCB2
Input/
output
GRB2 output compare or input capture pin
Input capture/output
compare A3
TIOCA3
Input/
output
GRA3 output compare or input capture pin
PWM output pin in PWM mode, complementary PWM mode, or reset-synchronized
PWM mode
Input capture/output
compare B3
TIOCB3
Input/
output
GRB3 output compare or input capture pin
PWM output pin in complementary PWM
mode or reset-synchronized PWM mode
Input capture/output
compare A4
TIOCA4
Input/
output
GRA4 output compare or input capture pin
PWM output pin in PWM mode, complementary PWM mode, or reset-synchronized
PWM mode
Input capture/output
compare B4
TIOCB4
Input/
output
GRB4 output compare or input capture pin
PWM output pin in complementary PWM
mode or reset-synchronized PWM mode
Output compare XA4 TOCXA4
Output
PWM output pin in complementary PWM
mode or reset-synchronized PWM mode
Output compare XB4 TOCXB4
Output
PWM output pin in complementary PWM
mode or reset-synchronized PWM mode
Channel
0
1
2
3
4
Name
177
Function
8.1.4 Register Configuration
Table 8-3 summarizes the ITU registers.
Table 8-3 ITU Registers
Channel
Address*1
Name
Abbreviation
R/W
Initial
Value
Common
H'FF60
Timer start register
TSTR
R/W
H'E0
H'FF61
Timer synchro register
TSNC
R/W
H'E0
H'FF62
Timer mode register
TMDR
R/W
H'80
H'FF63
Timer function control register
TFCR
R/W
H'C0
H'FF90
Timer output master enable register
TOER
R/W
H'FF
H'FF91
Timer output control register
TOCR
R/W
H'FF
H'FF64
Timer control register 0
TCR0
R/W
H'80
H'FF65
Timer I/O control register 0
TIOR0
R/W
H'88
H'FF66
Timer interrupt enable register 0
TIER0
R/W
H'F8
H'F8
0
1
H'FF67
Timer status register 0
TSR0
R/(W)*2
H'FF68
Timer counter 0 (high)
TCNT0H
R/W
H'00
H'FF69
Timer counter 0 (low)
TCNT0L
R/W
H'00
H'FF6A
General register A0 (high)
GRA0H
R/W
H'FF
H'FF6B
General register A0 (low)
GRA0L
R/W
H'FF
H'FF6C
General register B0 (high)
GRB0H
R/W
H'FF
H'FF6D
General register B0 (low)
GRB0L
R/W
H'FF
H'FF6E
Timer control register 1
TCR1
R/W
H'80
H'FF6F
Timer I/O control register 1
TIOR1
R/W
H'88
H'FF70
Timer interrupt enable register 1
TIER1
R/W
H'F8
H'F8
H'FF71
Timer status register 1
TSR1
R/(W)*2
H'FF72
Timer counter 1 (high)
TCNT1H
R/W
H'00
H'FF73
Timer counter 1 (low)
TCNT1L
R/W
H'00
H'FF74
General register A1 (high)
GRA1H
R/W
H'FF
H'FF75
General register A1 (low)
GRA1L
R/W
H'FF
H'FF76
General register B1 (high)
GRB1H
R/W
H'FF
H'FF77
General register B1 (low)
GRB1L
R/W
H'FF
Notes: 1. The lower 16 bits of the address are indicated.
2. Only 0 can be written, to clear flags.
178
Table 8-3 ITU Registers (cont)
Channel
Address*1
Name
Abbreviation
R/W
Initial
Value
2
H'FF78
Timer control register 2
TCR2
R/W
H'80
H'FF79
Timer I/O control register 2
TIOR2
R/W
H'88
H'FF7A
Timer interrupt enable register 2
TIER2
R/W
H'F8
H'F8
3
H'FF7B
Timer status register 2
TSR2
R/(W)*2
H'FF7C
Timer counter 2 (high)
TCNT2H
R/W
H'00
H'FF7D
Timer counter 2 (low)
TCNT2L
R/W
H'00
H'FF7E
General register A2 (high)
GRA2H
R/W
H'FF
H'FF7F
General register A2 (low)
GRA2L
R/W
H'FF
H'FF80
General register B2 (high)
GRB2H
R/W
H'FF
H'FF81
General register B2 (low)
GRB2L
R/W
H'FF
H'FF82
Timer control register 3
TCR3
R/W
H'80
H'FF83
Timer I/O control register 3
TIOR3
R/W
H'88
H'FF84
Timer interrupt enable register 3
TIER3
R/W
H'F8
H'F8
H'FF85
Timer status register 3
TSR3
R/(W)*2
H'FF86
Timer counter 3 (high)
TCNT3H
R/W
H'00
H'FF87
Timer counter 3 (low)
TCNT3L
R/W
H'00
H'FF88
General register A3 (high)
GRA3H
R/W
H'FF
H'FF89
General register A3 (low)
GRA3L
R/W
H'FF
H'FF8A
General register B3 (high)
GRB3H
R/W
H'FF
H'FF8B
General register B3 (low)
GRB3L
R/W
H'FF
H'FF8C
Buffer register A3 (high)
BRA3H
R/W
H'FF
H'FF8D
Buffer register A3 (low)
BRA3L
R/W
H'FF
H'FF8E
Buffer register B3 (high)
BRB3H
R/W
H'FF
H'FF8F
Buffer register B3 (low)
BRB3L
R/W
H'FF
Notes: 1. The lower 16 bits of the address are indicated.
2. Only 0 can be written, to clear flags.
179
Table 8-3 ITU Registers (cont)
Channel
Address*1
Name
Abbreviation
R/W
Initial
Value
4
H'FF92
Timer control register 4
TCR4
R/W
H'80
H'FF93
Timer I/O control register 4
TIOR4
R/W
H'88
H'FF94
Timer interrupt enable register 4
TIER4
R/W
H'F8
H'F8
H'FF95
Timer status register 4
TSR4
R/(W)*2
H'FF96
Timer counter 4 (high)
TCNT4H
R/W
H'00
H'FF97
Timer counter 4 (low)
TCNT4L
R/W
H'00
H'FF98
General register A4 (high)
GRA4H
R/W
H'FF
H'FF99
General register A4 (low)
GRA4L
R/W
H'FF
H'FF9A
General register B4 (high)
GRB4H
R/W
H'FF
H'FF9B
General register B4 (low)
GRB4L
R/W
H'FF
H'FF9C
Buffer register A4 (high)
BRA4H
R/W
H'FF
H'FF9D
Buffer register A4 (low)
BRA4L
R/W
H'FF
H'FF9E
Buffer register B4 (high)
BRB4H
R/W
H'FF
H'FF9F
Buffer register B4 (low)
BRB4L
R/W
H'FF
Notes: 1. The lower 16 bits of the address are indicated.
2. Only 0 can be written, to clear flags.
180
8.2 Register Descriptions
8.2.1 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in
channels 0 to 4.
Bit
7
6
5
4
3
2
1
0
—
—
—
STR4
STR3
STR2
STR1
STR0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Reserved bits
Counter start 4 to 0
These bits start and
stop TCNT4 to TCNT0
TSTR is initialized to H'E0 by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—Counter Start 4 (STR4): Starts and stops timer counter 4 (TCNT4).
Bit 4
STR4
Description
0
TCNT4 is halted
1
TCNT4 is counting
(Initial value)
Bit 3—Counter Start 3 (STR3): Starts and stops timer counter 3 (TCNT3).
Bit 3
STR3
Description
0
TCNT3 is halted
1
TCNT3 is counting
(Initial value)
Bit 2—Counter Start 2 (STR2): Starts and stops timer counter 2 (TCNT2).
Bit 2
STR2
Description
0
TCNT2 is halted
1
TCNT2 is counting
(Initial value)
181
Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1).
Bit 1
STR1
Description
0
TCNT1 is halted
1
TCNT1 is counting
(Initial value)
Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0).
Bit 0
STR0
Description
0
TCNT0 is halted
1
TCNT0 is counting
(Initial value)
8.2.2 Timer Synchro Register (TSNC)
TSNC is an 8-bit readable/writable register that selects whether channels 0 to 4 operate
independently or synchronously. Channels are synchronized by setting the corresponding bits to 1.
Bit
7
6
5
4
3
2
1
0
—
—
—
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Reserved bits
Timer sync 4 to 0
These bits synchronize
channels 4 to 0
TSNC is initialized to H'E0 by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—Timer Sync 4 (SYNC4): Selects whether channel 4 operates independently or
synchronously.
Bit 4
SYNC4
Description
0
Channel 4’s timer counter (TCNT4) operates independently
TCNT4 is preset and cleared independently of other channels
1
Channel 4 operates synchronously
TCNT4 can be synchronously preset and cleared
182
(Initial value)
Bit 3—Timer Sync 3 (SYNC3): Selects whether channel 3 operates independently or
synchronously.
Bit 3
SYNC3
Description
0
Channel 3’s timer counter (TCNT3) operates independently
TCNT3 is preset and cleared independently of other channels
1
Channel 3 operates synchronously
TCNT3 can be synchronously preset and cleared
(Initial value)
Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or
synchronously.
Bit 2
SYNC2
Description
0
Channel 2’s timer counter (TCNT2) operates independently
TCNT2 is preset and cleared independently of other channels
1
Channel 2 operates synchronously
TCNT2 can be synchronously preset and cleared
(Initial value)
Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or
synchronously.
Bit 1
SYNC1
Description
0
Channel 1’s timer counter (TCNT1) operates independently
TCNT1 is preset and cleared independently of other channels
1
Channel 1 operates synchronously
TCNT1 can be synchronously preset and cleared
(Initial value)
Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or
synchronously.
Bit 0
SYNC0
Description
0
Channel 0’s timer counter (TCNT0) operates independently
TCNT0 is preset and cleared independently of other channels
1
Channel 0 operates synchronously
TCNT0 can be synchronously preset and cleared
183
(Initial value)
8.2.3 Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
7
6
5
4
3
2
1
0
—
MDF
FDIR
PWM4
PWM3
PWM2
PWM1
PWM0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM mode 4 to 0
These bits select PWM
mode for channels 4 to 0
Flag direction
Selects the setting condition for the overflow
flag (OVF) in timer status register 2 (TSR2)
Phase counting mode flag
Selects phase counting mode for channel 2
Reserved bit
TMDR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF
Description
0
Channel 2 operates normally
1
Channel 2 operates in phase counting mode
(Initial value)
184
When MDF is set to 1 to select phase counting mode, timer counter 2 (TCNT2) operates as an
up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts
both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows.
Counting Direction
Down-Counting
TCLKA pin
TCLKB pin
Up-Counting
High
Low
Low
High
Low
High
High
Low
In phase counting mode channel 2 operates as above regardless of the external clock edges
selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0 in
timer control register 2 (TCR2). Phase counting mode takes precedence over these settings.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in TCR2 and the compare
match/input capture settings and interrupt functions of timer I/O control register 2 (TIOR2), timer
interrupt enable register 2 (TIER2), and timer status register 2 (TSR2) remain effective in phase
counting mode.
Bit 5—Flag Direction (FDIR): Designates the setting condition for the overflow flag (OVF) in
timer status register 2 (TSR2). The FDIR designation is valid in all modes in channel 2.
Bit 5
FDIR
Description
0
OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
1
OVF is set to 1 in TSR2 when TCNT2 overflows
(Initial value)
Bit 4—PWM Mode 4 (PWM4): Selects whether channel 4 operates normally or in PWM mode.
Bit 4
PWM4
Description
0
Channel 4 operates normally
1
Channel 4 operates in PWM mode
(Initial value)
When bit PWM4 is set to 1 to select PWM mode, pin TIOCA4 becomes a PWM output pin. The
output goes to 1 at compare match with general register A4 (GRA4), and to 0 at compare match
with general register B4 (GRB4).
If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and
CMD0 in the timer function control register (TFCR), the CMD1 and CMD0 setting takes
precedence and the PWM4 setting is ignored.
185
Bit 3—PWM Mode 3 (PWM3): Selects whether channel 3 operates normally or in PWM mode.
Bit 3
PWM3
Description
0
Channel 3 operates normally
1
Channel 3 operates in PWM mode
(Initial value)
When bit PWM3 is set to 1 to select PWM mode, pin TIOCA3 becomes a PWM output pin. The
output goes to 1 at compare match with general register A3 (GRA3), and to 0 at compare match
with general register B3 (GRB3).
If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and
CMD0 in the timer function control register (TFCR), the CMD1 and CMD0 setting takes
precedence and the PWM3 setting is ignored.
Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.
Bit 2
PWM2
Description
0
Channel 2 operates normally
1
Channel 2 operates in PWM mode
(Initial value)
When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The
output goes to 1 at compare match with general register A2 (GRA2), and to 0 at compare match
with general register B2 (GRB2).
Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.
Bit 1
PWM1
Description
0
Channel 1 operates normally
1
Channel 1 operates in PWM mode
(Initial value)
When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The
output goes to 1 at compare match with general register A1 (GRA1), and to 0 at compare match
with general register B1 (GRB1).
186
Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0
PWM0
Description
0
Channel 0 operates normally
1
Channel 0 operates in PWM mode
(Initial value)
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The
output goes to 1 at compare match with general register A0 (GRA0), and to 0 at compare match
with general register B0 (GRB0).
8.2.4 Timer Function Control Register (TFCR)
TFCR is an 8-bit readable/writable register that selects complementary PWM mode, resetsynchronized PWM mode, and buffering for channels 3 and 4.
Bit
7
6
5
4
3
2
1
0
—
—
CMD1
CMD0
BFB4
BFA4
BFB3
BFA3
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Combination mode 1/0
These bits select complementary
PWM mode or reset-synchronized
PWM mode for channels 3 and 4
Buffer mode B4 and A4
These bits select buffering of
general registers (GRB4 and
GRA4) by buffer registers
(BRB4 and BRA4) in channel 4
Buffer mode B3 and A3
These bits select buffering
of general registers (GRB3
and GRA3) by buffer
registers (BRB3 and BRA3)
in channel 3
TFCR is initialized to H'C0 by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
187
Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels
3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode.
Bit 5
CMD1
Bit 4
CMD0
Description
0
0
Channels 3 and 4 operate normally
(Initial value)
1
1
0
Channels 3 and 4 operate together in complementary PWM mode
1
Channels 3 and 4 operate together in reset-synchronized PWM mode
Before selecting reset-synchronized PWM mode or complementary PWM mode, halt the timer
counter or counters that will be used in these modes.
When these bits select complementary PWM mode or reset-synchronized PWM mode, they take
precedence over the setting of the PWM mode bits (PWM4 and PWM3) in TMDR. Settings of
timer sync bits SYNC4 and SYNC3 in the timer synchro register (TSNC) are valid in
complementary PWM mode and reset-synchronized PWM mode, however. When complementary
PWM mode is selected, channels 3 and 4 must not be synchronized (do not set bits SYNC3 and
SYNC4 both to 1 in TSNC).
Bit 3—Buffer Mode B4 (BFB4): Selects whether GRB4 operates normally in channel 4, or
whether GRB4 is buffered by BRB4.
Bit 3
BFB4
Description
0
GRB4 operates normally
1
GRB4 is buffered by BRB4
(Initial value)
Bit 2—Buffer Mode A4 (BFA4): Selects whether GRA4 operates normally in channel 4, or
whether GRA4 is buffered by BRA4.
Bit 2
BFA4
Description
0
GRA4 operates normally
1
GRA4 is buffered by BRA4
(Initial value)
188
Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or
whether GRB3 is buffered by BRB3.
Bit 1
BFB3
Description
0
GRB3 operates normally
1
GRB3 is buffered by BRB3
(Initial value)
Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or
whether GRA3 is buffered by BRA3.
Bit 0
BFA3
Description
0
GRA3 operates normally
1
GRA3 is buffered by BRA3
(Initial value)
8.2.5 Timer Output Master Enable Register (TOER)
TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3
and 4.
Bit
7
6
5
4
3
2
1
0
—
—
EXB4
EXA4
EB3
EB4
EA4
EA3
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
Master enable TOCXA4, TOCXB4
These bits enable or disable output
settings for pins TOCXA4 and TOCXB4
Master enable TIOCA3, TIOCB3 , TIOCA4, TIOCB4
These bits enable or disable output settings for pins
TIOCA3, TIOCB3 , TIOCA4, and TIOCB4
TOER is initialized to H'FF by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
189
Bit 5—Master Enable TOCXB4 (EXB4): Enables or disables ITU output at pin TOCXB4.
Bit 5
EXB4
Description
0
TOCXB4 output is disabled regardless of TFCR settings (TOCXB4 operates as a generic
input/output pin).
If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in channel 1.
1
TOCXB4 is enabled for output according to TFCR settings
(Initial value)
Bit 4—Master Enable TOCXA4 (EXA4): Enables or disables ITU output at pin TOCXA4.
Bit 4
EXA4
Description
0
TOCXA4 output is disabled regardless of TFCR settings (TOCXA4 operates as a generic
input/output pin).
If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1.
1
TOCXA4 is enabled for output according to TFCR settings
(Initial value)
Bit 3—Master Enable TIOCB3 (EB3): Enables or disables ITU output at pin TIOCB3.
Bit 3
EB3
Description
0
TIOCB3 output is disabled regardless of TIOR3 and TFCR settings (TIOCB3 operates as
a generic input/output pin).
If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
1
TIOCB3 is enabled for output according to TIOR3 and TFCR settings
190
(Initial value)
Bit 2—Master Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB4.
Bit 2
EB4
Description
0
TIOCB4 output is disabled regardless of TIOR4 and TFCR settings (TIOCB4 operates as
a generic input/output pin).
If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.
1
TIOCB4 is enabled for output according to TIOR4 and TFCR settings
(Initial value)
Bit 1—Master Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA4.
Bit 1
EA4
Description
0
TIOCA4 output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA4
operates as a generic input/output pin).
If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1.
1
TIOCA4 is enabled for output according to TIOR4, TMDR, and
TFCR settings
(Initial value)
Bit 0—Master Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA3.
Bit 0
EA3
Description
0
TIOCA3 output is disabled regardless of TIOR3, TMDR, and TFCR settings (TIOCA3
operates as a generic input/output pin).
If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1.
1
TIOCA3 is enabled for output according to TIOR3, TMDR, and
TFCR settings
191
(Initial value)
8.2.6 Timer Output Control Register (TOCR)
TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels.
Bit
7
6
5
4
3
2
1
0
—
—
—
XTGD
—
—
OLS4
OLS3
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
R/W
—
—
R/W
R/W
Reserved bits
Output level select 3, 4
These bits select output
levels in complementary
PWM mode and resetsynchronized PWM mode
Reserved bits
External trigger disable
Selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized
PWM mode
The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode
and reset-synchronized PWM mode. These settings do not affect other modes.
TOCR is initialized to H'FF by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output
in complementary PWM mode and reset-synchronized PWM mode.
Bit 4
XTGD
Description
0
Input capture A in channel 1 is used as an external trigger signal in complementary PWM
mode and reset-synchronized PWM mode.
When an external trigger occurs, bits 5 to 0 in the timer output master enable register
(TOER) are cleared to 0, disabling ITU output.
1
External triggering is disabled
(Initial value)
192
Bits 3 and 2—Reserved: Read-only bits, always read as 1.
Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and
reset-synchronized PWM mode.
Bit 1
OLS4
Description
0
TIOCA3, TIOCA4, and TIOCB4 outputs are inverted
1
TIOCA3, TIOCA4, and TIOCB4 outputs are not inverted
(Initial value)
Bit 0—Output Level Select 3 (OLS3): Selects output levels in complementary PWM mode and
reset-synchronized PWM mode.
Bit 0
OLS3
Description
0
TIOCB3, TOCXA4, and TOCXB4 outputs are inverted
1
TIOCB3, TOCXA4, and TOCXB4 outputs are not inverted
(Initial value)
8.2.7 Timer Counters (TCNT)
TCNT is a 16-bit counter. The ITU has five TCNTs, one for each channel.
Channel
Abbreviation
Function
0
TCNT0
Up-counter
1
TCNT1
2
TCNT2
Phase counting mode: up/down-counter
Other modes: up-counter
3
TCNT3
4
TCNT4
Complementary PWM mode: up/down-counter
Other modes: up-counter
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Each TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The
clock source is selected by bits TPSC2 to TPSC0 in the timer control register (TCR).
193
TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and
an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters in complementary PWM
mode and up-counters in other modes.
TCNT can be cleared to H'0000 by compare match with general register A or B (GRA or GRB) or
by input capture to GRA or GRB (counter clearing function) in the same channel.
When TCNT overflows (changes from H'FFFF to H'0000), the overflow flag (OVF) is set to 1 in
the timer status register (TSR) of the corresponding channel.
When TCNT underflows (changes from H'0000 to H'FFFF), the overflow flag (OVF) is set to 1 in
TSR of the corresponding channel.
The TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either
word access or byte access.
Each TCNT is initialized to H'0000 by a reset and in standby mode.
8.2.8 General Registers (GRA, GRB)
The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel.
Channel
Abbreviation
Function
0
GRA0, GRB0
Output compare/input capture register
1
GRA1, GRB1
2
GRA2, GRB2
3
GRA3, GRB3
4
GRA4, GRB4
Output compare/input capture register; can be buffered by buffer
registers BRA and BRB
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
A general register is a 16-bit readable/writable register that can function as either an output
compare register or an input capture register. The function is selected by settings in the timer I/O
control register (TIOR).
When a general register is used as an output compare register, its value is constantly compared
with the TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set
to 1 in the timer status register (TSR). Compare match output can be selected in TIOR.
194
When a general register is used as an input capture register, rising edges, falling edges, or both
edges of an external input capture signal are detected and the current TCNT value is stored in the
general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The
valid edge or edges of the input capture signal are selected in TIOR.
TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized
PWM mode.
General registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word access or byte access.
General registers are initialized to the output compare function (with no output signal) by a reset
and in standby mode. The initial value is H'FFFF.
8.2.9 Buffer Registers (BRA, BRB)
The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels 3
and 4.
Channel
Abbreviation
Function
3
BRA3, BRB3
Used for buffering
4
BRA4, BRB4
• When the corresponding GRA or GRB functions as an output
compare register, BRA or BRB can function as an output compare
buffer register: the BRA or BRB value is automatically transferred
to GRA or GRB at compare match
• When the corresponding GRA or GRB functions as an input
capture register, BRA or BRB can function as an input capture
buffer register: the GRA or GRB value is automatically transferred
to BRA or BRB at input capture
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
A buffer register is a 16-bit readable/writable register that is used when buffering is selected.
Buffering can be selected independently by bits BFB4, BFA4, BFB3, and BFA3 in TFCR.
The buffer register and general register operate as a pair. When the general register functions as an
output compare register, the buffer register functions as an output compare buffer register. When
the general register functions as an input capture register, the buffer register functions as an input
capture buffer register.
195
The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by
either word or byte access.
Buffer registers are initialized to H'FFFF by a reset and in standby mode.
8.2.10 Timer Control Registers (TCR)
TCR is an 8-bit register. The ITU has five TCRs, one in each channel.
Channel
Abbreviation
Function
0
TCR0
1
TCR1
2
TCR2
TCR controls the timer counter. The TCRs in all channels are
functionally identical. When phase counting mode is selected in
channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to
TPSC0 in TCR2 are ignored.
3
TCR3
4
TCR4
Bit
7
6
5
—
CCLR1
CCLR0
Initial value
1
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
4
3
CKEG1 CKEG0
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Timer prescaler 2 to 0
These bits select the
counter clock
Clock edge 1/0
These bits select external clock edges
Counter clear 1/0
These bits select the counter clear source
Reserved bit
Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects
the edge or edges of external clock sources, and selects how the counter is cleared.
TCR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
196
Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.
Bit 6
CCLR1
Bit 5
CCLR0
Description
0
0
TCNT is not cleared
1
(Initial value)
capture*1
1
TCNT is cleared by GRA compare match or input
0
TCNT is cleared by GRB compare match or input capture*1
1
Synchronous clear: TCNT is cleared in synchronization with other
synchronized timers*2
Notes: 1. TCNT is cleared by compare match when the general register functions as a compare
match register, and by input capture when the general register functions as an input
capture register.
2. Selected in the timer synchro register (TSNC).
Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges
when an external clock source is used.
Bit 4
CKEG1
Bit 3
CKEG0
Description
0
0
Count rising edges
1
Count falling edges
—
Count both edges
1
(Initial value)
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.
Phase counting takes precedence.
197
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Function
0
0
0
Internal clock: ø
1
Internal clock: ø/2
0
Internal clock: ø/4
1
Internal clock: ø/8
0
External clock A: TCLKA input
1
External clock B: TCLKB input
0
External clock C: TCLKC input
1
External clock D: TCLKD input
1
1
0
1
(Initial value)
When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only
falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer
counts the edge or edges selected by bits CKEG1 and CKEG0.
When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to
TPSC0 in TCR2 are ignored. Phase counting takes precedence.
8.2.11 Timer I/O Control Register (TIOR)
TIOR is an 8-bit register. The ITU has five TIORs, one in each channel.
Channel
Abbreviation
Function
0
TIOR0
1
TIOR1
2
TIOR2
TIOR controls the general registers. Some functions differ in PWM
mode. TIOR3 and TIOR4 settings are ignored when complementary
PWM mode or reset-synchronized PWM mode is selected in
channels 3 and 4.
3
TIOR3
4
TIOR4
198
Bit
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
I/O control A2 to A0
These bits select GRA
functions
Reserved bit
I/O control B2 to B0
These bits select GRB functions
Reserved bit
Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture
function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins. If the
output compare function is selected, TIOR also selects the type of output. If input capture is
selected, TIOR also selects the edge or edges of the input capture signal.
TIOR is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
0
0
0
1
1
1
0
GRB is an output
compare register
No output at compare match
0 output at GRB compare
(Initial value)
match*1
0
1 output at GRB compare match*1
1
Output toggles at GRB compare match
(1 output in channel 2)*1, *2
0
1
1
Function
0
GRB is an input
capture register
GRB captures rising edge of input
GRB captures falling edge of input
GRB captures both edges of input
1
Notes: 1. After a reset, the output is 0 until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
199
Bit 3—Reserved: Read-only bit, always read as 1.
Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
0
0
0
1
1
1
0
GRA is an output
compare register
No output at compare match
0 output at GRA compare
(Initial value)
match*1
0
1 output at GRA compare match*1
1
Output toggles at GRA compare match
(1 output in channel 2)*1, *2
0
1
1
Function
GRA is an input
capture register
GRA captures rising edge of input
GRA captures falling edge of input
0
GRA captures both edges of input
1
Notes: 1. After a reset, the output is 0 until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
8.2.12 Timer Status Register (TSR)
TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel
Abbreviation
Function
0
TSR0
Indicates input capture, compare match, and overflow status
1
TSR1
2
TSR2
3
TSR3
4
TSR4
200
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Bit
Reserved bits
Overflow flag
Status flag indicating
overflow or underflow
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
Note: * Only 0 can be written, to clear the flag.
Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in the timer interrupt enable register
(TIER).
TSR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow.
Bit 2
OVF
Description
0
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
(Initial value)
1
[Setting condition]
TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF*
Notes: * TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow occurs
only under the following conditions:
1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR)
2. Channels 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0 in
TFCR)
201
Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB
compare match or input capture events.
Bit 1
IMFB
Description
0
[Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
(Initial value)
1
[Setting conditions]
TCNT = GRB when GRB functions as a compare match register.
TCNT value is transferred to GRB by an input capture signal, when GRB functions as
an input capture register.
Bit 0—Input Capture/Compare Match Flag A (IMFA): This status flag indicates GRA
compare match or input capture events.
Bit 0
IMFA
Description
0
[Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA.
DMAC activated by IMIA interrupt (channels 0 to 3 only).
1
[Setting conditions]
TCNT = GRA when GRA functions as a compare match register.
TCNT value is transferred to GRA by an input capture signal, when GRA functions
as an input capture register.
202
(Initial value)
8.2.13 Timer Interrupt Enable Register (TIER)
TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel
Abbreviation
Function
0
TIER0
Enables or disables interrupt requests.
1
TIER1
2
TIER2
3
TIER3
4
TIER4
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Reserved bits
Overflow interrupt enable
Enables or disables OVF
interrupts
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register compare match and input capture interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: Read-only bits, always read as 1.
203
Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the
overflow flag (OVF) in TSR when OVF is set to 1.
Bit 2
OVIE
Description
0
OVI interrupt requested by OVF is disabled
1
OVI interrupt requested by OVF is enabled
(Initial value)
Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the
interrupt requested by the IMFB flag in TSR when IMFB is set to 1.
Bit 1
IMIEB
Description
0
IMIB interrupt requested by IMFB is disabled
1
IMIB interrupt requested by IMFB is enabled
(Initial value)
Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the
interrupt requested by the IMFA flag in TSR when IMFA is set to 1.
Bit 0
IMIEA
Description
0
IMIA interrupt requested by IMFA is disabled
1
IMIA interrupt requested by IMFA is enabled
204
(Initial value)
8.3 CPU Interface
8.3.1 16-Bit Accessible Registers
The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A
and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data
bus. These registers can be written or read a word at a time, or a byte at a time.
Figures 8-6 and 8-7 show examples of word access to a timer counter (TCNT). Figures 8-8, 8-9,
8-10, and 8-11 show examples of byte access to TCNTH and TCNTL.
On-chip data bus
H
CPU
H
L
Bus interface
L
TCNTH
Module
data bus
TCNTL
Figure 8-6 Access to Timer Counter (CPU Writes to TCNT, Word)
On-chip data bus
H
CPU
L
H
Bus interface
L
TCNTH
TCNTL
Figure 8-7 Access to Timer Counter (CPU Reads TCNT, Word)
205
Module
data bus
On-chip data bus
H
CPU
L
H
Bus interface
L
TCNTH
Module
data bus
TCNTL
Figure 8-8 Access to Timer Counter (CPU Writes to TCNT, Upper Byte)
On-chip data bus
H
CPU
L
H
Bus interface
L
TCNTH
Module
data bus
TCNTL
Figure 8-9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte)
On-chip data bus
H
CPU
L
H
Bus interface
L
TCNTH
TCNTL
Figure 8-10 Access to Timer Counter (CPU Reads TCNT, Upper Byte)
206
Module
data bus
On-chip data bus
H
CPU
H
L
Bus interface
L
TCNTH
Module
data bus
TCNTL
Figure 8-11 Access to Timer Counter (CPU Reads TCNT, Lower Byte)
8.3.2 8-Bit Accessible Registers
The registers other than the timer counters, general registers, and buffer registers are 8-bit
registers. These registers are linked to the CPU by an internal 8-bit data bus.
Figures 8-12 and 8-13 show examples of byte read and write access to a TCR.
If a word-size data transfer instruction is executed, two byte transfers are performed.
On-chip data bus
H
CPU
L
H
Bus interface
L
TCR
Figure 8-12 TCR Access (CPU Writes to TCR)
207
Module
data bus
On-chip data bus
H
CPU
L
H
Bus interface
L
TCR
Figure 8-13 TCR Access (CPU Reads TCR)
208
Module
data bus
8.4 Operation
8.4.1 Overview
A summary of operations in the various modes is given below.
Normal Operation: Each channel has a timer counter and general registers. The timer counter
counts up, and can operate as a free-running counter, periodic counter, or external event counter.
General registers A and B can be used for input capture or output compare.
Synchronous Operation: The timer counters in designated channels are preset synchronously.
Data written to the timer counter in any one of these channels is simultaneously written to the
timer counters in the other channels as well. The timer counters can also be cleared synchronously
if so designated by the CCLR1 and CCLR0 bits in the TCRs.
PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare
match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending
on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB
automatically become output compare registers.
Reset-Synchronized PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with
complementary waveforms. (The three phases are related by having a common transition point.)
When reset-synchronized PWM mode is selected GRA3, GRB3, GRA4, and GRB4 automatically
function as output compare registers, TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and
TOCXB4 function as PWM output pins, and TCNT3 operates as an up-counter. TCNT4 operates
independently, and is not compared with GRA4 or GRB4.
Complementary PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with
non-overlapping complementary waveforms. When complementary PWM mode is selected
GRA3, GRB3, GRA4, and GRB4 automatically function as output compare registers, and
TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 function as PWM output pins.
TCNT3 and TCNT4 operate as up/down-counters.
Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and
TCLKB is detected and TCNT2 counts up or down accordingly. When phase counting mode is
selected TCLKA and TCLKB become clock input pins and TCNT2 operates as an up/downcounter.
209
Buffering
•
If the general register is an output compare register
When compare match occurs the buffer register value is transferred to the general register.
•
If the general register is an input capture register
When input capture occurs the TCNT value is transferred to the general register, and the
previous general register value is transferred to the buffer register.
•
Complementary PWM mode
The buffer register value is transferred to the general register when TCNT3 and TCNT4
change counting direction.
•
Reset-synchronized PWM mode
The buffer register value is transferred to the general register at GRA3 compare match.
8.4.2 Basic Functions
Counter Operation: When one of bits STR0 to STR4 is set to 1 in the timer start register
(TSTR), the timer counter (TCNT) in the corresponding channel starts counting. The counting can
be free-running or periodic.
•
Sample setup procedure for counter
Figure 8-14 shows a sample procedure for setting up a counter.
210
Counter setup
Select counter clock
1
Type of counting?
Free-running counting
Periodic counting
Select counter clear source
2
Select output compare
register function
3
Set period
4
Start counter
5
Start counter
Periodic counter
5
Free-running counter
Figure 8-14 Counter Setup Procedure (Example)
1.
2.
3.
4.
5.
Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock
source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the
external clock signal.
For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA
compare match or GRB compare match.
Set TIOR to select the output compare function of GRA or GRB, whichever was selected in
step 2.
Write the count period in GRA or GRB, whichever was selected in step 2.
Set the STR bit to 1 in TSTR to start the timer counter.
211
•
Free-running and periodic counter operation
A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A
free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When
the count overflows from H'FFFF to H'0000, the overflow flag (OVF) is set to 1 in the timer
status register (TSR). If the corresponding OVIE bit is set to 1 in the timer interrupt enable
register, a CPU interrupt is requested. After the overflow, the counter continues counting up
from H'0000. Figure 8-15 illustrates free-running counting.
TCNT value
H'FFFF
H'0000
Time
STR0 to
STR4 bit
OVF
Figure 8-15 Free-Running Counter Operation
When a channel is set to have its counter cleared by compare match, in that channel TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit
CCLR1 or CCLR0 in the timer control register (TCR) to have the counter cleared by compare
match, and set the count period in GRA or GRB. After these settings, the counter starts
counting up as a periodic counter when the corresponding bit is set to 1 in TSTR. When the
count matches GRA or GRB, the IMFA or IMFB flag is set to 1 in TSR and the counter is
cleared to H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TIER, a CPU
interrupt is requested at this time. After the compare match, TCNT continues counting up
from H'0000. Figure 8-16 illustrates periodic counting.
212
TCNT value
Counter cleared by general
register compare match
GR
Time
H'0000
STR bit
IMF
Figure 8-16 Periodic Counter Operation
•
Count timing
— Internal clock source
Bits TPSC2 to TPSC0 in TCR select the system clock (ø) or one of three internal clock
sources obtained by prescaling the system clock (ø/2, ø/4, ø/8).
Figure 8-17 shows the timing.
ø
Internal
clock
TCNT input
TCNT
N–1
N
Figure 8-17 Count Timing for Internal Clock Sources
213
N+1
— External clock source
Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD),
and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge,
falling edge, or both edges can be selected.
The pulse width of the external clock signal must be at least 1.5 system clocks when a
single edge is selected, and at least 2.5 system clocks when both edges are selected.
Shorter pulses will not be counted correctly.
Figure 8-18 shows the timing when both edges are detected.
ø
External
clock input
TCNT input
TCNT
N–1
N
N+1
Figure 8-18 Count Timing for External Clock Sources (when Both Edges are Detected)
214
Waveform Output by Compare Match: In ITU channels 0, 1, 3, and 4, compare match A or B
can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the
output can only go to 0 or go to 1.
•
Sample setup procedure for waveform output by compare match
Figure 8-19 shows a sample procedure for setting up waveform output by compare match.
Output setup
1. Select the compare match output mode (0, 1, or
toggle) in TIOR. When a waveform output mode
is selected, the pin switches from its generic input/
output function to the output compare function
(TIOCA or TIOCB). An output compare pin outputs
0 until the first compare match occurs.
Select waveform
output mode
1
Set output timing
2
2. Set a value in GRA or GRB to designate the
compare match timing.
Start counter
3
3. Set the STR bit to 1 in TSTR to start the timer
counter.
Waveform output
Figure 8-19 Setup Procedure for Waveform Output by Compare Match (Example)
•
Examples of waveform output
Figure 8-20 shows examples of 0 and 1 output. TCNT operates as a free-running counter, 0
output is selected for compare match A, and 1 output is selected for compare match B. When
the pin is already at the selected output level, the pin level does not change.
215
TCNT value
H'FFFF
GRB
GRA
Time
TIOCB
TIOCA
No change
No change
No change
No change
1 output
0 output
Figure 8-20 0 and 1 Output (Examples)
Figure 8-21 shows examples of toggle output. TCNT operates as a periodic counter, cleared
by compare match B. Toggle output is selected for both compare match A and B.
TCNT value
Counter cleared by compare match with GRB
GRB
GRA
Time
TIOCB
Toggle
output
TIOCA
Toggle
output
Figure 8-21 Toggle Output (Example)
216
•
Output compare timing
The compare match signal is generated in the last state in which TCNT and the general
register match (when TCNT changes from the matching value to the next value). When the
compare match signal is generated, the output value selected in TIOR is output at the output
compare pin (TIOCA or TIOCB). When TCNT matches a general register, the compare
match signal is not generated until the next counter clock pulse.
Figure 8-22 shows the output compare timing.
ø
TCNT input
clock
TCNT
N
GR
N
N+1
Compare
match signal
TIOCA,
TIOCB
Figure 8-22 Output Compare Timing
Input Capture Function: The TCNT value can be captured into a general register when a
transition occurs at an input capture/output compare pin (TIOCA or TIOCB). Capture can take
place on the rising edge, falling edge, or both edges. The input capture function can be used to
measure pulse width or period.
•
Sample setup procedure for input capture
Figure 8-23 shows a sample procedure for setting up input capture.
217
Input selection
Select input-capture input
1
Start counter
2
1. Set TIOR to select the input capture function of a
general register and the rising edge, falling edge,
or both edges of the input capture signal. Clear the
port data direction bit to 0 before making these
TIOR settings.
2. Set the STR bit to 1 in TSTR to start the timer
counter.
Input capture
Figure 8-23 Setup Procedure for Input Capture (Example)
•
Examples of input capture
Figure 8-24 illustrates input capture when the falling edge of TIOCB and both edges of
TIOCA are selected as capture edges. TCNT is cleared by input capture into GRB.
TCNT value
Counter cleared by TIOCB
input (falling edge)
H'0180
H'0160
H'0005
H'0000
Time
TIOCB
TIOCA
GRA
H'0005
H'0160
GRB
H'0180
Figure 8-24 Input Capture (Example)
218
•
Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in
TIOR. Figure 8-25 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system
clocks for capture of both edges.
ø
Input-capture input
Internal input
capture signal
TCNT
N
GRA, GRB
N
Figure 8-25 Input Capture Signal Timing
219
8.4.3 Synchronization
The synchronization function enables two or more timer counters to be synchronized by writing
the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or
more timer counters can also be cleared simultaneously (synchronous clear). Synchronization
enables additional general registers to be associated with a single time base. Synchronization can
be selected for all channels (0 to 4).
Sample Setup Procedure for Synchronization: Figure 8-26 shows a sample procedure for
setting up synchronization.
Setup for synchronization
Select synchronization
1
Synchronous preset
Write to TCNT
Synchronous clear
2
Clearing
synchronized to this
channel?
No
Yes
Synchronous preset
Select counter clear source
3
Select counter clear source
4
Start counter
5
Start counter
5
Counter clear
Synchronous clear
1. Set the SYNC bits to 1 in TSNC for the channels to be synchronized.
2. When a value is written in TCNT in one of the synchronized channels, the same value is
simultaneously written in TCNT in the other channels (synchronized preset).
3. Set the CCLR1 or CCLR0 bit in TCR to have the counter cleared by compare match or input capture.
4. Set the CCLR1 and CCLR0 bits in TCR to have the counter cleared synchronously.
5. Set the STR bits in TSTR to 1 to start the synchronized counters.
Figure 8-26 Setup Procedure for Synchronization (Example)
220
Example of Synchronization: Figure 8-27 shows an example of synchronization. Channels 0, 1,
and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing
by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The
timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by
compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0,
TIOCA1, and TIOCA2. For further information on PWM mode, see section 8.4.4, PWM Mode.
Value of TCNT0 to TCNT2
Cleared by compare match with GRB0
GRB0
GRB1
GRA0
GRB2
GRA1
GRA2
Time
TIOCA0
TIOCA1
TIOCA2
Figure 8-27 Synchronization (Example)
221
8.4.4 PWM Mode
In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.
GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which
the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a
PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can
be selected in all channels (0 to 4).
Table 8-4 summarizes the PWM output pins and corresponding registers. If the same value is set
in GRA and GRB, the output does not change when compare match occurs.
Table 8-4 PWM Output Pins and Registers
Channel
Output Pin
1 Output
0 Output
0
TIOCA0
GRA0
GRB0
1
TIOCA1
GRA1
GRB1
2
TIOCA2
GRA2
GRB2
3
TIOCA3
GRA3
GRB3
4
TIOCA4
GRA4
GRB4
222
Sample Setup Procedure for PWM Mode: Figure 8-28 shows a sample procedure for setting up
PWM mode.
PWM mode
Select counter clock
1
Select counter clear source
2
Set GRA
3
Set GRB
4
Select PWM mode
5
Start counter
6
1. Set bits TPSC2 to TPSC0 in TCR to
select the counter clock source. If an
external clock source is selected, set
bits CKEG1 and CKEG0 in TCR to
select the desired edge(s) of the
external clock signal.
2. Set bits CCLR1 and CCLR0 in TCR
to select the counter clear source.
3. Set the time at which the PWM
waveform should go to 1 in GRA.
4. Set the time at which the PWM
waveform should go to 0 in GRB.
5. Set the PWM bit in TMDR to select
PWM mode. When PWM mode is
selected, regardless of the TIOR
contents, GRA and GRB become
output compare registers specifying
the times at which the PWM
goes to 1 and 0. The TIOCA pin
automatically becomes the PWM
output pin. The TIOCB pin conforms
to the settings of bits IOB1 and IOB0
in TIOR. If TIOCB output is not
desired, clear both IOB1 and IOB0 to 0.
6. Set the STR bit to 1 in TSTR to start
the timer counter.
PWM mode
Figure 8-28 Setup Procedure for PWM Mode (Example)
223
Examples of PWM Mode: Figure 8-29 shows examples of operation in PWM mode. The PWM
waveform is output from the TIOCA pin. The output goes to 1 at compare match with GRA, and
to 0 at compare match with GRB.
In the examples shown, TCNT is cleared by compare match with GRA or GRB. Synchronized
operation and free-running counting are also possible.
TCNT value
Counter cleared by compare match with GRA
GRA
GRB
Time
H'0000
TIOCA
a. Counter cleared by GRA
TCNT value
Counter cleared by compare match with GRB
GRB
GRA
H'0000
Time
TIOCA
b. Counter cleared by GRB
Figure 8-29 PWM Mode (Example 1)
224
Figure 8-30 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%.
If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB,
the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a
higher value than GRA, the duty cycle is 100%.
TCNT value
Counter cleared by compare match with GRB
GRB
GRA
H'0000
Time
TIOCA
Write to GRA
Write to GRA
a. 0% duty cycle
TCNT value
Counter cleared by compare match with GRA
GRA
GRB
H'0000
Time
TIOCA
Write to GRB
Write to GRB
b. 100% duty cycle
Figure 8-30 PWM Mode (Example 2)
225
8.4.5 Reset-Synchronized PWM Mode
In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of
complementary PWM waveforms, all having one waveform transition point in common.
When reset-synchronized PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4,
TIOCB4, and TOCXB4 automatically become PWM output pins, and TCNT3 functions as an upcounter.
Table 8-5 lists the PWM output pins. Table 8-6 summarizes the register settings.
Table 8-5 Output Pins in Reset-Synchronized PWM Mode
Channel
Output Pin
Description
3
TIOCA3
PWM output 1
TIOCB3
PWM output 1´ (complementary waveform to PWM output 1)
TIOCA4
PWM output 2
TOCXA4
PWM output 2´ (complementary waveform to PWM output 2)
TIOCB4
PWM output 3
TOCXB4
PWM output 3´ (complementary waveform to PWM output 3)
4
Table 8-6 Register Settings in Reset-Synchronized PWM Mode
Register
Setting
TCNT3
Initially set to H'0000
TCNT4
Not used (operates independently)
GRA3
Specifies the count period of TCNT3
GRB3
Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3
GRA4
Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4
GRB4
Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4
226
Sample Setup Procedure for Reset-Synchronized PWM Mode: Figure 8-31 shows a sample
procedure for setting up reset-synchronized PWM mode.
Reset-synchronized PWM mode
Stop counter
1
Select counter clock
2
Select counter clear source
3
Select reset-synchronized
PWM mode
4
Set TCNT
5
Set general registers
6
Start counter
7
1. Clear the STR3 bit in TSTR to 0 to
halt TCNT3. Reset-synchronized
PWM mode must be set up while
TCNT3 is halted.
2. Set bits TPSC2 to TPSC0 in TCR to
select the counter clock source for
channel 3. If an external clock source
is selected, select the external clock
edge(s) with bits CKEG1 and CKEG0
in TCR.
3. Set bits CCLR1 and CCLR0 in TCR3
to select GRA3 compare match as
the counter clear source.
4. Set bits CMD1 and CMD0 in TFCR to
select reset-synchronized PWM mode.
TIOCA3, TIOCB3, TIOCA4, TIOCB4,
TOCXA4, and TOCXB4 automatically
become PWM output pins.
5. Preset TCNT3 to H'0000. TCNT4
need not be preset.
6. GRA3 is the waveform period register.
Set the waveform period value in
GRA3. Set transition times of the
PWM output waveforms in GRB3,
GRA4, and GRB4. Set times within
the compare match range of TCNT3.
X ≤ GRA3 (X: setting value)
7. Set the STR3 bit in TSTR to 1 to start
TCNT3.
Reset-synchronized PWM mode
Figure 8-31 Setup Procedure for Reset-Synchronized PWM Mode (Example)
227
Example of Reset-Synchronized PWM Mode: Figure 8-32 shows an example of operation in
reset-synchronized PWM mode. TCNT3 operates as an up-counter in this mode. TCNT4 operates
independently, detached from GRA4 and GRB4. When TCNT3 matches GRA3, TCNT3 is
cleared and resumes counting from H'0000. The PWM outputs toggle at compare match with
GRB3, GRA4, GRB4, and TCNT3 respectively, and all toggle when the counter is cleared.
TCNT3 value
Counter cleared at compare match with GRA3
GRA3
GRB3
GRA4
GRB4
H'0000
Time
TIOCA3
TIOCB3
TIOCA4
TOCXA4
TIOCB4
TOCXB4
Figure 8-32 Operation in Reset-Synchronized PWM Mode (Example)
(when OLS3 = OLS4 = 1)
For the settings and operation when reset-synchronized PWM mode and buffer mode are both
selected, see section 8.4.8, Buffering.
228
8.4.6 Complementary PWM Mode
In complementary PWM mode channels 3 and 4 are combined to output three pairs of
complementary, non-overlapping PWM waveforms.
When complementary PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4,
and TOCXB4 automatically become PWM output pins, and TCNT3 and TCNT4 function as
up/down-counters.
Table 8-7 lists the PWM output pins. Table 8-8 summarizes the register settings.
Table 8-7 Output Pins in Complementary PWM Mode
Channel
Output Pin
Description
3
TIOCA3
PWM output 1
TIOCB3
PWM output 1´ (non-overlapping complementary waveform to PWM
output 1)
TIOCA4
PWM output 2
TOCXA4
PWM output 2´ (non-overlapping complementary waveform to PWM
output 2)
TIOCB4
PWM output 3
TOCXB4
PWM output 3´ (non-overlapping complementary waveform to PWM
output 3)
4
Table 8-8 Register Settings in Complementary PWM Mode
Register
Setting
TCNT3
Initially specifies the non-overlap margin (difference to TCNT4)
TCNT4
Initially set to H'0000
GRA3
Specifies the upper limit value of TCNT3 minus 1
GRB3
Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3
GRA4
Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4
GRB4
Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4
229
Setup Procedure for Complementary PWM Mode: Figure 8-33 shows a sample procedure for
setting up complementary PWM mode.
Complementary PWM mode
Stop counting
1
Select counter clock
2
Select complementary
PWM mode
3
Set TCNTs
4
Set general registers
5
Start counters
6
Complementary PWM mode
1. Clear bits STR3 and STR4 to 0 in
TSTR to halt the timer counters.
Complementary PWM mode must be
set up while TCNT3 and TCNT4 are
halted.
2. Set bits TPSC2 to TPSC0 in TCR to
select the same counter clock source
for channels 3 and 4. If an external
clock source is selected, select the
external clock edge(s) with bits
CKEG1 and CKEG0 in TCR. Do not
select any counter clear source
with bits CCLR1 and CCLR0 in TCR.
3. Set bits CMD1 and CMD0 in TFCR
to select complementary PWM mode.
TIOCA3, TIOCB3, TIOCA4, TIOCB4,
TOCXA4, and TOCXB4 automatically
become PWM output pins.
4. Clear TCNT4 to H'0000. Set the
non-overlap margin in TCNT3. Do not
set TCNT3 and TCNT4 to the same
value.
5. GRA3 is the waveform period
register. Set the upper limit value of
TCNT3 minus 1 in GRA3. Set
transition times of the PWM output
waveforms in GRB3, GRA4, and
GRB4. Set times within the compare
match range of TCNT3 and TCNT4.
T ≤ X (X: initial setting of GRB3,
GRA4, or GRB4. T: initial setting of
TCNT3)
6. Set bits STR3 and STR4 in TSTR to
1 to start TCNT3 and TCNT4.
Note: After exiting complementary PWM mode, to resume operating in complementary
PWM mode, follow the entire setup procedure from step 1 again.
Figure 8-33 Setup Procedure for Complementary PWM Mode (Example)
230
Clearing Complementary PWM Mode: Figure 8-34 shows a sample procedure for clearing
complementary PWM mode.
Complementary PWM mode
Clear complementary mode
Stop counting
1
1. Clear bit CMD1 in TFCR to 0, and set
channels 3 and 4 to normal operating
mode.
2
2. After setting channels 3 and 4 to normal
operating mode, wait at least one clock
count before clearing bits STR3 and
STR4 of TSTR to 0 to stop the counter
operation of TCNT3 and TCNT4.
Normal operation
Figure 8-34 Clearing Procedure for Complementary PWM Mode (Example)
231
Examples of Complementary PWM Mode: Figure 8-35 shows an example of operation in
complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down
from compare match between TCNT3 and GRA3 and counting up from the point at which
TCNT4 underflows. During each up-and-down counting cycle, PWM waveforms are generated by
compare match with general registers GRB3, GRA4, and GRB4. Since TCNT3 is initially set to a
higher value than TCNT4, compare match events occur in the sequence TCNT3, TCNT4, TCNT4,
TCNT3.
TCNT3 and
TCNT4 values
Down-counting starts at compare
match between TCNT3 and GRA3
GRA3
TCNT3
GRB3
GRA4
GRB4
TCNT4
Time
H'0000
TIOCA3
Up-counting starts when
TCNT4 underflows
TIOCB3
TIOCA4
TOCXA4
TIOCB4
TOCXB4
Figure 8-35 Operation in Complementary PWM Mode (Example 1)
(when OLS3 = OLS4 = 1)
232
Figure 8-36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in
complementary PWM mode. In this example the outputs change at compare match with GRB3, so
waveforms with duty cycles of 0% or 100% can be output by setting GRB3 to a value larger than
GRA3. The duty cycle can be changed easily during operation by use of the buffer registers. For
further information see section 8.4.8, Buffering.
TCNT3 and
TCNT4 values
GRA3
GRB3
Time
H'0000
TIOCA3
0% duty cycle
TIOCB3
a. 0% duty cycle
TCNT3 and
TCNT4 values
GRA3
GRB3
Time
H'0000
TIOCA3
TIOCB3
100% duty cycle
b. 100% duty cycle
Figure 8-36 Operation in Complementary PWM Mode (Example 2)
(when OLS3 = OLS4 = 1)
233
In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at the transitions
between up-counting and down-counting. The setting conditions for the IMFA bit in channel 3
and the OVF bit in channel 4 differ from the usual conditions. In buffered operation the buffer
transfer conditions also differ. Timing diagrams are shown in figures 8-37 and 8-38.
TCNT3
N–1
N
N+1
GRA3
N
N–1
N
Flag not set
IMFA
Set to 1
Buffer transfer
signal (BR to GR)
GR
Buffer transfer
No buffer transfer
Figure 8-37 Overshoot Timing
234
Underflow
TCNT4
H'0001
H'0000
Overflow
H'FFFF
H'0000
Flag not set
OVF
Set to 1
Buffer transfer
signal (BR to GR)
GR
Buffer transfer
No buffer transfer
Figure 8-38 Undershoot Timing
In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when
an underflow occurs. When buffering is selected, buffer register contents are transferred to the
general register at compare match A3 during up-counting, and when TCNT4 underflows.
General Register Settings in Complementary PWM Mode: When setting up general registers
for complementary PWM mode or changing their settings during operation, note the following
points.
•
Initial settings
Do not set values from H'0000 to T – 1 (where T is the initial value of TCNT3). After the
counters start and the first compare match A3 event has occurred, however, settings in this
range also become possible.
•
Changing settings
Use the buffer registers. Correct waveform output may not be obtained if a general register is
written to directly.
•
Cautions on changes of general register settings
Figure 8-39 shows six correct examples and one incorrect example.
235
GRA3
GR
H'0000
Not allowed
BR
GR
Figure 8-39 Changing a General Register Setting by Buffer Transfer (Example 1)
— Buffer transfer at transition from up-counting to down-counting
If the general register value is in the range from GRA3 – T + 1 to GRA3, do not transfer a
buffer register value outside this range. Conversely, if the general register value is outside
this range, do not transfer a value within this range. See figure 8-40.
GRA3 + 1
GRA3
Illegal changes
GRA3 – T + 1
GRA3 – T
TCNT3
TCNT4
Figure 8-40 Changing a General Register Setting by Buffer Transfer (Caution 1)
236
— Buffer transfer at transition from down-counting to up-counting
If the general register value is in the range from H'0000 to T – 1, do not transfer a buffer
register value outside this range. Conversely, when a general register value is outside this
range, do not transfer a value within this range. See figure 8-41.
TCNT3
TCNT4
T
T–1
Illegal changes
H'0000
H'FFFF
Figure 8-41 Changing a General Register Setting by Buffer Transfer (Caution 2)
237
— General register settings outside the counting range (H'0000 to GRA3)
Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to
a value outside the counting range. When a buffer register is set to a value outside the
counting range, then later restored to a value within the counting range, the counting
direction (up or down) must be the same both times. See figure 8-42.
GRA3
GR
H'0000
0% duty cycle
100% duty cycle
Output pin
Output pin
BR
GR
Write during down-counting
Write during up-counting
Figure 8-42 Changing a General Register Setting by Buffer Transfer (Example 2)
Settings can be made in this way by detecting GRA3 compare match or TCNT4
underflow before writing to the buffer register.
238
8.4.7 Phase Counting Mode
In phase counting mode the phase difference between two external clock inputs (at the TCLKA
and TCLKB pins) is detected, and TCNT2 counts up or down accordingly.
In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock
input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to
TPSC0, CKEG1, and CKEG0 in TCR2. Settings of bits CCLR1, CCLR0 in TCR2, and settings in
TIOR2, TIER2, TSR2, GRA2, and GRB2 are valid. The input capture and output compare
functions can be used, and interrupts can be generated.
Phase counting is available only in channel 2.
Sample Setup Procedure for Phase Counting Mode: Figure 8-43 shows a sample procedure for
setting up phase counting mode.
Phase counting mode
Select phase counting mode
1
Select flag setting condition
2
Start counter
3
1. Set the MDF bit in TMDR to 1 to select
phase counting mode.
2. Select the flag setting condition with
the FDIR bit in TMDR.
3. Set the STR2 bit to 1 in TSTR to start
the timer counter.
Phase counting mode
Figure 8-43 Setup Procedure for Phase Counting Mode (Example)
239
Example of Phase Counting Mode: Figure 8-44 shows an example of operations in phase
counting mode. Table 8-9 lists the up-counting and down-counting conditions for TCNT2.
In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted.
The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap
must also be at least 1.5 states, and the pulse width must be at least 2.5 states. See figure 8-45.
TCNT2 value
Counting up
Counting down
Time
TCLKB
TCLKA
Figure 8-44 Operation in Phase Counting Mode (Example)
Table 8-9 Up/Down Counting Conditions
Counting Direction
Up-Counting
TCLKB
Down-Counting
High
TCLKA
Low
Phase
difference
Low
High
Phase
difference
High
Low
Low
Pulse width
High
Pulse width
TCLKA
TCLKB
Overlap
Overlap
Phase difference and overlap: at least 1.5 states
Pulse width:
at least 2.5 states
Figure 8-45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
240
8.4.8 Buffering
Buffering operates differently depending on whether a general register is an output compare
register or an input capture register, with further differences in reset-synchronized PWM mode
and complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering
operations under the conditions mentioned above are described next.
•
General register used for output compare
The buffer register value is transferred to the general register at compare match. See
figure 8-46.
Compare match signal
BR
GR
Comparator
TCNT
Figure 8-46 Compare Match Buffering
•
General register used for input capture
The TCNT value is transferred to the general register at input capture. The previous general
register value is transferred to the buffer register.
See figure 8-47.
Input capture signal
BR
GR
Figure 8-47 Input Capture Buffering
241
TCNT
•
Complementary PWM mode
The buffer register value is transferred to the general register when TCNT3 and TCNT4
change counting direction. This occurs at the following two times:
— When TCNT3 matches GRA3
— When TCNT4 underflows
•
Reset-synchronized PWM mode
The buffer register value is transferred to the general register at compare match A3.
Sample Buffering Setup Procedure: Figure 8-48 shows a sample buffering setup procedure.
Buffering
Select general register functions
1
Set buffer bits
2
Start counters
3
1. Set TIOR to select the output compare or input
capture function of the general registers.
2. Set bits BFA3, BFA4, BFB3, and BFB4 in TFCR
to select buffering of the required general registers.
3. Set the STR bits to 1 in TSTR to start the timer
counters.
Buffered operation
Figure 8-48 Buffering Setup Procedure (Example)
242
Examples of Buffering: Figure 8-49 shows an example in which GRA is set to function as an
output compare register buffered by BRA, TCNT is set to operate as a periodic counter cleared by
GRB compare match, and TIOCA and TIOCB are set to toggle at compare match A and B.
Because of the buffer setting, when TIOCA toggles at compare match A, the BRA value is
simultaneously transferred to GRA. This operation is repeated each time compare match A occurs.
Figure 8-50 shows the transfer timing.
TCNT value
Counter cleared by compare match B
GRB
H'0250
H'0200
H'0100
H'0000
Time
BRA
H'0200
GRA
H'0250
H'0200
H'0100
H'0200
H'0100
H'0200
TIOCB
Toggle
output
TIOCA
Toggle
output
Compare match A
Figure 8-49 Register Buffering (Example 1: Buffering of Output Compare Register)
243
ø
n
TCNT
n+1
Compare
match signal
Buffer transfer
signal
N
BR
GR
n
N
Figure 8-50 Compare Match and Buffer Transfer Timing (Example)
244
Figure 8-51 shows an example in which GRA is set to function as an input capture register
buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the
input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because
of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous
GRA value is simultaneously transferred to BRA. Figure 8-52 shows the transfer timing.
TCNT value
Counter cleared by
input capture B
H'0180
H'0160
H'0005
H'0000
Time
TIOCB
TOICA
GRA
H'0005
H'0160
H'0005
BRA
GRB
H'0160
H'0180
Input capture A
Figure 8-51 Register Buffering (Example 2: Buffering of Input Capture Register)
245
ø
TIOC pin
Input capture
signal
TCNT
n
n+1
N
N+1
GR
M
n
n
N
BR
m
M
M
n
Figure 8-52 Input Capture and Buffer Transfer Timing (Example)
246
Figure 8-53 shows an example in which GRB3 is buffered by BRB3 in complementary PWM
mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform
with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and
when TCNT4 underflows.
TCNT3 and
TCNT4 values
TCNT3
H'1FFF
GRA3
GRB3
TCNT4
H'0999
H'0000
BRB3
GRB3
Time
H'1FFF
H'0999
H'0999
H'0999
H'1FFF
H'0999
H'1FFF
H'0999
TIOCA3
TIOCB3
Figure 8-53 Register Buffering (Example 4: Buffering in Complementary PWM Mode)
247
8.4.9 ITU Output Timing
The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external
trigger, or inverted by bit settings in TOCR.
Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is
disabled by clearing a master enable bit to 0 in TOER. An arbitrary value can be output by
appropriate settings of the data register (DR) and data direction register (DDR) of the
corresponding input/output port. Figure 8-54 illustrates the timing of the enabling and disabling of
ITU output by TOER.
T1
T2
T3
ø
Address
TOER address
TOER
ITU output pin
Timer output
ITU output
I/O port
Generic input/output
Figure 8-54 Timing of Disabling of ITU Output by Writing to TOER (Example)
248
Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in
TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture
A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU
output. Figure 8-55 shows the timing.
ø
TIOCA1 pin
Input capture
signal
N
TOER
ITU output
pins
H'C0
N
ITU output
I/O port
Generic
input/output
ITU output
ITU output
ITU output
H'C0
I/O port
Generic
input/output
N: Arbitrary setting (H'C1 to H'FF)
Figure 8-55 Timing of Disabling of ITU Output by External Trigger (Example)
Timing of Output Inversion by TOCR: The output levels in reset-synchronized PWM mode and
complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and
OLS3) in TOCR. Figure 8-56 shows the timing.
T1
T2
T3
ø
Address
TOCR address
TOCR
ITU output pin
Inverted
Figure 8-56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example)
249
8.5 Interrupts
The ITU has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
8.5.1 Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a
compare match signal generated when TCNT matches a general register (GR). The compare
match signal is generated in the last state in which the values match (when TCNT is updated from
the matching count to the next count). Therefore, when TCNT matches a general register, the
compare match signal is not generated until the next timer clock input. Figure 8-57 shows the
timing of the setting of IMFA and IMFB.
ø
TCNT input
clock
TCNT
N
N+1
GR
N
Compare
match signal
IMF
IMI
Figure 8-57 Timing of Setting of IMFA and IMFB by Compare Match
250
Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an
input capture signal. The TCNT contents are simultaneously transferred to the corresponding
general register. Figure 8-58 shows the timing.
ø
Input capture
signal
IMF
N
TCNT
GR
N
IMI
Figure 8-58 Timing of Setting of IMFA and IMFB by Input Capture
Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when TCNT overflows from
H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 8-59 shows the timing.
251
ø
TCNT
H'FFFF
H'0000
Overflow
signal
OVF
OVI
Figure 8-59 Timing of Setting of OVF
8.5.2 Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 8-60 shows the timing.
TSR write cycle
T1
T2
T3
ø
Address
TSR address
IMF, OVF
Figure 8-60 Timing of Clearing of Status Flags
252
8.5.3 Interrupt Sources
Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input
capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all
independently vectored. An interrupt is requested when the interrupt request flag and interrupt
enable bit are both set to 1.
The priority order of the channels can be modified in interrupt priority registers A and B (IPRA
and IPRB). For details see section 5, Interrupt Controller.
Table 8-10 lists the interrupt sources.
Table 8-10 ITU Interrupt Sources
Channel
Interrupt
Source
Description
Priority*
0
IMIA0
Compare match/input capture A0
High
IMIB0
Compare match/input capture B0
OVI0
Overflow 0
IMIA1
Compare match/input capture A1
IMIB1
Compare match/input capture B1
OVI1
Overflow 1
IMIA2
Compare match/input capture A2
IMIB2
Compare match/input capture B2
OVI2
Overflow 2
IMIA3
Compare match/input capture A3
IMIB3
Compare match/input capture B3
OVI3
Overflow 3
IMIA4
Compare match/input capture A4
IMIB4
Compare match/input capture B4
OVI4
Overflow 4
1
2
3
4
Low
Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed
by settings in IPRA and IPRB.
253
8.6 Usage Notes
This section describes contention and other matters requiring special attention during ITU
operations.
Contention between TCNT Write and Clear: If a counter clear signal occurs in the T3 state of a
TCNT write cycle, clearing of the counter takes priority and the write is not performed. See
figure 8-61.
TCNT write cycle
T2
T1
T3
ø
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'0000
Figure 8-61 Contention between TCNT Write and Clear
254
Contention between TCNT Word Write and Increment: If an increment pulse occurs in the T3
state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. See
figure 8-62.
TCNT word write cycle
T1
T2
T3
ø
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
TCNT write data
Figure 8-62 Contention between TCNT Word Write and Increment
255
Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T2
or T3 state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The
TCNT byte that was not written retains its previous value. See figure 8-63, which shows an
increment pulse occurring in the T2 state of a byte write to TCNTH.
TCNTH byte write cycle
T2
T1
T3
ø
TCNTH address
Address
Internal write signal
TCNT input clock
TCNTH
N
M
TCNTH write data
TCNTL
X
X+1
X
Figure 8-63 Contention between TCNT Byte Write and Increment
256
Contention between General Register Write and Compare Match: If a compare match occurs
in the T3 state of a general register write cycle, writing takes priority and the compare match
signal is inhibited. See figure 8-64.
General register write cycle
T2
T1
T3
ø
GR address
Address
Internal write signal
TCNT
N
GR
N
N+1
M
General register write data
Compare match signal
Inhibited
Figure 8-64 Contention between General Register Write and Compare Match
257
Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the T3
state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is
set to 1.The same holds for underflow. See figure 8-65.
TCNT write cycle
T1
T2
T3
ø
Address
TCNT address
Internal write signal
TCNT input clock
Overflow signal
TCNT
H'FFFF
M
TCNT write data
OVF
Figure 8-65 Contention between TCNT Write and Overflow
258
Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T3 state of a general register read cycle, the value before input capture is read.
See figure 8-66.
General register read cycle
T1
T2
T3
ø
GR address
Address
Internal read signal
Input capture signal
GR
X
Internal data bus
M
X
Figure 8-66 Contention between General Register Read and Input Capture
259
Contention between Counter Clearing by Input Capture and Counter Increment: If an input
capture signal and counter increment signal occur simultaneously, the counter is cleared according
to the input capture signal. The counter is not incremented by the increment signal. The value
before the counter is cleared is transferred to the general register. See figure 8-67.
ø
Input capture signal
Counter clear signal
TCNT input clock
N
TCNT
GR
H'0000
N
Figure 8-67 Contention between Counter Clearing by Input Capture and
Counter Increment
260
Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T3 state of a general register write cycle, input capture takes priority and the write to
the general register is not performed. See figure 8-68.
General register write cycle
T1
T2
T3
ø
Address
GR address
Internal write signal
Input capture signal
M
TCNT
GR
M
Figure 8-68 Contention between General Register Write and Input Capture
Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is
cleared in the last state at which the TCNT value matches the general register value, at the time
when this value would normally be updated to the next count. The actual counter frequency is
therefore given by the following formula:
f=
ø
(N + 1)
(f: counter frequency. ø: system clock frequency. N: value set in general register.)
261
Contention between Buffer Register Write and Input Capture: If a buffer register is used for
input capture buffering and an input capture signal occurs in the T3 state of a write cycle, input
capture takes priority and the write to the buffer register is not performed.
See figure 8-69.
Buffer register write cycle
T1
T2
T3
ø
Address
BR address
Internal write signal
Input capture signal
GR
N
X
TCNT value
BR
M
N
Figure 8-69 Contention between Buffer Register Write and Input Capture
262
Note on Synchronous Preset: When channels are synchronized, if a TCNT value is modified by
byte write access, all 16 bits of all synchronized counters assume the same value as the counter
that was addressed.
(Example) When channels 2 and 3 are synchronized
• Byte write to channel 2 or byte write to channel 3
TCNT2
W
X
TCNT3
Y
Z
Upper byte Lower byte
Write A to upper byte
of channel 2
TCNT2
A
X
TCNT3
A
X
Upper byte Lower byte
Write A to lower byte
of channel 3
TCNT2
Y
A
TCNT3
Y
A
Upper byte Lower byte
• Word write to channel 2 or word write to channel 3
TCNT2
W
X
TCNT3
Y
Z
Write AB word to
channel 2 or 3
Upper byte Lower byte
TCNT2
A
B
TCNT3
A
B
Upper byte Lower byte
Note on Setup of Reset-Synchronized PWM Mode and Complementary PWM Mode: When
setting bits CMD1 and CMD0 in TFCR, take the following precautions:
•
Write to bits CMD1 and CMD0 only when TCNT3 and TCNT4 are stopped.
•
Do not switch directly between reset-synchronized PWM mode and complementary PWM
mode. First switch to normal mode (by clearing bit CMD1 to 0), then select resetsynchronized PWM mode or complementary PWM mode.
263
ITU Operating Modes
Table 8-11 (a) ITU Operating Modes (Channel 0)
Register Settings
TSNC
Operating Mode
Synchronization
TMDR
MDF
TFCR
TOCR
TOER
TIOR0
TCR0
FDIR PWM
ResetComple- SynchroOutput
mentary nized
BufferLevel
PWM
PWM
ing
XTGD Select
Master
Enable
IOA
IOB
Clear
Select
Clock
Select
o
Synchronous preset
SYNC0 = 1 —
—
o
—
—
—
—
—
—
o
o
o
PWM mode
o
—
—
PWM0 = 1 —
—
—
—
—
—
—*
o*
o
o
Output compare A
o
—
—
PWM0 = 0 —
—
—
—
—
—
IOA2 = 0
o
Other bits
unrestricted
o
o
Output compare B
o
—
—
o
—
—
—
—
—
—
o
IOB2 = 0
o
Other bits
unrestricted
o
Input capture A
o
—
—
PWM0 = 0 —
—
—
—
—
—
IOA2 = 1
o
Other bits
unrestricted
Input capture B
o
—
—
PWM0 = 0 —
—
—
—
—
—
Counter By compare
clearing match/input
capture A
o
—
—
o
—
—
—
—
—
By compare
match/input
capture B
o
—
—
o
—
—
—
—
Synchronous
clear
SYNC0 = 1 —
—
o
—
—
—
—
o
o
o
IOB2 = 1
o
Other bits
unrestricted
o
—
o
o
CCLR1 = 0 o
CCLR0 = 1
—
—
o
o
CCLR1 = 1 o
CCLR0 = 0
—
—
o
o
CCLR1 = 1 o
CCLR0 = 1
Legend: o Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
264
Table 8-11 (b) ITU Operating Modes (Channel 1)
Register Settings
TSNC
Operating Mode
Synchronization
TMDR
MDF
TFCR
TOCR
TOER
TIOR1
TCR1
FDIR PWM
ResetComple- SynchroOutput
mentary nized
BufferLevel
PWM
PWM
ing
XTGD Select
Master
Enable
IOA
IOB
Clear
Select
Clock
Select
o
Synchronous preset
SYNC1 = 1 —
—
o
—
—
—
—
—
—
o
o
o
PWM mode
o
—
—
PWM1 = 1 —
—
—
—
—
—
—
o*1
o
o
Output compare A
o
—
—
PWM1 = 0 —
—
—
—
—
—
IOA2 = 0
o
Other bits
unrestricted
o
o
Output compare B
o
—
—
o
—
—
—
—
—
—
o
IOB2 = 0
o
Other bits
unrestricted
o
Input capture A
o
—
—
PWM1 = 0 —
—
—
o*2
—
—
IOA2 = 1
o
Other bits
unrestricted
Input capture B
o
—
—
PWM1 = 0 —
—
—
—
—
—
Counter By compare
clearing match/input
capture A
o
—
—
o
—
—
—
—
—
By compare
match/input
capture B
o
—
—
o
—
—
—
—
Synchronous
clear
SYNC1 = 1 —
—
o
—
—
—
—
o
o
o
IOB2 = 1
o
Other bits
unrestricted
o
—
o
o
CCLR1 = 0 o
CCLR0 = 1
—
—
o
o
CCLR1 = 1 o
CCLR0 = 0
—
—
o
o
CCLR1 = 1 o
CCLR0 = 1
Legend: o Setting available (valid). — Setting does not affect this mode.
Notes: 1. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
2. Valid only when channels 3 and 4 are operating in complementary PWM mode or reset-synchronized PWM mode.
265
Table 8-11 (c) ITU Operating Modes (Channel 2)
Register Settings
TSNC
Operating Mode
Synchronization
TMDR
MDF
TFCR
TOCR
TOER
TIOR2
TCR2
FDIR PWM
ResetComple- SynchroOutput
mentary nized
BufferLevel
PWM
PWM
ing
XTGD Select
Master
Enable
IOA
IOB
Clear
Select
Clock
Select
o
Synchronous preset
SYNC2 = 1 o
—
o
—
—
—
—
—
—
o
o
o
PWM mode
o
o
—
PWM2 = 1 —
—
—
—
—
—
—
o*
o
o
Output compare A
o
o
—
PWM2 = 0 —
—
—
—
—
—
IOA2 = 0
o
Other bits
unrestricted
o
o
Output compare B
o
o
—
o
—
—
—
—
—
—
o
IOB2 = 0
o
Other bits
unrestricted
o
Input capture A
o
—
—
PWM2 = 0 —
—
—
—
—
—
IOA2 = 1
o
Other bits
unrestricted
Input capture B
o
—
—
PWM2 = 0 —
—
—
—
—
—
Counter By compare
clearing match/input
capture A
o
o
—
o
—
—
—
—
—
By compare
match/input
capture B
o
o
—
o
—
—
—
—
Synchronous
clear
SYNC2 = 1 o
—
o
—
—
—
o
—
—
—
Phase counting
mode
o
MDF = 1 o
o
o
o
IOB2 = 1
o
Other bits
unrestricted
o
—
o
o
CCLR1 = 0 o
CCLR0 = 1
—
—
o
o
CCLR1 = 1 o
CCLR0 = 0
—
—
—
o
o
CCLR1 = 1 o
CCLR0 = 1
—
—
—
o
o
o
—
Legend: o Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
266
Table 8-11 (d) ITU Operating Modes (Channel 3)
TSNC
TMDR
Register Settings
TFCR
TOCR
ResetOutput
SynchroLevel
nized PWM Buffering XTGD Select
o
o
—
—
CMD1 = 0 o
—
—
CMD1 = 0 o
—
—
Master
Enable
IOA
IOB
Clear
Select
Clock
Select
o*1
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
TOER
TIOR3
TCR3
FDIR
—
—
—
PWM
Complementary
PWM
o
o*3
—
—
o
CMD1 = 0
CMD1 = 0
o
—
—
o
o
—
—
PWM3 = 0 CMD1 = 0
CMD1 = 0
o
—
—
Input capture B
o
—
—
PWM3 = 0 CMD1 = 0
CMD1 = 0
o
—
—
EA3 ignored
Other bits
unrestricted
EA3 ignored
Other bits
unrestricted
—
o*2
IOA2 = 0
o
Other bits
unrestricted
o
IOB2 = 0
Other bits
unrestricted
IOA2 = 1
o
Other bits
unrestricted
o
IOA2 = 1
Other bits
unrestricted
Counter
clearing
By compare
match/input
capture A
By compare
match/input
capture B
Synchronous
clear
Complementary
PWM mode
Reset-synchronized
PWM mode
Buffering
(BRA)
o
—
—
o
o
—
—
o*1
o
o
CCLR1 = 0 o
CCLR0 = 1
o
—
—
o
Illegal setting: o*4
CMD1 = 1
CMD0 = 0
CMD1 = 0
CMD1 = 0
o
—
—
o*1
o
o
CCLR1 = 1 o
CCLR0 = 0
SYNC3 = 1 —
—
o
o
o
—
—
o*1
o
o
CCLR1 = 1 o
CCLR0 = 1
o*3
—
—
—
o*6
o
o
—
—
—
—
—
CMD1 = 1
CMD0 = 0
CMD1 = 1
CMD0 = 1
o
o
Illegal setting:
CMD1 = 1
CMD0 = 0
CMD1 = 1
CMD0 = 0
CMD1 = 1
CMD0 = 1
o
o*6
o
o
—
—
CCLR1 = 0 o*5
CCLR0 = 0
CCLR1 = 0 o
CCLR0 = 1
o
—
—
o
o
o
—
o*1
o
o
o
o
Buffering
(BRB)
o
—
—
o
o
o
BFA3 = 1 —
Other bits
unrestricted
BFB3 = 1 —
Other bits
unrestricted
—
o*1
o
o
o
o
Operating Mode
Synchronous preset
PWM mode
Output compare A
Synchronization
MDF
SYNC3 = 1 —
o
—
o
—
Output compare B
o
Input capture A
PWM3 = 1 CMD1 = 0
PWM3 = 0 CMD1 = 0
o
Legend: o Setting available (valid). — Setting does not affect this mode.
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
3. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
4. The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected.
5. In complementary PWM mode, select the same clock source for channels 3 and 4.
6. Use the input capture A function in channel 1.
267
Table 8-11 (e) ITU Operating Modes (Channel 4)
TSNC
TMDR
Register Settings
TFCR
TOCR
ResetOutput
SynchroLevel
nized PWM Buffering XTGD Select
o
o
—
—
CMD1 = 0 o
—
—
CMD1 = 0 o
—
—
Master
Enable
IOA
IOB
Clear
Select
Clock
Select
o*1
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
TOER
TIOR4
TCR4
FDIR
—
—
—
PWM
Complementary
PWM
o
o*3
—
—
o
CMD1 = 0
CMD1 = 0
o
—
—
o
o
—
—
PWM4 = 0 CMD1 = 0
CMD1 = 0
o
—
—
Input capture B
o
—
—
PWM4 = 0 CMD1 = 0
CMD1 = 0
o
—
—
EA4 ignored
Other bits
unrestricted
EB4 ignored
Other bits
unrestricted
—
o*2
IOA2 = 0
o
Other bits
unrestricted
o
IOB2 = 0
Other bits
unrestricted
IOA2 = 1
o
Other bits
unrestricted
o
IOB2 = 1
Other bits
unrestricted
Counter
clearing
By compare
match/input
capture A
By compare
match/input
capture B
Synchronous
clear
Complementary
PWM mode
Reset-synchronized
PWM mode
Buffering
(BRA)
o
—
—
o
o*4
o
—
—
o*1
o
o
CCLR1 = 0 o
CCLR0 = 1
o
—
—
o
o*4
o
—
—
o*1
o
o
CCLR1 = 1 o
CCLR0 = 0
SYNC4 = 1 —
—
o
o*3
—
—
—
o
—
—
—
o
—
—
Buffering
(BRB)
o
—
—
Operating Mode
Synchronous preset
PWM mode
Output compare A
Synchronization
MDF
SYNC4 = 1 —
o
—
o
—
Output compare B
o
Input capture A
PWM4 = 1 CMD1 = 0
PWM4 = 0 CMD1 = 0
o
Illegal setting:
CMD1 = 1
CMD0 = 0
Illegal setting:
CMD1 = 1
CMD0 = 0
Illegal setting:
CMD1 = 1
CMD0 = 0
CMD1 = 1
CMD0 = 0
CMD1 = 1
CMD0 = 1
o*4
o
—
—
o*1
o
o
CCLR1 = 1 o
CCLR0 = 1
CMD1 = 1
CMD0 = 0
CMD1 = 1
CMD0 = 1
o
o
o
o
—
—
CCLR1 = 0 o*5
CCLR0 = 0
o
o
o
o
—
—
o*6
o*6
o
o
o
—
o*1
o
o
o
o
o
o
o
BFA4 = 1 —
Other bits
unrestricted
BFB4 = 1 —
Other bits
unrestricted
—
o*1
o
o
o
o
Legend: o Setting available (valid). — Setting does not affect this mode.
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
3. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
4. When reset-synchronized PWM mode is selected, TCNT4 operates independently and the counter clearing function is available. Waveform output is not affected.
5. In complementary PWM mode, select the same clock source for channels 3 and 4.
6. TCR4 settings are valid in reset-synchronized PWM mode, but TCNT4 operates independently, without affecting waveform output.
268
Section 9 Programmable Timing Pattern Controller
9.1 Overview
The H8/3032 Series has a built-in programmable timing pattern controller (TPC) that provides
pulse outputs by using the 16-bit integrated timer-pulse unit (ITU) as a time base. The TPC pulse
outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and
independently.
9.1.1 Features
TPC features are listed below.
•
16-bit output data
Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis.
•
Four output groups
Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit
outputs.
•
Selectable output trigger signals
Output trigger signals can be selected for each group from the compare-match signals of four
ITU channels.
•
Non-overlap mode
A non-overlap margin can be provided between pulse outputs.
269
9.1.2 Block Diagram
Figure 9-1 shows a block diagram of the TPC.
ITU compare match signals
Control logic
TP15
TP14
TP13
TP12
TP11
TP10
TP 9
TP 8
TP 7
TP 6
TP 5
TP 4
TP 3
TP 2
TP 1
TP 0
Legend
TPMR:
TPCR:
NDERB:
NDERA:
PBDDR:
PADDR:
NDRB:
NDRA:
PBDR:
PADR:
PADDR
PBDDR
NDERA
NDERB
TPMR
TPCR
Internal
data bus
Pulse output
pins, group 3
PBDR
NDRB
PADR
NDRA
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
TPC output mode register
TPC output control register
Next data enable register B
Next data enable register A
Port B data direction register
Port A data direction register
Next data register B
Next data register A
Port B data register
Port A data register
Figure 9-1 TPC Block Diagram
270
9.1.3 TPC Pins
Table 9-1 summarizes the TPC output pins.
Table 9-1 TPC Pins
Name
Symbol
I/O
Function
TPC output 0
TP0
Output
Group 0 pulse output
TPC output 1
TP1
Output
TPC output 2
TP2
Output
TPC output 3
TP3
Output
TPC output 4
TP4
Output
TPC output 5
TP5
Output
TPC output 6
TP6
Output
TPC output 7
TP7
Output
TPC output 8
TP8
Output
TPC output 9
TP9
Output
TPC output 10
TP10
Output
TPC output 11
TP11
Output
TPC output 12
TP12
Output
TPC output 13
TP13
Output
TPC output 14
TP14
Output
TPC output 15
TP15
Output
Group 1 pulse output
Group 2 pulse output
Group 3 pulse output
271
9.1.4 Registers
Table 9-2 summarizes the TPC registers.
Table 9-2 TPC Registers
Address*1
Name
Abbreviation
R/W
Initial Value
H'FFD1
Port A data direction register
PADDR
W
H'00
H'00
H'FFD3
Port A data register
PADR
R/(W)*2
H'FFD4
Port B data direction register
PBDDR
W
H'00
H'00
H'FFD6
Port B data register
PBDR
R/(W)*2
H'FFA0
TPC output mode register
TPMR
R/W
H'F0
H'FFA1
TPC output control register
TPCR
R/W
H'FF
H'FFA2
Next data enable register B
NDERB
R/W
H'00
H'FFA3
Next data enable register A
NDERA
R/W
H'00
H'FFA5/
H'FFA7*3
Next data register A
NDRA
R/W
H'00
H'FFA4
H'FFA6*3
Next data register B
NDRB
R/W
H'00
Notes: 1. Lower 16 bits of the address.
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFA5 when the same output trigger is selected for TPC output
groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA
address is H'FFA7 for group 0 and H'FFA5 for group 1. Similarly, the address of NDRB
is H'FFA4 when the same output trigger is selected for TPC output groups 2 and 3 by
settings in TPCR. When the output triggers are different, the NDRB address is H'FFA6
for group 2 and H'FFA4 for group 3.
272
9.2 Register Descriptions
9.2.1 Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit
7
6
5
4
3
2
1
0
PA7 DDR PA6 DDR PA5 DDR PA4 DDR PA3 DDR PA2 DDR PA1 DDR PA0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or
output for port A pins
Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must
be set to 1. For further information about PADDR, see section 7.10, Port A.
9.2.2 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
Bit
7
6
5
4
3
2
1
0
PA 7
PA 6
PA 5
PA 4
PA 3
PA 2
PA 1
PA 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
Note: * Bits selected for TPC output by NDERA settings become read-only bits.
For further information about PADR, see section 7.10, Port A.
273
9.2.3 Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Bit
7
6
5
4
3
2
1
0
PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port B data direction 7 to 0
These bits select input or
output for port B pins
Port B is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must
be set to 1. For further information about PBDDR, see section 7.11, Port B.
9.2.4 Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when
these TPC output groups are used.
Bit
7
6
5
4
3
2
1
0
PB 7
PB 6
PB 5
PB 4
PB 3
PB 2
PB 1
PB 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Port B data 7 to 0
These bits store output data
for TPC output groups 2 and 3
Note: * Bits selected for TPC output by NDERB settings become read-only bits.
For further information about PBDR, see section 7.11, Port B.
274
9.2.5 Next Data Register A (NDRA)
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP7 to TP0). During TPC output, when an ITU compare match event specified in
TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of
NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or
different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by
the same compare match event, the NDRA address is H'FFA5. The upper 4 bits belong to group 1
and the lower 4 bits to group 0. Address H'FFA7 consists entirely of reserved bits that cannot be
modified and always read 1.
Address H'FFA5
Bit
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Next data 3 to 0
These bits store the next output
data for TPC output group 0
Address H'FFA7
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
—
Reserved bits
275
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5
and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7
to 4 of address H'FFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFA5
Bit
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Reserved bits
Address H'FFA7
Bit
7
6
5
4
3
2
1
0
—
—
—
—
NDR3
NDR2
NDR1
NDR0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Next data 3 to 0
These bits store the next output
data for TPC output group 0
276
9.2.6 Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP15 to TP8). During TPC output, when an ITU compare match event specified in
TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of
NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or
different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFA4. The upper 4 bits belong to group 3
and the lower 4 bits to group 2. Address H'FFA6 consists entirely of reserved bits that cannot be
modified and always read 1.
Address H'FFA4
Bit
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Next data 11 to 8
These bits store the next output
data for TPC output group 2
Address H'FFA6
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
—
Reserved bits
277
Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered
by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFA4
and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7
to 4 of address H'FFA6 are reserved bits that cannot be modified and always read 1.
Address H'FFA4
Bit
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Reserved bits
Address H'FFA6
Bit
7
6
5
4
3
2
1
0
—
—
—
—
NDR11
NDR10
NDR9
NDR8
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Next data 11 to 8
These bits store the next output
data for TPC output group 2
278
9.2.7 Next Data Enable Register A (NDERA)
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP7 to TP0) on a bit-by-bit basis.
Bit
7
6
5
4
3
2
1
0
NDER1 NDER0
NDER7
NDER6
NDER5
NDER4
NDER3
NDER2
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
If a bit is enabled for TPC output by NDERA, then when the ITU compare match event selected
in the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to
the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is
not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis.
Bits 7 to 0
NDER7 to NDER0
Description
0
TPC outputs TP7 to TP0 are disabled
(NDR7 to NDR0 are not transferred to PA7 to PA0)
1
TPC outputs TP7 to TP0 are enabled
(NDR7 to NDR0 are transferred to PA7 to PA0)
279
(Initial value)
9.2.8 Next Data Enable Register B (NDERB)
NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2
(TP15 to TP8) on a bit-by-bit basis.
Bit
7
6
4
5
3
2
1
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
0
NDER8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 15 to 8
These bits enable or disable
TPC output groups 3 and 2
If a bit is enabled for TPC output by NDERB, then when the ITU compare match event selected in
the TPC output control register (TPCR) occurs, the NDRB value is automatically transferred to
the corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is
not transferred from NDRB to PBDR and the output value does not change.
NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC
output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis.
Bits 7 to 0
NDER15 to NDER8
Description
0
TPC outputs TP15 to TP8 are disabled
(NDR15 to NDR8 are not transferred to PB7 to PB0)
1
TPC outputs TP15 to TP8 are enabled
(NDR15 to NDR8 are transferred to PB7 to PB0)
280
(Initial value)
9.2.9 TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit
7
6
5
4
3
2
0
1
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match
Group 2 compare
event that triggers
TPC output group 3 match select 1 and 0
These bits select
(TP15 to TP12 )
the compare match
event that triggers Group 1 compare
TPC output group 2 match select 1 and 0
These bits select
(TP11 to TP8 )
the compare match
event that triggers Group 0 compare
TPC output group 1 match select 1 and 0
These bits select
(TP7 to TP4 )
the compare match
event that triggers
TPC output group 0
(TP3 to TP0 )
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
281
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP15 to TP12).
Bit 7
G3CMS1
Bit 6
G3CMS0
0
0
TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU
channel 0
1
TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU
channel 1
0
TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU
channel 2
1
TPC output group 3 (TP15 to TP12) is triggered by
compare match in ITU channel 3
1
Description
(Initial value)
Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits
select the compare match event that triggers TPC output group 2 (TP11 to TP8).
Bit 5
G2CMS1
Bit 4
G2CMS0
0
0
TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU
channel 0
1
TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU
channel 1
0
TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU
channel 2
1
TPC output group 2 (TP11 to TP8) is triggered by
compare match in ITU channel 3
1
Description
282
(Initial value)
Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match event that triggers TPC output group 1 (TP7 to TP4).
Bit 3
G1CMS1
Bit 2
G1CMS0
0
0
TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU
channel 0
1
TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU
channel 1
0
TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU
channel 2
1
TPC output group 1 (TP7 to TP4) is triggered by
compare match in ITU channel 3
1
Description
(Initial value)
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match event that triggers TPC output group 0 (TP3 to TP0).
Bit 1
G0CMS1
Bit 0
G0CMS0
0
0
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU
channel 0
1
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU
channel 1
0
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU
channel 2
1
TPC output group 0 (TP3 to TP0) is triggered by
compare match in ITU channel 3
1
Description
283
(Initial value)
9.2.10 TPC Output Mode Register (TPMR)
TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for
each group.
Bit
7
6
5
4
—
—
—
—
3
2
G3NOV G2NOV
1
0
G1NOV G0NOV
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Reserved bits
Group 3 non-overlap
Selects non-overlapping TPC
output for group 3 (TP15 to TP12 )
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP11 to TP8 )
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP7 to TP4 )
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP3 to TP0 )
The output trigger period of a non-overlapping TPC output waveform is set in general register B
(GRB) in the ITU channel selected for output triggering. The non-overlap margin is set in general
register A (GRA). The output values change at compare match A and B. For details see
section 9.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
284
Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for
group 3 (TP15 to TP12).
Bit 3
G3NOV
Description
0
Normal TPC output in group 3 (output values change at
compare match A in the selected ITU channel)
1
Non-overlapping TPC output in group 3 (independent 1 and 0 output at
compare match A and B in the selected ITU channel)
(Initial value)
Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for
group 2 (TP11 to TP8).
Bit 2
G2NOV
Description
0
Normal TPC output in group 2 (output values change at
compare match A in the selected ITU channel)
1
Non-overlapping TPC output in group 2 (independent 1 and 0 output at
compare match A and B in the selected ITU channel)
(Initial value)
Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for
group 1 (TP7 to TP4).
Bit 1
G1NOV
Description
0
Normal TPC output in group 1 (output values change at
compare match A in the selected ITU channel)
1
Non-overlapping TPC output in group 1 (independent 1 and 0 output at
compare match A and B in the selected ITU channel)
(Initial value)
Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for
group 0 (TP3 to TP0).
Bit 0
G0NOV
Description
0
Normal TPC output in group 0 (output values change at
compare match A in the selected ITU channel)
1
Non-overlapping TPC output in group 0 (independent 1 and 0 output at
compare match A and B in the selected ITU channel)
285
(Initial value)
9.3 Operation
9.3.1 Overview
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 9-2 illustrates the TPC output operation. Table 9-3 summarizes the TPC operating
conditions.
DDR
NDER
Q
Q
Output trigger signal
C
Q
DR
D
Q NDR
D
Internal
data bus
TPC output pin
Figure 9-2 TPC Output Operation
Table 9-3 TPC Operating Conditions
NDER
DDR
Pin Function
0
0
Generic input port
1
Generic output port
0
Generic input port (but the DR bit is a read-only bit, and when compare
match occurs, the NDR bit value is transferred to the DR bit)
1
TPC pulse output
1
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see
section 9.3.4, Non-Overlapping TPC Output.
286
9.3.2 Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when
the selected compare match event occurs. Figure 9-3 shows the timing of these operations for the
case of normal output in groups 2 and 3, triggered by compare match A.
ø
TCNT
N
N+1
GRA
N
Compare
match A signal
NDRB
n
PBDR
m
n
TP8 to TP15
m
n
Figure 9-3 Timing of Transfer of Next Data Register Contents and Output (Example)
287
9.3.3 Normal TPC Output
Sample Setup Procedure for Normal TPC Output: Figure 9-4 shows a sample procedure for
setting up normal TPC output.
Normal TPC output
Select GR functions
1
Set GRA value
2
Select counting operation
3
Select interrupt request
4
Set initial output data
5
Select port output
6
Enable TPC output
7
Select TPC output trigger
8
Set next TPC output data
9
Start counter
10
ITU setup
Port and
TPC setup
ITU setup
Compare match?
1.
Set TIOR to make GRA an output compare
register (with output inhibited).
2. Set the TPC output trigger period.
3. Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
4. Enable the IMFA interrupt in TIER.
5. Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
6. Set the DDR bits of the input/output port
pins to be used for TPC output to 1.
7. Set the NDER bits of the pins to be used for
TPC output to 1.
8. Select the ITU compare match event to be
used as the TPC output trigger in TPCR.
9. Set the next TPC output values in the NDR bits.
10. Set the STR bit to 1 in TSTR to start the
timer counter.
11. At each IMFA interrupt, set the next output
values in the NDR bits.
No
Yes
Set next TPC output data
11
Figure 9-4 Setup Procedure for Normal TPC Output (Example)
288
Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 9-5 shows an
example in which the TPC is used for cyclic five-phase pulse output.
TCNT value
Compare match
TCNT
GRA
Time
H'0000
NDRB
80
PBDR
00
C0
80
40
C0
60
40
20
60
30
20
10
30
18
10
08
18
88
08
80
88
C0
80
40
C0
TP15
TP14
TP13
TP12
TP11
•
•
•
•
The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare
register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt.
H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRB.
The timer counter in this ITU channel is started. When compare match A occurs, the NDRB contents
are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt service routine
writes the next output data (H'C0) in NDRB.
Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts.
Figure 9-5 Normal TPC Output Example (Five-Phase Pulse Output)
289
9.3.4 Non-Overlapping TPC Output
Sample Setup Procedure for Non-Overlapping TPC Output: Figure 9-6 shows a sample
procedure for setting up non-overlapping TPC output.
Non-overlapping
TPC output
Select GR functions
1
Set GR values
2
Select counting operation
3
Select interrupt requests
4
Set initial output data
5
Set up TPC output
6
Enable TPC transfer
7
Select TPC transfer trigger
8
Select non-overlapping groups
9
Set next TPC output data
10
Start counter
11
ITU setup
Port and
TPC setup
ITU setup
Compare match A?
1. Set TIOR to make GRA and GRB output
compare registers (with output inhibited).
2. Set the TPC output trigger period in GRB
and the non-overlap margin in GRA.
3. Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
4. Enable the IMFA interrupt in TIER.
5. Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
6. Set the DDR bits of the input/output port pins
to be used for TPC output to 1.
7. Set the NDER bits of the pins to be used for
TPC output to 1.
8. In TPCR, select the ITU compare match
event to be used as the TPC output trigger.
9. In TPMR, select the groups that will operate
in non-overlap mode.
10. Set the next TPC output values in the NDR
bits.
11. Set the STR bit to 1 in TSTR to start the timer
counter.
12. At each IMFA interrupt, write the next output
value in the NDR bits.
No
Yes
Set next TPC output data
12
Figure 9-6 Setup Procedure for Non-Overlapping TPC Output (Example)
290
Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 9-7 shows an example of the use of TPC output for four-phase
complementary non-overlapping pulse output.
TCNT value
GRB
TCNT
GRA
H'0000
Time
NDRB
95
PBDR
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
65
Non-overlap margin
TP15
TP14
TP13
TP12
TP11
TP10
TP9
TP8
• The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output
compare registers and the counter will be cleared by compare match B. The TPC output trigger
period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable
IMFA interrupts.
• H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set
Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is
written in NDRB.
• The timer counter in this ITU channel is started. When compare match B occurs, outputs change from
1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.
• Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…
at successive IMFA interrupts.
Figure 9-7 Non-Overlapping TPC Output Example (Four-Phase Complementary
Non-Overlapping Pulse Output)
291
9.3.5 TPC Output Triggering by Input Capture
TPC output can be triggered by ITU input capture as well as by compare match. If GRA functions
as an input capture register in the ITU channel selected in TPCR, TPC output will be triggered by
the input capture signal. Figure 9-8 shows the timing.
ø
TIOC pin
Input capture
signal
N
NDR
DR
M
N
Figure 9-8 TPC Output Triggering by Input Capture (Example)
292
9.4 Usage Notes
9.4.1 Operation of TPC Output Pins
TP0 to TP15 are multiplexed with ITU pin functions. When ITU output is enabled, the
corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits
takes place, however, regardless of the usage of the pin.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
9.4.2 Note on Non-Overlapping Output
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as
follows.
1.
NDR bits are always transferred to DR bits at compare match A.
2.
At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 9-9 illustrates the non-overlapping TPC output operation.
DDR
NDER
Q
Q
Compare match A
Compare match B
C
Q
DR
D
Q NDR
TPC output pin
Figure 9-9 Non-Overlapping TPC Output
293
D
Internal
data bus
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. NDR contents should not be altered during the interval from compare match B
to compare match A (the non-overlap margin).
This can be accomplished by having the IMFA interrupt service routine write the next data in
NDR, or by having the IMFA interrupt activate the DMAC. The next data must be written before
the next compare match B occurs.
Figure 9-10 shows the timing relationships.
Compare
match A
Compare
match B
NDR write
NDR write
NDR
DR
0 output
0/1 output
0 output
Write to NDR
in this interval
Do not write
to NDR in this
interval
0/1 output
Write to NDR
in this interval
Do not write
to NDR in this
interval
Figure 9-10 Non-Overlapping Operation and NDR Write Timing
294
Section 10 Watchdog Timer
10.1 Overview
The H8/3032 Series has an on-chip watchdog timer (WDT). The WDT has two selectable
functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an
interval timer. As a watchdog timer, it generates a reset signal for the H8/3032 Series chip if a
system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval
timer operation, an interval timer interrupt is requested at each TCNT overflow.
10.1.1 Features
WDT features are listed below.
•
Selection of eight counter clock sources
ø/2, ø/32, ø/64, ø/128, ø/256, ø/512, ø/2048, or ø/4096
•
Interval timer option
•
Timer counter overflow generates a reset signal or interrupt.
The reset signal is generated in watchdog timer operation. An interval timer interrupt is
generated in interval timer operation.
•
Watchdog timer reset signal resets the entire H8/3032 Series internally, and can also be output
externally.
The reset signal generated by timer counter overflow during watchdog timer operation resets
the entire H8/3032 Series internally. An external reset signal can be output from the RESO
pin to reset other system devices simultaneously.
295
10.1.2 Block Diagram
Figure 10-1 shows a block diagram of the WDT.
Overflow
TCNT
Interrupt signal
(interval timer)
Interrupt
control
TCSR
Read/
write
control
Internal
data bus
Internal clock sources
ø/2
RSTCSR
ø/32
Reset
(internal, external)
Reset control
ø/64
Clock
Clock
selector
ø/128
ø/256
ø/512
Legend
TCNT:
Timer counter
TCSR:
Timer control/status register
RSTCSR: Reset control/status register
ø/2048
ø/4096
Figure 10-1 WDT Block Diagram
10.1.3 Pin Configuration
Table 10-1 describes the WDT output pin.
Table 10-1 WDT Pin
Name
Abbreviation
I/O
Function
Reset output
RESO
Output*
External output of the watchdog timer reset signal
Note: * Open-drain output.
296
10.1.4 Register Configuration
Table 10-2 summarizes the WDT registers.
Table 10-2 WDT Registers
Address*1
Write*2
H'FFA8
H'FFAA
Read
Name
Abbreviation
R/W
Initial Value
H'18
H'FFA8
Timer control/status register
TCSR
R/(W)*3
H'FFA9
Timer counter
TCNT
R/W
H'00
RSTCSR
R/(W)*3
H'3F
H'FFAB
Reset control/status register
Notes: 1. Lower 16 bits of the address.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7, to clear the flag.
297
10.2 Register Descriptions
10.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable and writable* up-counter.
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when
the TME bit is cleared to 0.
Note: * TCNT is write-protected by a password. For details see section 10.2.4, Notes on Register
Access.
298
10.2.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and writable*1 register. Its functions include selecting the timer mode
and clock source.
Bit
7
6
5
4
3
2
1
0
OVF
WT/IT
TME
—
—
CKS2
CKS1
CKS0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/(W)*2
R/W
R/W
—
—
R/W
R/W
R/W
Clock select
These bits select the
TCNT clock source
Reserved bits
Timer enable
Selects whether TCNT runs or halts
Timer mode select
Selects the mode
Overflow flag
Status flag indicating overflow
Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a
reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.
Notes: 1. TCSR is write-protected by a password. For details see section 10.2.4, Notes on
Register Access.
2. Only 0 can be written, to clear the flag.
299
Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed
from H'FF to H'00.
Bit 7
OVF
0
1
Description
[Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 in OVF
(Initial value)
[Setting condition]
Set when TCNT changes from H'FF to H'00
Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when
TCNT overflows.
Bit 6
WT/IT
Description
0
Interval timer: requests interval timer interrupts
1
Watchdog timer: generates a reset signal
(Initial value)
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5
TME
Description
0
TCNT is initialized to H'00 and halted
1
TCNT is counting
(Initial value)
Bits 4 and 3—Reserved: Read-only bits, always read as 1.
300
Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock
sources, obtained by prescaling the system clock (ø), for input to TCNT.
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
0
ø/2
1
ø/32
0
ø/64
1
ø/128
0
ø/256
1
ø/512
0
ø/2048
1
ø/4096
1
1
0
1
(Initial value)
10.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable*1 register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Bit
7
6
5
4
3
2
1
0
WRST
RSTOE
—
—
—
—
—
—
Initial value
0
0
1
1
1
1
1
1
Read/Write
R/(W)*2
R/W
—
—
—
—
—
—
Reserved bits
Reset output enable
Enables or disables external output of the reset signal
Watchdog timer reset
Indicates that a reset signal has been generated
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Notes: 1. RSTCSR is write-protected by a password. For details see section 10.2.4, Notes on
Register Access.
2. Only 0 can be written in bit 7, to clear the flag.
301
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3003
chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices.
Bit 7
WRST
0
1
Description
[Clearing condition]
Cleared to 0 by reset signal input at RES pin, or by writing 0
(Initial value)
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of
the reset signal generated if TCNT overflows during watchdog timer operation.
Bit 6
RSTOE
Description
0
Reset signal is not output externally
1
Reset signal is output externally
(Initial value)
Bits 5 to 0—Reserved: Read-only bits, always read as 1.
302
10.2.4 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte instructions. Figure 10-2 shows the format of data written to
TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be
contained in the lower byte of the written word. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT
or TCSR.
15
TCNT write
Address
H'FFA8*
H'5A
15
TCSR write
Address
8 7
H'FFA8*
0
Write data
8 7
H'A5
0
Write data
Note: * Lower 16 bits of the address.
Figure 10-2 Format of Data Written to TCNT and TCSR
303
Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be
written by byte transfer instructions. Figure 10-3 shows the format of data written to RSTCSR. To
write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower
byte. The H'00 in the lower byte clears the WRST bit in RSTCSR to 0. To write to the RSTOE bit,
the upper byte must contain H'5A and the lower byte must contain the write data. Writing this
word transfers a write data value into the RSTOE bit.
Writing 0 in WRST bit
Address
H'FFAA*
Writing to RSTOE bit
Address
15
8 7
H'A5
15
H'FFAA*
0
Write data
8 7
H'5A
0
Write data
Note: * Lower 16 bits of the address.
Figure 10-3 Format of Data Written to RSTCSR
Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Byte access
instructions can be used. The read addresses are H'FFA8 for TCSR, H'FFA9 for TCNT, and
H'FFAB for RSTCSR, as listed in table 10-3.
Table 10-3 Read Addresses of TCNT, TCSR, and RSTCSR
Address*
Register
H'FFA8
TCSR
H'FFA9
TCNT
H'FFAB
RSTCSR
Note: * Lower 16 bits of the address.
304
10.3 Operation
Operations when the WDT is used as a watchdog timer and as an interval timer are described
below.
10.3.1 Watchdog Timer Operation
Figure 10-4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and
overflows due to a system crash etc., the H8/3032 Series is internally reset for a duration of 518
states.
The watchdog reset signal can be externally output from the RESO pin to reset external system
devices. The reset signal is output externally for 132 states. External output can be enabled or
disabled by the RSTOE bit in RSTCSR.
A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can
distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR.
If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.
WDT overflow
H'FF
TME set to 1
TCNT count
value
H'00
OVF = 1
Start
Internal
reset signal
H'00 written
in TCNT
Reset
518 states
RESO
132 states
Figure 10-4 Watchdog Timer Operation
305
H'00 written
in TCNT
10.3.2 Interval Timer Operation
Figure 10-5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit
WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each
TCNT overflow. This function can be used to generate interval timer interrupts at regular
intervals.
H'FF
TCNT
count value
Time t
H'00
WT/ IT = 0
TME = 1
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
Figure 10-5 Interval Timer Operation
306
10.3.3 Timing of Setting of Overflow Flag (OVF)
Figure 10-6 shows the timing of setting of the OVF flag in TCSR. The OVF flag is set to 1 when
TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an
interval timer interrupt is generated in interval timer operation.
ø
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 10-6 Timing of Setting of OVF
307
10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)
The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 10-7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is
generated for the entire H8/3032 Series chip. This internal reset signal clears OVF to 0, but the
WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
ø
H'FF
TCNT
H'00
Overflow signal
OVF
WDT internal
reset
WRST
Figure 10-7 Timing of Setting of WRST Bit and Internal Reset
308
10.4 Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
10.5 Usage Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated
during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not
incremented. See figure 10-8.
Write cycle: CPU writes to TCNT
T1
T2
T3
ø
TCNT
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 10-8 Contention between TCNT Write and Increment
Changing CKS2 to CKS0 Values: Halt TCNT by clearing the TME bit to 0 in TCSR before
changing the values of bits CKS2 to CKS0.
309
310
Section 11 Serial Communication Interface
11.1 Overview
The H8/3032 Series has a serial communication interface (SCI). The SCI can communicate in
asynchronous mode or synchronous mode, and has a multiprocessor communication function for
serial communication among two or more processors.
11.1.1 Features
SCI features are listed below.
•
Selection of asynchronous or synchronous mode for serial communication
a.
Asynchronous mode
Serial data communication is synchronized one character at a time. The SCI can communicate
with a universal asynchronous receiver/transmitter (UART), asynchronous communication
interface adapter (ACIA), or other chip that employs standard asynchronous serial
communication. It can also communicate with two or more other processors using the
multiprocessor communication function. There are twelve selectable serial data
communication formats.
—
—
—
—
—
—
b.
Data length:
Stop bit length:
Parity bit:
Multiprocessor bit:
Receive error detection:
Break detection:
7 or 8 bits
1 or 2 bits
even, odd, or none
1 or 0
parity, overrun, and framing errors
by reading the RxD level directly when a framing error occurs
Synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can communicate
with other chips having a synchronous communication function. There is one serial data
communication format.
— Data length:
8 bits
— Receive error detection: overrun errors
311
•
Full duplex communication
The transmitting and receiving sections are independent, so the SCI can transmit and receive
simultaneously. The transmitting and receiving sections are both double-buffered, so serial
data can be transmitted and received continuously.
•
Built-in baud rate generator with selectable bit rates
•
Selectable transmit/receive clock sources: internal clock from baud rate generator, or external
clock from the SCK pin.
•
Four types of interrupts
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are
requested independently.
312
11.1.2 Block Diagram
Bus interface
Figure 11-1 shows a block diagram of the SCI.
Module data bus
RxD
RDR
TDR
RSR
TSR
BRR
SSR
SCR
SMR
Baud rate
generator
Transmit/
receive control
TxD
Parity generate
Parity check
SCK
ø
ø/4
ø/16
ø/64
Clock
External clock
TEI
TXI
RXI
ERI
Legend
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
Figure 11-1 SCI Block Diagram
313
Internal
data bus
11.1.3 Input/Output Pins
The SCI has serial pins for each channel as listed in table 11-1.
Table 11-1 SCI Pins
Name
Abbreviation
I/O
Function
Serial clock pin
SCK
Input/output
SCI clock input/output
Receive data pin
RxD
Input
SCI receive data input
Transmit data pin
TxD
Output
SCI transmit data output
11.1.4 Register Configuration
The SCI has internal registers as listed in table 11-2. These registers select asynchronous or
synchronous mode, specify the data format and bit rate, and control the transmitter and receiver
sections.
Table 11-2 Registers
Channel
Address*1
Name
Abbreviation
R/W
Initial Value
0
H'FFB0
Serial mode register
SMR
R/W
H'00
H'FFB1
Bit rate register
BRR
R/W
H'FF
H'FFB2
Serial control register
SCR
R/W
H'00
H'FFB3
Transmit data register
TDR
R/W
H'FF
H'FFB4
Serial status register
SSR
R/(W)*2
H'84
H'FFB5
Receive data register
RDR
R
H'00
H'FFB8
Serial mode register
SMR
R/W
H'00
H'FFB9
Bit rate register
BRR
R/W
H'FF
H'FFBA
Serial control register
SCR
R/W
H'00
H'FFBB
Transmit data register
TDR
R/W
H'FF
H'FFBC
Serial status register
SSR
R/(W)*2
H'84
H'FFBD
Receive data register
RDR
R
H'00
1
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
314
11.2 Register Descriptions
11.2.1 Receive Shift Register (RSR)
RSR is the register that receives serial data.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value
Read/Write
The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first,
thereby converting the data to parallel data. When 1 byte has been received, it is automatically
transferred to RDR. The CPU cannot read or write RSR directly.
11.2.2 Receive Data Register (RDR)
RDR is the register that stores received serial data.
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
When the SCI finishes receiving 1 byte of serial data, it transfers the received data from RSR into
RDR for storage. RSR is then ready to receive the next data. This double buffering allows data to
be received continuously.
RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to
H'00 by a reset and in standby mode.
315
11.2.3 Transmit Shift Register (TSR)
TSR is the register that transmits serial data.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value
Read/Write
The SCI loads transmit data from TDR into TSR, then transmits the data serially from the TxD
pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next
transmit data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR,
however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write TSR
directly.
11.2.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for serial transmission.
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into
TSR and starts serial transmission. Continuous serial transmission is possible by writing the next
transmit data in TDR during serial transmission from TSR.
The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby
mode.
316
11.2.5 Serial Mode Register (SMR)
SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock
source for the baud rate generator.
Bit
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock select 1/0
These bits select the
baud rate generator’s
clock source
Multiprocessor mode
Selects the multiprocessor
function
Stop bit length
Selects the stop bit length
Parity mode
Selects even or odd parity
Parity enable
Selects whether a parity bit is added
Character length
Selects character length in asynchronous mode
Communication mode
Selects asynchronous or synchronous mode
The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby
mode.
317
Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or
synchronous mode.
Bit 7
C/A
Description
0
Asynchronous mode
1
Synchronous mode
(Initial value)
Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In
synchronous mode the data length is 8 bits regardless of the CHR setting.
Bit 6
CHR
Description
0
8-bit data
1
7-bit data*
(Initial value)
Note: * When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted.
Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a
parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode
the parity bit is neither added nor checked, regardless of the PE setting.
Bit 5
PE
Description
0
Parity bit not added or checked
1
Parity bit added and checked*
(Initial value)
Note: * When PE is set to 1, an even or odd parity bit is added to transmit data according to the
even or odd parity mode selected by the O/E bit, and the parity bit in receive data is
checked to see that it matches the even or odd mode selected by the O/E bit.
318
Bit 4—Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is valid in
asynchronous mode when the PE bit is set to 1 to enable the adding and checking of a parity bit.
The O/E setting is ignored in synchronous mode, or when parity adding and checking is disabled
in asynchronous mode.
Bit 4
O/E
Description
0
Even parity*1
1
Odd
(Initial value)
parity*2
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even
number of 1s in the transmitted character and parity bit combined. Receive data must
have an even number of 1s in the received character and parity bit combined.
2. When odd parity is selected, the parity bit added to transmit data makes an odd number
of 1s in the transmitted character and parity bit combined. Receive data must have an
odd number of 1s in the received character and parity bit combined.
Bit 3—Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting
is used only in asynchronous mode. In synchronous mode no stop bit is added, so the STOP bit
setting is ignored.
Bit 3
STOP
Description
0
One stop bit*1
1
Two stop
(Initial value)
bits*2
Notes: 1. One stop bit (with value 1) is added at the end of each transmitted character.
2. Two stop bits (with value 1) are added at the end of each transmitted character.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1 it is treated as a stop bit. If the second stop bit is 0 it is treated as the start bit of the
next incoming character.
319
Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is
valid only in asynchronous mode. It is ignored in synchronous mode.
For further information on the multiprocessor communication function, see section 11.3.3,
Multiprocessor Communication Function.
Bit 2
MP
Description
0
Multiprocessor function disabled
1
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1/0): These bits select the clock source of the on-chip
baud rate generator. Four clock sources are available: ø, ø/4, ø/16, and ø/64.
For the relationship between the clock source, bit rate register setting, and baud rate, see
section 11.2.8, Bit Rate Register.
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
ø
0
1
ø/4
1
0
ø/16
1
1
ø/64
(Initial value)
320
11.2.6 Serial Control Register (SCR)
SCR enables the SCI transmitter and receiver, enables or disables serial clock output in
asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source.
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock enable 1/0
These bits select the
SCI clock source
Transmit end interrupt enable
Enables or disables transmitend interrupts (TEI)
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
Receive enable
Enables or disables the receiver
Transmit enable
Enables or disables the transmitter
Receive interrupt enable
Enables or disables receive-data-full interrupts (RXI) and
receive-error interrupts (ERI)
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TXI)
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
321
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from
TDR to TSR.
Bit 7
TIE
Description
0
Transmit-data-empty interrupt request (TXI) is disabled*
1
Transmit-data-empty interrupt request (TXI) is enabled
(Initial value)
Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then
clearing it to 0; or by clearing the TIE bit to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt
(RXI) requested when the RDRF flag is set to 1 in SSR due to transfer of serial receive data from
RSR to RDR; also enables or disables the receive-error interrupt (ERI).
Bit 6
RIE
Description
0
Receive-end (RXI) and receive-error (ERI) interrupt requests are disabled (Initial value)
1
Receive-end (RXI) and receive-error (ERI) interrupt requests are enabled
Note: * RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER,
PER, or ORER flag, then clearing it to 0; or by clearing the RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations.
Bit 5
TE
Description
0
Transmitting disabled*1
1
Transmitting enabled*2
(Initial value)
Notes: 1. The TDRE bit is locked at 1 in SSR.
2. In the enabled state, serial transmitting starts when the TDRE bit in SSR is cleared to 0
after writing of transmit data into TDR. Select the transmit format in SMR before setting
the TE bit to 1.
322
Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.
Bit 4
RE
Description
0
Receiving disabled*1
1
enabled*2
Receiving
(Initial value)
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These
flags retain their previous values.
2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous
mode, or serial clock input is detected in synchronous mode. Select the receive format
in SMR before setting the RE bit to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR.
The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupts are disabled (normal receive operation)
[Clearing conditions]
The MPIE bit is cleared to 0.
MPB = 1 in received data.
(Initial value)
1
Multiprocessor interrupts are enabled*
Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of the RDRF,
FER, and ORER status flags in SSR are disabled until data with the multiprocessor bit
set to 1 is received.
Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,
and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which
MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0,
enables RXI and ERI interrupts (if the RIE bit is set to 1 in SCR), and allows the FER and
ORER flags to be set.
323
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain new transmit data when the MSB is transmitted.
Bit 2
TEIE
Description
0
Transmit-end interrupt requests (TEI) are disabled*
1
Transmit-end interrupt requests (TEI) are enabled*
(Initial value)
Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,
then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing
the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0,
the SCK pin can be used for generic input/output, serial clock output, or serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the
CKE1 and CKE0 bits. For further details on selection of the SCI clock source, see table 11-9 in
section 11.3, Operation.
Bit 1
CKE1
Bit 0
CKE0
Description
0
0
Asynchronous mode
Internal clock, SCK pin available for generic
input/output *1
Synchronous mode
Internal clock, SCK pin used for serial clock output *1
Asynchronous mode
Internal clock, SCK pin used for clock output *2
Synchronous mode
Internal clock, SCK pin used for serial clock output
Asynchronous mode
External clock, SCK pin used for clock input *3
Synchronous mode
External clock, SCK pin used for serial clock input
Asynchronous mode
External clock, SCK pin used for clock input *3
Synchronous mode
External clock, SCK pin used for serial clock input
0
1
1
1
0
1
Notes: 1. Initial value
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
324
11.2.7 Serial Status Register (SSR)
SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI
operating status.
Bit
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Multiprocessor
bit transfer
Value of multiprocessor bit to
be transmitted
Multiprocessor bit
Stores the received
multiprocessor bit value
Transmit end
Status flag indicating end of
transmission
Parity error
Status flag indicating detection of
a receive parity error
Framing error
Status flag indicating detection of a receive
framing error
Overrun error
Status flag indicating detection of a receive overrun error
Receive data register full
Status flag indicating that data has been received and stored in RDR
Transmit data register empty
Status flag indicating that transmit data has been transferred from TDR into
TSR and new data can be written in TDR
Note: * Only 0 can be written, to clear the flag.
325
The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,
and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The
TEND and MPB flags are read-only bits that cannot be written.
SSR is initialized to H'84 by a reset and in standby mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and the next serial transmit data can be written in TDR.
Bit 7
TDRE
Description
0
TDR contains valid transmit data
[Clearing conditions]
Software reads TDRE while it is set to 1, then writes 0.
1
TDR does not contain valid transmit data
[Setting conditions]
The chip is reset or enters standby mode.
The TE bit in SCR is cleared to 0.
TDR contents are loaded into TSR, so new data can be written in TDR.
(Initial value)
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6
RDRF
Description
0
RDR does not contain new receive data
[Clearing conditions]
The chip is reset or enters standby mode.
Software reads RDRF while it is set to 1, then writes 0.
The DMAC reads data from RDR.
1
RDR contains new receive data
[Setting condition]
When serial data is received normally and transferred from RSR to RDR.
(Initial value)
Note: The RDR contents and RDRF flag are not affected by detection of receive errors or by
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still
set to 1 when reception of the next data ends, an overrun error occurs and receive data is
lost.
326
Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5
ORER
Description
0
Receiving is in progress or has ended normally
[Clearing conditions]
The chip is reset or enters standby mode.
Software reads ORER while it is set to 1, then writes 0.
1
A receive overrun error occurred*2
[Setting condition]
Reception of the next serial data ends when RDRF = 1.
(Initial value)*1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its
previous value.
2. RDR continues to hold the receive data before the overrun error, so subsequent receive
data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing
error in asynchronous mode.
Bit 4
FER
Description
0
Receiving is in progress or has ended normally
[Clearing conditions]
The chip is reset or enters standby mode.
Software reads FER while it is set to 1, then writes 0.
1
A receive framing error occurred*2
[Setting condition]
The stop bit at the end of receive data is checked and found to be 0.
(Initial value)*1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous
value.
2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not
checked. When a framing error occurs the SCI transfers the receive data into RDR but
does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set
to 1. In synchronous mode, serial transmitting is also disabled.
327
Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error
in asynchronous mode.
Bit 3
PER
Description
0
Receiving is in progress or has ended normally*1
[Clearing conditions]
The chip is reset or enters standby mode.
Software reads PER while it is set to 1, then writes 0.
1
A receive parity error occurred*2
[Setting condition]
The number of 1s in receive data, including the parity bit, does not match the even or
odd parity setting of O/E in SMR.
(Initial value)
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous
value.
2. When a parity error occurs the SCI transfers the receive data into RDR but does not set
the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted TDR did not contain new transmit data, so transmission has ended. The TEND flag is
a read-only bit and cannot be written.
Bit 2
TEND
Description
0
Transmission is in progress
[Clearing conditions]
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
1
End of transmission
[Setting conditions]
The chip is reset or enters standby mode.
The TE bit is cleared to 0 in SCR.
TDRE is 1 when the last bit of a serial character is transmitted.
328
(Initial value)
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot
be written.
Bit 1
MPB
Description
0
Multiprocessor bit value in receive data is 0*
1
Multiprocessor bit value in receive data is 1
(Initial value)
Note: * If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its
previous value.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in asynchronous mode.
The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected,
or when the SCI is not transmitting.
Bit 0
MPBT
Description
0
Multiprocessor bit value in transmit data is 0
1
Multiprocessor bit value in transmit data is 1
(Initial value)
11.2.8 Bit Rate Register (BRR)
BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud
rate generator clock source, determines the serial communication bit rate.
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby
mode. The two SCI channels have independent baud rate generator control, so different values can
be set in the two channels.
Table 11-3 shows examples of BRR settings in asynchronous mode. Table 11-4 shows examples
of BRR settings in synchronous mode.
329
Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode
ø (MHz)
2
2.097152
2.4576
3
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
1
141
0.03
1
148
–0.04
1
174
–0.26
1
212
0.03
150
1
103
0.16
1
108
0.21
1
127
0
1
155
0.16
300
0
207
0.16
0
217
0.21
0
255
0
1
77
0.16
600
0
103
0.16
0
108
0.21
0
127
0
0
155
0.16
1200
0
51
0.16
0
54
–0.70
0
63
0
0
77
0.16
2400
0
25
0.16
0
26
1.14
0
31
0
0
38
0.16
4800
0
12
0.16
0
13
–2.48
0
15
0
0
19
–2.34
9600
0
6
–6.99
0
6
–2.48
0
7
0
0
9
–2.34
19200
0
2
8.51
0
2
13.78
0
3
0
0
4
–2.34
31250
0
1
0
0
1
4.86
0
1
22.88
0
2
0
38400
0
1
–18.62
0
1
–14.67
0
1
0
—
—
—
ø (MHz)
3.6864
4
4.9152
5
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
64
0.70
2
70
0.03
2
86
0.31
2
88
–0.25
150
1
191
0
1
207
0.16
1
255
0
2
64
0.16
300
1
95
0
1
103
0.16
1
127
0
1
129
0.16
600
0
191
0
0
207
0.16
0
255
0
1
64
0.16
1200
0
95
0
0
103
0.16
0
127
0
0
129
0.16
2400
0
47
0
0
51
0.16
0
63
0
0
64
0.16
4800
0
23
0
0
25
0.16
0
31
0
0
32
–1.36
9600
0
11
0
0
12
0.16
0
15
0
0
15
1.73
19200
0
5
0
0
6
–6.99
0
7
0
0
7
1.73
31250
—
—
—
0
3
0
0
4
–1.70
0
4
0
38400
0
2
0
0
2
8.51
0
3
0
0
3
1.73
330
Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont)
ø (MHz)
6
6.144
7.3728
8
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
106
–0.44
2
108
0.08
2
130
–0.07
2
141
0.03
150
2
77
0.16
2
79
0
2
95
0
2
103
0.16
300
1
155
0.16
1
159
0
1
191
0
1
207
0.16
600
1
77
0.16
1
79
0
1
95
0
1
103
0.16
1200
0
155
0.16
0
159
0
0
191
0
0
207
0.16
2400
0
77
0.16
0
79
0
0
95
0
0
103
0.16
4800
0
38
0.16
0
39
0
0
47
0
0
51
0.16
9600
0
19
–2.34
0
19
0
0
23
0
0
25
0.16
19200
0
9
–2.34
0
9
0
0
11
0
0
12
0.16
31250
0
5
0
0
5
2.40
0
6
5.33
0
7
0
38400
0
4
–2.34
0
4
0
0
5
0
0
6
–6.99
ø (MHz)
9.8304
10
12
12.288
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
174
–0.26
2
177
–0.25
2
212
0.03
2
217
0.08
150
2
127
0
2
129
0.16
2
155
0.16
2
159
0
300
1
255
0
2
64
0.16
2
77
0.16
2
79
0
600
1
127
0
1
129
0.16
1
155
0.16
1
159
0
1200
0
255
0
1
64
0.16
1
77
0.16
1
79
0
2400
0
127
0
0
129
0.16
0
155
0.16
0
159
0
4800
0
63
0
0
64
0.16
0
77
0.16
0
79
0
9600
0
31
0
0
32
–1.36
0
38
0.16
0
39
0
19200
0
15
0
0
15
1.73
0
19
–2.34
0
19
0
31250
0
9
–1.70
0
9
0
0
11
0
0
11
2.40
38400
0
7
0
0
7
1.73
0
9
–2.34
0
9
0
331
Table 11-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont)
ø (MHz)
14
14.7456
16
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
248
–0.17
3
64
0.70
3
70
0.03
150
2
181
0.16
2
191
0
2
207
0.16
300
2
90
0.16
2
95
0
2
103
0.16
600
1
181
0.16
1
191
0
1
207
0.16
1200
1
90
0.16
1
95
0
1
103
0.16
2400
0
181
0.16
0
191
0
0
207
0.16
4800
0
90
0.16
0
95
0
0
103
0.16
9600
0
45
–0.93
0
47
0
0
51
0.16
19200
0
22
–0.93
0
23
0
0
25
0.16
31250
0
13
0
0
14
–1.70
0
15
0
38400
0
10
3.57
0
11
0
0
12
0.16
332
Table 11-4 Examples of Bit Rates and BRR Settings in Synchronous Mode
ø (MHz)
2
4
8
10
16
Bit Rate
(bits/s)
n
N
n
N
n
N
n
N
n
N
110
3
70
—
—
—
—
—
—
—
—
250
2
124
2
249
3
124
—
—
3
249
500
1
249
2
124
2
249
—
—
3
124
1k
1
124
1
249
2
124
—
—
2
249
2.5 k
0
199
1
99
1
199
1
249
2
99
5k
0
99
0
199
1
99
1
124
1
199
10 k
0
49
0
99
0
199
0
249
1
99
25 k
0
19
0
39
0
79
0
99
0
159
50 k
0
9
0
19
0
39
0
49
0
79
100 k
0
4
0
9
0
19
0
24
0
39
250 k
0
1
0
3
0
7
0
9
0
15
500 k
0
0*
0
1
0
3
0
4
0
7
0
0*
0
1
—
—
0
3
2M
0
0*
—
—
0
1
2.5 M
—
—
0
0*
—
—
0
0*
1M
4M
Note: Settings with an error of 1% or less are recommended.
Legend
Blank: No setting available
—:
Setting possible, but error occurs
*:
Continuous transmit/receive not possible
The BRR setting is calculated as follows:
Asynchronous mode:
N=
ø
64 ×
22n–1
×B
× 106 – 1
Synchronous mode:
N=
B:
N:
ø:
n:
ø
8 × 22n–1 × B
× 106 – 1
Bit rate (bits/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
System clock frequency (MHz)
Baud rate generator clock source (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the table below.)
333
SMR Settings
n
Clock Source
CKS1
CKS0
0
ø
0
0
1
ø/4
0
1
2
ø/16
1
0
3
ø/64
1
1
The bit rate error in asynchronous mode is calculated as follows.
ø × 106
Error (%) =
(N + 1) × B × 64 × 22n–1
–1 × 100
334
Table 11-5 indicates the maximum bit rates in asynchronous mode for various system clock
frequencies. Tables 11-6 and 11-7 indicate the maximum bit rates with external clock input.
Table 11-5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode)
Settings
ø (MHz)
Maximum Bit Rate (bits/s)
n
N
2
62500
0
0
2.097152
65536
0
0
2.4576
76800
0
0
3
93750
0
0
3.6864
115200
0
0
4
125000
0
0
4.9152
153600
0
0
5
156250
0
0
6
187500
0
0
6.144
192000
0
0
7.3728
230400
0
0
8
250000
0
0
9.8304
307200
0
0
10
312500
0
0
12
375000
0
0
12.288
384000
0
0
14
437500
0
0
14.7456
460800
0
0
16
500000
0
0
335
Table 11-6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
ø (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.5000
31250
2.097152
0.5243
32768
2.4576
0.6144
38400
3
0.7500
46875
3.6864
0.9216
57600
4
1.0000
62500
4.9152
1.2288
76800
5
1.2500
78125
6
1.5000
93750
6.144
1.5360
96000
7.3728
1.8432
115200
8
2.0000
125000
9.8304
2.4576
153600
10
2.5000
156250
12
3.0000
187500
12.288
3.0720
192000
14
3.5000
218750
14.7456
3.6864
230400
16
4.0000
250000
336
Table 11-7 Maximum Bit Rates with External Clock Input (Synchronous Mode)
ø (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.3333
333333.3
4
0.6667
666666.7
6
1.0000
1000000.0
8
1.3333
1333333.3
10
1.6667
1666666.7
12
2.0000
2000000.0
14
2.3333
2333333.3
16
2.6667
2666666.7
337
11.3 Operation
11.3.1 Overview
The SCI has an asynchronous mode in which characters are synchronized individually, and a
synchronous mode in which communication is synchronized with clock pulses. Serial
communication is possible in either mode. Asynchronous or synchronous mode and the
communication format are selected in SMR, as shown in table 11-8. The SCI clock source is
selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 11-9.
Asynchronous Mode
•
Data length is selectable: 7 or 8 bits.
•
Parity and multiprocessor bits are selectable. So is the stop bit length (1 or 2 bits). These
selections determine the communication format and character length.
•
In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break
state.
•
An internal or external clock can be selected as the SCI clock source.
— When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and can output a serial clock signal with a frequency matching the bit rate.
— When an external clock is selected, the external clock input must have a frequency
16 times the bit rate. (The on-chip baud rate generator is not used.)
Synchronous Mode
•
The communication format has a fixed 8-bit data length.
•
In receiving, it is possible to detect overrun errors.
•
An internal or external clock can be selected as the SCI clock source.
— When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and outputs a serial clock signal to external devices.
— When an external clock is selected, the SCI operates on the input serial clock. The on-chip
baud rate generator is not used.
338
Table 11-8 SMR Settings and Serial Communication Formats
SCI Communication Format
SMR Settings
Bit 7 Bit 6 Bit 2 Bit 5 Bit 3
C/A CHR MP
PE
STOP Mode
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
—
0
0
0
1
—
1
0
1
1
—
0
0
1
1
—
1
1
—
—
—
—
Asynchronous
mode
Data
Length
Multiprocessor
Bit
Parity
Bit
Stop
Bit
Length
8-bit data
Absent
Absent
1 bit
2 bits
Present
1 bit
2 bits
7-bit data
Absent
1 bit
2 bits
Present
1 bit
2 bits
Asynchronous
mode (multiprocessor
format)
8-bit data
Present
Absent
1 bit
2 bits
7-bit data
1 bit
2 bits
Synchronous
mode
8-bit data
Absent
None
Table 11-9 SMR and SCR Settings and SCI Clock Source Selection
SMR
SCR Settings
SCI Transmit/Receive Clock
Bit 7 Bit 1 Bit 0
C/A CKE1 CKE0
Mode
Clock Source
SCK Pin Function
0
0
0
Asynchronous mode
Internal
SCI does not use the SCK pin
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Outputs a clock with frequency
matching the bit rate
Synchronous mode
External
Inputs a clock with frequency
16 times the bit rate
Internal
Outputs the serial clock
External
Inputs the serial clock
339
11.3.2 Operation in Asynchronous Mode
In asynchronous mode each transmitted or received character begins with a start bit and ends with
a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full duplex communication
is possible. The transmitter and receiver are both double buffered, so data can be written and read
while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Figure 11-2 shows the general format of asynchronous serial communication. In asynchronous
serial communication the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and stop bit (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit
rate. Receive data is latched at the center of each bit.
1
Serial data
(LSB)
0
D0
Idle (mark) state
1
(MSB)
D1
D2
D3
D4
D5
Start
bit
Transmit or receive data
1 bit
7 bits or 8 bits
D6
D7
0/1
Parity
bit
1
1
Stop
bit
1 bit or 1 bit or
no bit 2 bits
One unit of data (character or frame)
Figure 11-2 Data Format in Asynchronous Communication (Example: 8-Bit Data with
Parity and 2 Stop Bits)
340
Communication Formats: Table 11-10 shows the 12 communication formats that can be selected
in asynchronous mode. The format is selected by settings in SMR.
Table 11-10 Serial Communication Formats (Asynchronous Mode)
Serial Communication Format and Frame Length
SMR Settings
CHR
PE
MP
STOP
1
2
3
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P
STOP
0
1
0
1
S
8-bit data
P
STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8 bit data
MPB STOP
0
—
1
1
S
8 bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
Legend
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
341
4
5
6
7
8
9
10
11
12
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected
by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. See table 11-9.
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 11-3 so that
the rising edge of the clock occurs at the center of each transmit data bit.
0
D0
D1
D2
D3
D4
D5
D6
D7
O/I
1
1
1 frame
Figure 11-3 Phase Relationship between Output Clock and Serial Data
(Asynchronous Mode)
Transmitting and Receiving Data
SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE
bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes
TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and
RDR, which retain their previous contents.
When an external clock is used, the clock should not be stopped during initialization or
subsequent operation. SCI operation becomes unreliable if the clock is stopped.
Figure 11-4 is a sample flowchart for initializing the SCI.
342
Start of initialization
Clear TE and RE bits
to 0 in SCR
Set CKE1 and CKE0 bits
in SCR (leaving TE and
RE bits cleared to 0)
1
Select communication
format in SMR
2
Set value in BRR
3
1. Select the clock source in SCR. Clear the RIE, TIE, TEIE,
MPIE, TE, and RE bits to 0. If clock output is selected in
asynchronous mode, clock output starts immediately after
the setting is made in SCR.
2. Select the communication format in SMR.
3. Write the value corresponding to the bit rate in BRR.
This step is not necessary when an external clock is used.
4. Wait for at least the interval required to transmit or receive
1 bit, then set the TE or RE bit to 1 in SCR. Set the RIE,
TIE, TEIE, and MPIE bits as necessary. Setting the TE
or RE bit enables the SCI to use the TxD or RxD pin.
Wait
1 bit interval
elapsed?
No
Yes
Set TE or RE bit to 1 in SCR
Set RIE, TIE, TEIE, and
MPIE bits as necessary
4
Transmitting or receiving
Figure 11-4 Sample Flowchart for SCI Initialization
343
Transmitting Serial Data (Asynchronous Mode): Figure 11-5 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
1
Initialize
Start transmitting
2
Read TDRE flag in SSR
No
TDRE = 1?
Yes
1. SCI initialization: the transmit data output function
of the TxD pin is selected automatically.
2. SCI status check and transmit data write: read SSR,
check that the TDRE flag is 1, then write transmit data
in TDR and clear the TDRE flag to 0.
3. To continue transmitting serial data: after checking
that the TDRE flag is 1, indicating that data can be
written, write data in TDR, then clear the TDRE
flag to 0.
4. To output a break signal at the end of serial transmission:
set the DDR bit to 1 and clear the DR bit to 0
(DDR and DR are I/O port registers), then clear the
TE bit to 0 in SCR.
Write transmit data
in TDR and clear TDRE
flag to 0 in SSR
All data
transmitted?
No
3
Yes
Read TEND flag in SSR
TEND = 1?
No
Yes
Output break
signal?
No
4
Yes
Clear DR bit to 0,
set DDR bit to 1
Clear TE bit to 0 in SCR
End
Figure 11-5 Sample Flowchart for Transmitting Serial Data
344
In transmitting serial data, the SCI operates as follows.
•
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
•
After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
— Start bit:
One 0 bit is output.
— Transmit data:
7 or 8 bits are output, LSB first.
— Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
bit is output. Formats in which neither a parity bit nor a
multiprocessor bit is output can also be selected.
— Stop bit:
One or two 1 bits (stop bits) are output.
— Mark state:
Output of 1 bits continues until the start bit of the next
transmit data.
•
The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of
the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the
stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
Figure 11-6 shows an example of SCI transmit operation in asynchronous mode.
1
Start
bit
0
Parity Stop Start
bit
bit
bit
Data
D0
D1
D7
0/1
1
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
1
1
Idle (mark)
state
TDRE
TEND
TXI
interrupt
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI
interrupt
request
TEI interrupt request
1 frame
Figure 11-6 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and 1 Stop Bit)
345
Receiving Serial Data (Asynchronous Mode): Figure 11-7 shows a sample flowchart for
receiving serial data and indicates the procedure to follow.
1
Initialize
Start receiving
Read ORER, PER,
and FER flags in SSR
PER ∨ RER ∨
ORER = 1?
2
Yes
3
No
Error handling
(continued on next page)
4
Read RDRF flag in SSR
No
RDRF = 1?
1. SCI initialization: the receive data function of
the RxD pin is selected automatically.
2., 3. Receive error handling and break
detection: if a receive error occurs, read the
ORER, PER, and FER flags in SSR to identify
the error. After executing the necessary error
handling, clear the ORER, PER, and FER
flags all to 0. Receiving cannot resume if any
of the ORER, PER, and FER flags remains
set to 1. When a framing error occurs, the
RxD pin can be read to detect the break state.
4. SCI status check and receive data read: read
SSR, check that RDRF is set to 1, then read
receive data from RDR and clear the RDRF
flag to 0. Notification that the RDRF flag has
changed from 0 to 1 can also be given by the
RXI interrupt.
5. To continue receiving serial data: check the
RDRF flag, read RDR, and clear the RDRF
flag to 0 before the stop bit of the current
frame is received.
Yes
Read receive data
from RDR, and clear
RDRF flag to 0 in SSR
No
Finished
receiving?
5
Yes
Clear RE bit to 0 in SCR
End
Figure 11-7 Sample Flowchart for Receiving Serial Data (1)
346
3
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit to 0 in SCR
No
PER = 1?
Yes
Parity error handling
Clear ORER, PER, and
FER flags to 0 in SSR
End
Figure 11-7 Sample Flowchart for Receiving Serial Data (2)
347
In receiving, the SCI operates as follows.
•
The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes
internally and starts receiving.
•
Receive data is stored in RSR in order from LSB to MSB.
•
The parity bit and stop bit are received.
After receiving, the SCI makes the following checks:
— Parity check:
The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in SMR.
— Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop
bit is checked.
— Status check: The RDRF flag must be 0 so that receive data can be transferred from
RSR into RDR.
If these checks all pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one of
the checks fails (receive error), the SCI operates as indicated in table 11-11.
Note: When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag is
not set to 1. Be sure to clear the error flags.
•
When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
Table 11-11 Receive Error Conditions
Receive Error
Abbreviation
Condition
Data Transfer
Overrun error
ORER
Receiving of next data ends
while RDRF flag is still set to
1 in SSR
Receive data not transferred
from RSR to RDR
Framing error
FER
Stop bit is 0
Receive data transferred
from RSR to RDR
Parity error
PER
Parity of receive data differs
from even/odd parity setting
in SMR
Receive data transferred
from RSR to RDR
348
Figure 11-8 shows an example of SCI receive operation in asynchronous mode.
1
Start
bit
0
Parity Stop Start
bit
bit
bit
Data
D0
D1
D7
0/1
1
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
1
1
Idle (mark)
state
RDRF
FER
RXI
request
1 frame
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
Framing error,
ERI request
Figure 11-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
11.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set
to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 11-9 shows an example of communication among different processors using a
multiprocessor format.
349
Communication Formats: Four formats are available. Parity-bit settings are ignored when a
multiprocessor format is selected. For details see table 11-8.
Clock: See the description of asynchronous mode.
Transmitting
processor
Serial communication line
Receiving
processor A
Receiving
processor B
Receiving
processor C
Receiving
processor D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
H'01
Serial data
H'AA
(MPB = 1)
(MPB = 0)
ID-sending cycle: receiving
processor address
Data-sending cycle:
data sent to receiving
processor specified by ID
Legend
MPB: Multiprocessor bit
Figure 11-9 Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
350
Transmitting and Receiving Data
Transmitting Multiprocessor Serial Data: Figure 11-10 shows a sample flowchart for
transmitting multiprocessor serial data and indicates the procedure to follow.
1
Initialize
Start transmitting
2
Read TDRE flag in SSR
TDRE = 1?
No
Yes
Write transmit data in
TDR and set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
No
1. SCI initialization: the transmit data
output function of the TxD pin is
selected automatically.
2. SCI status check and transmit data
write: read SSR, check that the TDRE
flag is 1, then write transmit
data in TDR. Also set the MPBT flag to
0 or 1 in SSR. Finally, clear the TDRE
flag to 0.
3. To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be written,
write data in TDR, then clear the TDRE
flag to 0.
4. To output a break signal at the end of
serial transmission: set the DDR bit to
1 and clear the DR bit to 0 (DDR and
DR are I/O port registers), then clear
the TE bit to 0 in SCR.
3
Yes
Read TEND flag in SSR
TEND = 1?
No
Yes
Output break signal?
No
4
Yes
Clear DR bit to 0, set DDR bit to 1
Clear TE bit to 0 in SCR
End
Figure 11-10 Sample Flowchart for Transmitting Multiprocessor Serial Data
351
In transmitting serial data, the SCI operates as follows.
•
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
•
After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit in SCR is set to 1, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
—
—
—
—
—
•
Start bit:
Transmit data:
Multiprocessor bit:
Stop bit:
Mark state:
One 0 bit is output.
7 or 8 bits are output, LSB first.
One multiprocessor bit (MPBT value) is output.
One or two 1 bits (stop bits) are output.
Output of 1 bits continues until the start bit of the next transmit data.
The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag in SSR to 1, outputs the stop
bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
Figure 11-11 shows an example of SCI transmit operation using a multiprocessor format.
Multiprocessor
bit
Multiprocessor
bit
1
Serial
data
Start
bit
0
Stop Start
bit
bit
Data
D0
D1
D7
0/1
1
0
Stop
bit
Data
D0
D1
D7
0/1
1
1
Idle (mark)
state
TDRE
TEND
TXI
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI
request
TEI request
1 frame
Figure 11-11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and
One Stop Bit)
352
Receiving Multiprocessor Serial Data: Figure 11-12 shows a sample flowchart for receiving
multiprocessor serial data and indicates the procedure to follow.
Initialize
1. SCI initialization: the receive data function
of the RxD pin is selected automatically.
2. ID receive cycle: set the MPIE bit to 1 in SCR.
3. SCI status check and ID check: read SSR,
check that the RDRF flag is set to 1, then read
data from RDR and compare with the
processor’s own ID. If the ID does not match,
set the MPIE bit to 1 again and clear the
RDRF flag to 0. If the ID matches, clear the
RDRF flag to 0.
4. SCI status check and data receiving: read
SSR, check that the RDRF flag is set to 1,
then read data from RDR.
5. Receive error handling and break detection:
if a receive error occurs, read the
ORER and FER flags in SSR to identify the error.
After executing the necessary error handling,
clear the ORER and FER flags both to 0.
Receiving cannot resume while either the ORER
or FER flag remains set to 1. When a framing
error occurs, the RxD pin can be read to detect
the break state.
1
Start receiving
Set MPIE bit to 1 in SCR
2
Read ORER and FER flags in SSR
FER ∨ PRER = 1
Yes
No
Read RDRF flag in SSR
3
No
RDRF = 1?
Yes
Read receive data from RDR
No
Own ID?
Yes
Read ORER and FER flags in SSR
FER ∨ ORER = 1
Yes
No
4
Read RDRF flag in SSR
No
RDRF = 1?
Yes
Read receive data from RDR
No
No
5
Finished receiving?
Yes
Error handling
(continued on next page)
Clear RE bit to 0 in SCR
End
Figure 11-12 Sample Flowchart for Receiving Multiprocessor Serial Data (1)
353
5
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit to 0 in SCR
Clear ORER, PER, and FER
flags to 0 in SSR
End
Figure 11-12 Sample Flowchart for Receiving Multiprocessor Serial Data (2)
354
Figure 11-13 shows an example of SCI receive operation using a multiprocessor format.
1
Start
bit
0
Data (ID1)
D0
D1
MPB
D7
1
Stop Start
Data (data1)
bit
bit
1
0
D0
D1
MPB
D7
0
Stop
bit
1
1
Idle (mark)
state
MPIE
RDRF
RDR value
ID1
RXI request
RXI handler reads
(multiprocessor
RDR data and clears
interrupt), MPIE = 0 RDRF flag to 0
Not own ID, so
MPIE bit is set
to 1 again
No RXI request,
RDR not updated
a. Own ID does not match data
1
Start
bit
0
Data (ID2)
D0
D1
MPB
D7
1
Stop Start
Data (data2)
bit
bit
1
0
D0
D1
MPB
D7
0
Stop
bit
1
1
Idle (mark)
state
MPIE
RDRF
RDR value
ID1
ID2
Data 2
RXI request
RXI interrupt handler Own ID, so receiving MPIE bit is set
(multiprocessor
reads RDR data and continues, with data to 1 again
interrupt), MPIE = 0 clears RDRF flag to 0 received by RXI
interrupt handler
b. Own ID matches data
Figure 11-13 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and
One Stop Bit)
355
11.3.4 Synchronous Operation
In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses.
This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so full
duplex communication is possible. The transmitter and receiver are also double buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 11-14 shows the general format in synchronous serial communication.
Transfer direction
One unit (character or frame) of serial data
*
*
Serial clock
LSB
Serial data
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Don’t care
Note: * High except in continuous transmitting or receiving
Figure 11-14 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is placed on the communication line from one
falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.
In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After
output of the MSB, the communication line remains in the state of the MSB. In synchronous mode
the SCI receives data by synchronizing with the rise of the serial clock.
Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit
can be added.
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected by clearing or setting the CKE1 bit in SCR. See table 11-9.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock
pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains in the high state. When the SCI is only receiving, it receives in
units of two characters, so it outputs 16 clock pulses. To receive in units of one character, an
external clock source must be selected.
356
Transmitting and Receiving Data
SCI Initialization (Synchronous Mode): Before transmitting or receiving, clear the TE and RE
bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1 and
initializes TSR. Clearing the RE bit to 0, however, does not initialize the RDRF, PER, FER, and
ORE flags and RDR, which retain their previous contents.
Figure 11-15 is a sample flowchart for initializing the SCI.
Start of initialization
Clear TE and RE
bits to 0 in SCR
Set RIE, TIE, TEIE, MPIE,
CKE1, and CKE0 bits in SCR
(leaving TE and RE bits
cleared to 0)
1
1. Select the clock source in SCR. Clear the RIE, TIE, TEIE,
MPIE, TE, and RE bits to 0.
2. Select the communication format in SMR.
3. Write the value corresponding to the bit rate in BRR.
This step is not necessary when an external clock is used.
4. Wait for at least the interval required to transmit or receive
one bit, then set the TE or RE bit to 1 in SCR. Also set
the RIE, TIE, TEIE, and MPIE bits as necessary.
Setting the TE or RE bit enables the SCI to use the
TxD or RxD pin.
2
Select communication
format in SMR
3
Set value in BRR
Wait
1 bit interval
elapsed?
No
Yes
Set TE or RE to 1 in SCR
Set RIE, TIE, TEIE, and
MPIE bits as necessary
4
Start transmitting or receiving
Figure 11-15 Sample Flowchart for SCI Initialization
357
Transmitting Serial Data (Synchronous Mode): Figure 11-16 shows a sample flowchart for
transmitting serial data and indicates the procedure to follow.
1
Initialize
Start transmitting
2
Read TDRE flag in SSR
1. SCI initialization: the transmit data output function
of the TxD pin is selected automatically.
2. SCI status check and transmit data write: read SSR,
check that the TDRE flag is 1, then write transmit
data in TDR and clear the TDRE flag to 0.
3. To continue transmitting serial data: after checking
that the TDRE flag is 1, indicating that data can be
written, write data in TDR, then clear the TDRE flag
to 0.
No
TDRE = 1?
Yes
Write transmit data in
TDR and clear TDRE flag
to 0 in SSR
All data
transmitted?
No
3
Yes
Read TEND flag in SSR
TEND = 1?
No
Yes
Clear TE bit to 0 in SCR
End
Figure 11-16 Sample Flowchart for Serial Transmitting
358
In transmitting serial data, the SCI operates as follows.
•
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
•
After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock
source is selected, the SCI outputs data in synchronization with the input clock. Data is output
from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
•
The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the
SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the
TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB,
holds the TxD pin in the MSB state. If the TEIE bit in SCR is set to 1, a transmit-end
interrupt (TEI) is requested at this time.
•
After the end of serial transmission, the SCK pin is held in a constant state.
359
Figure 11-17 shows an example of SCI transmit operation.
Transmit
direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI
request
TXI interrupt handler
writes data in TDR
and clears TDRE
flag to 0
TXI
request
1 frame
Figure 11-17 Example of SCI Transmit Operation
360
TEI
request
Receiving Serial Data: Figure 11-18 shows a sample flowchart for receiving serial data and
indicates the procedure to follow. When switching from asynchronous mode to synchronous
mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is
set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled.
1
Initialize
1.
SCI initialization: the receive data function of
the RxD pin is selected automatically.
2., 3. Receive error handling: if a receive error
occurs, read the ORER flag in SSR, then after
executing the necessary error handling, clear
the ORER flag to 0. Neither transmitting nor
receiving can resume while the ORER flag
remains set to 1.
4. SCI status check and receive data read: read
SSR, check that the RDRF flag is set to 1,
then read receive data from RDR and clear
the RDRF flag to 0. Notification that the RDRF
flag has changed from 0 to 1 can also be
given by the RXI interrupt.
5. To continue receiving serial data: check the
RDRF flag, read RDR, and clear the RDRF
flag to 0 before the MSB (bit 7) of the current
frame is received.
Start receiving
Read ORER flag in SSR
ORER = 1?
2
Yes
3
No
Read RDRF flag in SSR
Error handling
4
No
RDRF = 1?
Yes
Read receive data
from RDR, and clear
RDRF flag to 0 in SSR
No
5
Finished
receiving?
Yes
Clear RE bit to 0 in SCR
End
Figure 11-18 Sample Flowchart for Serial Receiving (1)
361
3
Error handling
Overrun error handling
Clear ORER flag to 0 in SSR
End
Figure 11-18 Sample Flowchart for Serial Receiving (2)
In receiving, the SCI operates as follows.
•
The SCI synchronizes with serial clock input or output and initializes internally.
•
Receive data is stored in RSR in order from LSB to MSB.
After receiving the data, the SCI checks that the RDRF flag is 0 so that receive data can be
transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received
data is stored in RDR. If the check does not pass (receive error), the SCI operates as indicated
in table 11-11.
•
After setting the RDRF flag to 1, if the RIE bit is set to 1 in SCR, the SCI requests a receivedata-full interrupt (RXI). If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1,
the SCI requests a receive-error interrupt (ERI).
362
Figure 11-19 shows an example of SCI receive operation.
Receive direction
Serial clock
Serial data
Bit 7
Bit 7
Bit 0
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI
request
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
RXI
request
Overrun error,
ERI request
1 frame
Figure 11-19 Example of SCI Receive Operation
Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 11-20
shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates
the procedure to follow.
363
1
Initialize
Start transmitting and receiving
Read TDRE flag in SSR
2
No
TDRE = 1?
Yes
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
Read ORER flag in SSR
Yes
ORER = 1?
3
No
Error handling
4
Read RDRF flag in SSR
No
RDRF = 1?
Yes
Read receive data from RDR
and clear RDRF flag to 0 in SSR
No
End of transmitting and
receiving?
5
1. SCI initialization: the transmit data
output function of the TxD pin and
receive data input function of the
RxD pin are selected, enabling
simultaneous transmitting and
receiving.
2. SCI status check and transmit
data write: read SSR, check that
the TDRE flag is 1, then write
transmit data in TDR and clear
the TDRE flag to 0.
Notification that the TDRE flag has
changed from 0 to 1 can also be
given by the TXI interrupt.
3. Receive error handling: if a receive
error occurs, read the ORER flag in
SSR, then after executing the necessary error handling, clear the ORER
flag to 0.
Neither transmitting nor receiving
can resume while the ORER flag
remains set to 1.
4. SCI status check and receive
data read: read SSR, check that
the RDRF flag is 1, then read
receive data from RDR and clear
the RDRF flag to 0. Notification
that the RDRF flag has changed
from 0 to 1 can also be given
by the RXI interrupt.
5. To continue transmitting and
receiving serial data: check the
RDRF flag, read RDR, and clear
the RDRF flag to 0 before the
MSB (bit 7) of the current frame
is received. Also check that the
TDRE flag is (bit 7) of the current
frame is received. Also check that
the TDRE flag is set to 1, indicating that data can be written, write
data in TDR, then clear the TDRE
flag to 0 before the MSB (bit 7) of
the current frame is transmitted.
When the DMAC is activated by
a transmit-data-empty interrupt
request (TXI) to write data in TDR,
the TDRE flag is checked and
cleared automatically.
Yes
Clear TE and RE bits to 0 in SCR
End
Note: * When switching from transmitting or receiving to simultaneous
transmitting and receiving, clear the TE and RE bits both to 0,
then set the TE and RE bits both to 1.
Figure 11-20 Sample Flowchart for Serial Transmitting
364
11.4 SCI Interrupts
The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error
interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 11-12
lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled
by the TIE, TEIE, and RIE bits in SCR. Each interrupt request is sent separately to the interrupt
controller.
The TXI interrupt is requested when the TDRE flag is set to 1 in SSR. The TEI interrupt is
requested when the TEND flag is set to 1 in SSR.
The RXI interrupt is requested when the RDRF flag is set to 1 in SSR. The ERI interrupt is
requested when the ORER, PER, or FER flag is set to 1 in SSR.
Table 11-12 SCI Interrupt Sources
Interrupt
Description
Priority
ERI
Receive error (ORER, FER, or PER)
High
RXI
Receive data register full (RDRF)
TXI
Transmit data register empty (TDRE)
TEI
Transmit end (TEND)
Low
365
11.5 Usage Notes
Note the following points when using the SCI.
TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of
transmit data from TDR into TSR. The SCI sets the TDRE flag to 1 when it transfers data from
TDR to TSR.
Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in
TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not
yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE
flag is set to 1.
Simultaneous Multiple Receive Errors: Table 11-13 indicates the state of SSR status flags when
multiple receive errors occur simultaneously. When an overrun error occurs the RSR contents are
not transferred to RDR, so receive data is lost.
Table 11-13 SSR Status Flags and Transfer of Receive Data
RDRF
ORER
FER
PER
Receive Data
Transfer
RSR → RDR
1
1
0
0
×
Overrun error
0
0
1
0
o
Framing error
0
0
0
1
o
Parity error
1
1
1
0
×
Overrun error + framing error
1
1
0
1
×
Overrun error + parity error
0
0
1
1
o
Framing error + parity error
1
1
1
1
×
Overrun error + framing error + parity error
SSR Status Flags
Notes:
o:
Receive Errors
Receive data is transferred from RSR to RDR.
× Receive data is not transferred from RSR to RDR.
366
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the
SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Sending a Break Signal: When the TE bit is cleared to 0 the TxD pin becomes an I/O port, the
level and direction (input or output) of which are determined by DR and DDR bits. This feature
can be used to send a break signal.
After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE
bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR
bits should therefore both be set to 1 beforehand.
To send a break signal during serial transmission, clear the DR bit to 0, then clear the TE bit to 0.
When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the
TxD pin becomes an output port outputting the value 0.
Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive
error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE
flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that
clearing the RE bit to 0 does not clear the receive error flags to 0.
Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous
mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the eighth base clock pulse. See figure 11-21.
367
16 clocks
8 clocks
0
15 0
7
7
15 0
Internal
base clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 11-21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as in equation (1).
| D – 0.5 |
1
) – (L – 0.5) F –
(1 + F) | × 100%...................(1)
N
2N
Receive margin (%)
Ratio of clock frequency to bit rate (N = 16)
Clock duty cycle (D = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
M = | (0.5 –
M:
N:
D:
L:
F:
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
M = [0.5 – 1/(2 × 16)] × 100%
= 46.875%.................................................................................................(2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
368
Restrictions in Synchronous Mode: When an external clock source is used in synchronous
mode, after TDR is reset, wait at least 5 clock counts (5ø) before inputting the transmit clock. If
the clock is input four states after the reset of TDR or earlier, an operation error may occur (figure
11-22).
SCK
t
TDRE
D0
D1
D2
D3
D4
D5
D6
Note: When using an external clock, make sure t is 5 clock cycles or greater.
Figure 11-22 Transmission in Synchronous Mode (Example)
369
D7
370
Section 12 A/D Converter
12.1 Overview
The H8/3032 Series includes a 10-bit successive-approximations A/D converter with a selection
of up to eight analog input channels.
12.1.1 Features
A/D converter features are listed below.
•
10-bit resolution
•
Eight input channels
•
Selectable analog conversion voltage range
The analog voltage conversion range can be programmed by input of an analog reference
voltage at the VREF pin.
•
High-speed conversion
Conversion time: maximum 8.4 µs per channel (with 16 MHz system clock)
•
Two conversion modes
Single mode: A/D conversion of one channel
Scan mode: continuous conversion on one to four channels
•
Four 16-bit data registers
A/D conversion results are transferred for storage into data registers corresponding to the
channels.
•
Sample-and-hold function
•
A/D conversion can be externally triggered
•
A/D interrupt requested at end of conversion
At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
371
12.1.2 Block Diagram
Figure 12-1 shows a block diagram of the A/D converter.
On-chip
data bus
AV SS
AN 0
AN 5
ADCR
ADCSR
ADDRD
–
AN 2
AN 4
ADDRC
+
AN 1
AN 3
ADDRB
10-bit D/A
ADDRA
V REF
Successiveapproximations register
AVCC
Bus interface
Module data bus
Analog
multiplexer
ø/8
Comparator
Control circuit
Sample-andhold circuit
ø/16
AN 6
AN 7
ADI
ADTRG
Legend
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
Figure 12-1 A/D Converter Block Diagram
372
12.1.3 Input Pins
Table 12-1 summarizes the A/D converter’s input pins. The eight analog input pins are divided
into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the
power supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference
voltage.
Table 12-1 A/D Converter Pins
Pin Name
Abbreviation
I/O
Function
Analog power supply pin
AVCC
Input
Analog power supply
Analog ground pin
AVSS
Input
Analog ground and reference voltage
Reference voltage pin
VREF
Input
Analog reference voltage
Analog input pin 0
AN0
Input
Group 0 analog inputs
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
A/D external trigger input pin
ADTRG
Input
Group 1 analog inputs
External trigger input for starting A/D conversion
373
12.1.4 Register Configuration
Table 12-2 summarizes the A/D converter’s registers.
Table 12-2 A/D Converter Registers
Address*1
Name
Abbreviation
R/W
Initial Value
H'FFE0
A/D data register A (high)
ADDRAH
R
H'00
H'FFE1
A/D data register A (low)
ADDRAL
R
H'00
H'FFE2
A/D data register B (high)
ADDRBH
R
H'00
H'FFE3
A/D data register B (low)
ADDRBL
R
H'00
H'FFE4
A/D data register C (high)
ADDRCH
R
H'00
H'FFE5
A/D data register C (low)
ADDRCL
R
H'00
H'FFE6
A/D data register D (high)
ADDRDH
R
H'00
H'FFE7
A/D data register D (low)
ADDRDL
R
H'00
H'00
H'7E
H'FFE8
A/D control/status register
ADCSR
R/(W)*2
H'FFE9
A/D control register
ADCR
R/W
Notes: 1. Lower 16 bits of the address
2. Only 0 can be written in bit 7, to clear the flag.
374
12.2 Register Descriptions
12.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bit
14
12
10
8
6
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
15
13
11
9
7
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
(n = A to D)
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADDRn
A/D conversion data
10-bit data giving an
A/D conversion result
Reserved bits
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the
upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an
A/D data register are reserved bits that always read 0. Table 12-3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 12.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 12-3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0
Group 1
A/D Data Register
AN0
AN4
ADDRA
AN1
AN5
ADDRB
AN2
AN6
ADDRC
AN3
AN7
ADDRD
375
12.2.2 A/D Control/Status Register (ADCSR)
Bit
7
6
5
4
3
2
1
0
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel select 2 to 0
These bits select analog
input channels
Clock select
Selects the A/D conversion time
Scan mode
Selects single mode or scan mode
A/D start
Starts or stops A/D conversion
A/D interrupt enable
Enables and disables A/D end interrupts
A/D end flag
Indicates end of A/D conversion
Note: * Only 0 can be written, to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
376
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7
ADF
Description
0
[Clearing condition]
Cleared by reading ADF while ADF = 1, then writing 0 in ADF
1
[Setting conditions]
Single mode: A/D conversion ends
Scan mode: A/D conversion ends in all selected channels
(Initial value)
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6
ADIE
Description
0
A/D end interrupt request (ADI) is disabled
1
A/D end interrupt request (ADI) is enabled
(Initial value)
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.
Bit 5
ADST
Description
0
A/D conversion is stopped
1
Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion
ends.
Scan mode: A/D conversion starts and continues, cycling among the selected channels,
until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode.
(Initial value)
377
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on
operation in these modes, see section 12.4, Operation. Clear the ADST bit to 0 before switching
the conversion mode.
Bit 4
SCAN
Description
0
Single mode
1
Scan mode
(Initial value)
Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before
switching the conversion time.
Bit 3
CKS
Description
0
Conversion time = 266 states (maximum)
1
Conversion time = 134 states (maximum)
(Initial value)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Group
Selection
Channel Selection
Description
CH2
CH1
CH0
Single Mode
Scan Mode
0
0
0
AN0 (Initial value)
AN0
1
AN1
AN0, AN1
0
AN2
AN0 to AN2
1
AN3
AN0 to AN3
0
AN4
AN4
1
AN5
AN4, AN5
0
AN6
AN4 to AN6
1
AN7
AN4 to AN7
1
1
0
1
378
12.2.3 A/D Control Register (ADCR)
Bit
7
6
5
4
3
2
1
0
TRGE
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
Reserved bits
Trigger enable
Enables or disables external triggering of A/D conversion
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'7F by a reset and in standby mode.
Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.
Bit 7
TRGE
Description
0
A/D conversion cannot be externally triggered
1
A/D conversion starts at the falling edge of the external trigger signal (ADTRG)
Bits 6 to 0—Reserved: Read-only bits, always read as 1.
379
(Initial value)
12.3 CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 12-2 shows the data flow for access to an A/D data register.
Upper-byte read
CPU
(H'AA)
Module data bus
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Lower-byte read
CPU
(H'40)
Module data bus
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Figure 12-2 A/D Data Register Access Operation (Reading H'AA40)
380
12.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
12.4.1 Single Mode (SCAN = 0)
Single mode should be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when
conversion ends.
When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is
requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.
When the mode or analog input channel must be switched during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making
the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be
set at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next.
Figure 12-3 shows a timing diagram for this example.
1.
Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0,
CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started
(ADST = 1).
2.
When A/D conversion is completed, the result is transferred into ADDRB. At the same time
the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3.
Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4.
The A/D interrupt handling routine starts.
5.
The routine reads ADCSR, then writes 0 in the ADF flag.
6.
The routine reads and processes the conversion result (ADDRB).
7.
Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
381
382
Figure 12-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Set *
ADIE
A/D conversion
starts
Set *
Set *
ADST
Clear *
Clear *
ADF
State of channel 0
(AN 0)
State of channel 1
(AN 1)
Idle
Idle
A/D conversion 1
Idle
State of channel 2
(AN 2)
Idle
State of channel 3
(AN 3)
Idle
A/D conversion 2
Idle
ADDRA
ADDRB
ADDRC
ADDRD
Note: * Vertical arrows ( ) indicate instructions executed by software.
Read conversion result
Read conversion result
A/D conversion result 1
A/D conversion result 2
12.4.2 Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first
channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are
selected, after conversion of the first channel ends, conversion of the second channel (AN1 or
AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the
ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data
registers corresponding to the channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the
first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are
described next. Figure 12-4 shows a timing diagram for this example.
1.
Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
2.
When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3.
Conversion proceeds in the same way through the third channel (AN2).
4.
When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI
interrupt is requested at this time.
5.
Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
383
Continuous A/D conversion
Set *1
Clear*1
384
Figure 12-4 Example of A/D Converter Operation (Scan Mode,
Channels AN0 to AN2 Selected)
ADST
Clear* 1
ADF
A/D conversion time
State of channel 0
(AN 0)
State of channel 1
(AN 1)
State of channel 2
(AN 2)
Idle
A/D conversion 1
A/D conversion 4
Idle
A/D conversion 2
Idle
Idle
A/D conversion 3
Idle
State of channel 3
(AN 3)
Idle
A/D conversion 5 *2
Idle
Idle
Idle
Transfer
ADDRA
A/D conversion result 1
ADDRB
ADDRC
ADDRD
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
2. Data currently being converted is ignored.
A/D conversion result 4
A/D conversion result 2
A/D conversion result 3
12.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 12-5 shows the A/D
conversion timing. Table 12-4 indicates the A/D conversion time.
As indicated in figure 12-5, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 12-4.
In scan mode, the values given in table 12-4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
(1)
ø
Address bus
(2)
Write signal
Input sampling
timing
ADF
tD
t SPL
t CONV
Legend
(1):
ADCSR write cycle
(2):
ADCSR address
tD :
Synchronization delay
t SPL : Input sampling time
t CONV: A/D conversion time
Figure 12-5 A/D Conversion Timing
385
Table 12-4 A/D Conversion Time (Single Mode)
CKS = 0
CKS = 1
Symbol
Min
Typ
Max
Min
Typ
Max
Synchronization delay
tD
10
—
17
6
—
9
Input sampling time
tSPL
—
80
—
—
40
—
A/D conversion time
tCONV
259
—
266
131
—
134
Note: Values in the table are numbers of states.
12.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external
trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the
ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit had been set to 1 by software. Figure 12-6 shows the
timing.
ø
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 12-6 External Trigger Input Timing
386
12.5 Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
12.6 Usage Notes
When using the A/D converter, note the following points:
Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins
ANn should be in the range AVSS ≤ ANn ≤ VREF. (n = 0 to 7)
AVCC and AVSS Input Voltages: AVSS should have the following values: AVSS = VSS.
If the A/D converter is not used, the values should be AVCC = VCC and AVSS = VSS.
VREF Input Range: The analog reference voltage input at the VREF pin should be in the range
VREF ≤ AVCC. If the A/D converter is not used, the value should be VREF = VCC.
387
388
Section 13 RAM
13.1 Overview
The H8/3032 has 2 kbytes of on-chip static RAM, the H8/3031 has 1 kbyte, and the H8/3030 has
512 bytes. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte
data and word data in two states, making the RAM suitable for rapid data transfer.
The H8/3032 on-chip RAM is assigned to addresses H'FF710 to H'FFF0F in modes 1 and 3, and
addresses H'F7 10 to H'FF0F in mode 2. The H8/3031 on-chip RAM is assigned to addresses
H'FFB10 to H'FFF0F in modes 1 and 3, and addresses H'FB10 to H'FF0F in mode 2. The H8/3030
on-chip RAM is assigned to addresses H'FFD10 to H'FFF0F in modes 1 and 3, and addresses
H'FD10 to H'FF0F in mode 2. The RAM enable bit (RAME) in the system control register
(SYSCR) can enable or disable the on-chip RAM.
13.1.1 Block Diagram
Figure 13-1 shows a block diagram of the on-chip RAM.
On-chip data bus (upper 8 bits)
On-chip data bus (lower 8 bits)
Bus interface
H'FB10*
H'FB11*
H'FB12
H'FB13*
On-chip RAM
H'FF0E*
H'FF0F*
Even addresses
Odd addresses
Note: * Lower 16 bits of the address
Figure 13-1 RAM Block Diagram (H8/3031 in Mode 2)
389
13.1.2 Register Configuration
The on-chip RAM is controlled by the system control register (SYSCR). Table 13-1 gives the
address and initial value of SYSCR.
Table 13-1 RAM Control Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FFF2
System control register
SYSCR
R/W
H'0B
Note: * Lower 16 bits of the address
390
13.2 System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
—
RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable bit
Enables or
disables
on-chip RAM
Reserved bit
NMI edge select
User bit enable
Standby timer select 2 to 0
Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
(Initial value)
391
13.3 Operation
13.3.1 Mode 1
When the RAME bit is set to 1 in mode 1, accesses to addresses H'FF710 to H'FFF0F of the
H8/3032, to addresses H'FFB10 to H'FFF0F of the H8/3031, and to addresses H'FFD10 to
H'FFF0F of the H8/3030 are directed to the on-chip RAM space. When the RAME bit is cleared
to 0, accesses to such addresses are directed to the off-chip address space.
13.3.2 Modes 2 and 3
When the RAME bit is set to 1 in modes 2 and 3, accesses to addresses H'F710 to H'FF0F of the
H8/3032, to addresses H'FB10 to H'FF0F of the H8/3031, and to addresses H'FD10 to H'FF0F of
the H8/3030 are directed to the on-chip RAM space. When the RAME bit is cleared to 0, read
accesses to such addresses always return H'FF and write accesses are ignored. Note that these
addresses represent the lower 16 bits of the address.
392
Section 14 ROM
14.1 Overview
The H8/3030 has 16 kbytes of on-chip ROM, the H8/3031 has 32 kbytes, and the H8/3032 has
64 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte
data and word data in two states, enabling rapid data transfer.
The PROM version of the H8/3032 can be set to PROM mode and programmed with a generalpurpose PROM programmer.
14.1.1 Block Diagram
Figure 14-1 shows a block diagram of the ROM.
On-chip data bus (upper 8 bits)
On-chip data bus (lower 8 bits)
H'0000
H'0001
H'0002
H'0003
On-chip ROM
H'FFFE
H'FFFF
Even addresses
Odd addresses
Figure 14-1 ROM Block Diagram (H8/3032)
393
14.2 PROM Mode
14.2.1 PROM Mode Setting
In PROM mode, the H8/3032 version with on-chip PROM suspends its microcontroller functions,
enabling the on-chip PROM to be programmed. The programming method is the same as for the
HN27C101, except that page programming is not supported. Table 14-1 indicates how to select
PROM mode.
Table 14-1 Selecting PROM Mode
Pins
Setting
Two mode pins (MD1and MD0)
Low
STBY pin
P51 and P50
High
14.2.2 Socket Adapter and Memory Map
The PROM is programmed using a general-purpose PROM programmer with a socket adapter to
convert to 32 pins. Table 14-2 lists the socket adapter for each package option. Figure 14-2 shows
the pin assignments of the socket adapter. Figure 14-3 shows a memory map in PROM mode.
Table 14-2 Socket Adapter
Microcontroller
Package
Socket Adapter
H8/3032
80-pin QFP (FP-80A)
HS3032ESH01H
80-pin TQFP (TFP-80C)
HS3032ESN01H
The size of the H8/3032 PROM is 64 kbytes. Figure 14-3 shows a memory map in PROM mode.
H'FF data should be specified for unused address areas in the on-chip PROM.
When programming the H8/3032 with a PROM programmer, set the address range to H'0000 to
H'FFFF and specify H'FF data for addresses H'10000 and up. If H'10000 and higher addresses are
programmed by mistake, it may become impossible to program or verify the PROM. Attempts to
program in page-programming mode may have the same result.
394
H8/3032
FP-80A, TFP-80C
57
49
43
69
70
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
39
40
68
67
21
53
44
45
47
58
12
30
50
Pin
RESO
NMI
P60
P80
P81
P30
P31
P32
P33
P34
P35
P36
P37
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P50
P51
AVCC
VREF
VCC
VCC
MD0
MD1
STBY
AVSS
VSS
VSS
VSS
Pin
VPP
EA 9
EA15
EA16
PGM
EO0
EO1
EO2
EO3
EO4
EO5
EO6
EO7
EA 0
EA 1
EA 2
EA 3
EA 4
EA 5
EA 6
EA 7
EA 8
OE
EA 10
EA 11
EA 12
EA 13
EA 14
CE
VCC
PROM Socket
HN27C101 (32 pins)
1
26
3
2
31
13
14
15
17
18
19
20
21
12
11
10
9
8
7
6
5
27
24
23
25
4
28
29
22
32
VSS
Note: Pins not shown in this diagram should be left open.
Legend
V PP :
EO 7 to EO0 :
EA16 to EA 0 :
OE:
CE:
PGM:
Programming voltage (12.5 V)
Data input/output
Address input
Output enable
Chip enable
Program
Figure 14-2 Socket Adapter Pin Assignments
395
16
Address in
MCU mode
Address in
PROM mode
H'0000
H'0000
On-chip PROM
H'FFFF
H'FFFF
Missing area *
H'1FFFF
H'1FFFF
Note: * If read in PROM mode, this area returns H'FF output data.
Figure 14-3 H8/3032 Memory Map in PROM Mode
396
14.3 Programming
Table 14-3 indicates how to select the program, verify, and other modes in PROM mode.
Table 14-3 Mode Selection in PROM Mode
Pins
Mode
CE
OE
PGM
VPP
VCC
EO7 to EO0
EA16 to EA0
Program
L
H
L
VPP
VCC
Data input
Address input
Verify
L
L
H
VPP
VCC
Data output
Address input
Program inhibited
L
L
L
VPP
VCC
High impedance
Address input
L
H
H
H
L
L
H
H
H
Legend
L:
Low voltage level
H:
High voltage level
VPP: VPP voltage level
VCC: VCC voltage level
Read/write specifications are the same as for the standard HN27C101 EPROM, except that page
programming is not supported. Do not select page programming mode. A PROM programmer that
supports only page-programming mode cannot be used. When selecting a PROM programmer,
check that it supports a byte-at-a-time high-speed programming mode. Be sure to set the address
range to H'0000 to H'FFFF.
14.3.1 Programming and Verification
An efficient, high-speed programming procedure can be used to program and verify PROM data.
This procedure programs the chip quickly without subjecting it to voltage stress and without
sacrificing data reliability. Unused address areas contain H'FF data. Figure 14-4 shows the basic
high-speed programming flowchart. Tables 14-4 and 14-5 list the electrical characteristics of the
chip during programming. Figure 14-5 shows a timing chart.
397
Start
Set programming/verification mode
VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V
Address = 0
n=0
n + 1→ n
No
Yes
n < 25
Program with t PW = 0.2 ms ±5%
No
Address + 1 → address
Verification OK?
Yes
Program with t OPW = 0.2n ms
Last address?
No
Yes
Set read mode
VCC = 5.0 V ±0.25 V, VPP = VCC
No
Fail
All addresses
read?
Yes
End
Figure 14-4 High-Speed Programming Flowchart
398
Table 14-4 DC Characteristics
—Preliminary—
(Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Typ
Max
Unit
—
VCC + 0.3
V
Test Conditions
Input high
voltage
EO7 to EO0,
EA16 to EA0,
OE, CE, PGM
VIH
2.4
Input low
voltage
EO7 to EO0,
EA16 to EA0,
OE, CE, PGM
VIL
–0.3 —
0.8
V
Output high
voltage
EO7 to EO0
VOH
2.4
—
—
V
IOH = –200 µA
Output low
voltage
EO7 to EO0
VOL
—
—
0.45
V
IOL = 1.6 mA
Input leakage
current
EO7 to EO0,
EA16 to EA0,
OE, CE, PGM
|ILI|
—
—
2
µA
Vin = 5.25 V/0.5 V
VCC current
ICC
—
—
40
mA
VPP current
IPP
—
—
40
mA
399
Table 14-5 AC Characteristics
(Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Address setup time
tAS
2
—
—
µs
Figure 14-5*1
OE setup time
tOES
2
—
—
µs
Data setup time
tDS
2
—
—
µs
Address hold time
tAH
0
—
—
µs
Data hold time
tDH
2
—
—
µs
*2
Data output disable time
tDF
—
—
130
ns
VPP setup time
tVPS
2
—
—
µs
Programming pulse width
tPW
0.19
0.20
0.21
ms
PGM pulse width for overwrite
programming
tOPW*3
0.19
—
5.25
ms
VCC setup time
tVCS
2
—
—
µs
CE setup time
tCES
2
—
—
µs
Data output delay time
tOE
0
—
150
ns
Notes: 1. Input pulse level: 0.8 V to 2.2 V
Input rise time and fall time ≤ 20 ns
Timing reference levels: 1.0 V and 2.0 V for input; 0.8 V and 2.0 V for output
2. tDF is defined at the point where the output is in the open state and the output level
cannot be read.
3. tOPW is defined by the value given in the flowchart.
400
Program
Verify
Address
tAH
tAS
Data
Input data
tDH
tDS
VPP
VCC
Output data
tDF
VPP
VCC
tVPS
VCC+1
VCC
tVCS
CE
tCES
PGM
tPW
OE
tOES
tOE
tOPW*
Note: * t OPW is defined by the value given in the flowchart.
Figure 14-5 PROM Program/Verify Timing
401
14.3.2 Programming Precautions
•
Program with the specified voltages and timing.
The programming voltage (VPP) in PROM mode is 12.5 V.
Applied voltages in excess of the rated values can permanently destroy the chip. Be
particularly careful about the PROM programmer’s overshoot characteristics.
If the PROM programmer is set to Hitachi HN27C101 specifications, VPP will be 12.5 V.
•
Before programming, check that the chip is correctly mounted in the PROM programmer.
Overcurrent damage to the chip can result if the index marks on the PROM programmer,
socket adapter, and chip are not correctly aligned.
•
Don’t touch the socket adapter or chip while programming. Touching either of these can cause
contact faults and write errors.
•
Select the programming mode carefully. The chip cannot be programmed in page programming
mode.
•
The H8/3032 PROM size is 64 kbytes. Set the address range to H'0000 to H'FFFF. When
programming, assign H'FF data to the unused address area (H'10000 to H'1FFFF).
402
14.4 Reliability of Programmed Data
A highly effective way to improve data retention characteristics is to bake the programmed chips at
150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 14-6 shows the recommended screening procedure.
Program chip and verify programmed data
Bake chip for 24 to 48 hours at
125°C to 150°C with power off
Read and check program
Install
Figure 14-6 Recommended Screening Procedure
If a series of programming errors occurs while the same PROM programmer is in use, stop
programming and check the PROM programmer and socket adapter for defects. Please inform
Hitachi of any abnormal conditions noted during or after programming or in screening of program
data after high-temperature baking.
403
404
Section 15 Clock Pulse Generator
15.1 Overview
The H8/3032 Series has a built-in clock pulse generator (CPG) that generates the system clock (ø)
and other internal clock signals (ø/2 to ø/4096). The clock pulse generator consists of an oscillator
circuit, a duty adjustment circuit, and prescalers.
15.1.1 Block Diagram
Figure 15-1 shows a block diagram of the clock pulse generator.
CPG
XTAL
Oscillator
EXTAL
Duty
adjustment
circuit
Prescalers
ø
ø/2 to ø/4096
Figure 15-1 Block Diagram of Clock Pulse Generator
405
15.2 Oscillator Circuit
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock
signal.
15.2.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as in the example in figure 15-2.
The damping resistance Rd should be selected according to table 15-1. An AT-cut parallelresonance crystal should be used.
C L1
EXTAL
XTAL
Rd
C L1 = C L2 = 10 pF to 22 pF
C L2
Figure 15-2 Connection of Crystal Resonator (Example)
Table 15-1 Damping Resistance Value
Frequency (MHz)
2
4
8
10
12
16
Rd (Ω)
1k
500
200
0
0
0
Crystal Resonator: Figure 15-3 shows an equivalent circuit of the crystal resonator. The crystal
resonator should have the characteristics listed in table 15-2.
CL
L
Rs
XTAL
EXTAL
CO
AT-cut parallel-resonance type
Figure 15-3 Crystal Resonator Equivalent Circuit
406
Table 15-2 Crystal Resonator Parameters
Frequency (MHz)
2
4
8
10
12
16
Rs max (Ω)
500
120
80
70
60
50
Co (pF)
7 pF max
Use a crystal resonator with a frequency equal to the system clock frequency (ø).
Notes on Board Design: When a crystal resonator is connected, the following points should be
noted:
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 15-4.
When the board is designed, the crystal resonator and its load capacitors should be placed as close
as possible to the XTAL and EXTAL pins.
Avoid
Signal A
Signal B
C L2
H8/3032 Series
XTAL
EXTAL
C L1
Figure 15-4 Example of Incorrect Board Design
407
15.2.2 External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in
figure 15-5. In example b, the clock should be held high in standby mode.
If the XTAL pin is left open, the stray capacitance should not exceed 10 pF.
External clock input
EXTAL
Open
XTAL
a. XTAL pin left open
External clock input
EXTAL
XTAL
74HC04
b. Complementary clock input at XTAL pin
Figure 15-5 External Clock Input (Examples)
408
External Clock: The external clock frequency should be equal to the system clock frequency (ø).
Table 15-3 and figure 15-6 indicate the clock timing.
Table 15-3 Clock Timing
VCC =
2.7 V to 5.5 V
VCC = 5.0 V ± 10%
Item
Symbol
Min
Max
Min
Max
Unit Test Conditions
External clock rise
time
tEXr
—
10
—
5
ns
External clock fall
time
tEXf
—
10
—
5
ns
External clock
input duty (a/tcyc)
—
30
70
30
70
%
ø ≥ 5 MHz
40
60
40
60
%
ø < 5 MHz
ø clock duty
(b/tcyc)
—
40
60
40
60
%
Figure 15-6
Figure 15-16
tcyc
a
VCC × 0.5
EXTAL
tEXr
tEXf
tcyc
b
VCC × 0.5
ø
Figure 15-6 External Clock Input Timing
409
Figure
15-6
15.3 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (ø).
15.4 Prescalers
The prescalers divide the system clock (ø) to generate internal clocks (ø/2 to ø/4096).
410
Section 16 Power-Down State
16.1 Overview
The H8/3032 Series has a power-down state that greatly reduces power consumption by halting
CPU functions. The power-down state includes the following three modes:
•
•
•
Sleep mode
Software standby mode
Hardware standby mode
Table 16-1 indicates the methods of entering and exiting these power-down modes and the status
of the CPU and on-chip supporting modules in each mode.
Table 16-1 Power-Down State
State
Mode
Entering
Conditions
Clock
CPU
CPU
Supporting
Registers Functions RAM
I/O
Ports
Exiting
Conditions
Sleep
mode
SLEEP instruc- Active
tion executed
while SSBY = 0
in SYSCR
Halted
Held
Active
Held
Held
• Interrupt
• RES
• STBY
Software
standby
mode
SLEEP instruc- Halted
tion executed
while SSBY = 1
in SYSCR
Halted
Held
Halted
and
reset
Held
Held
•
•
•
•
Halted
Undeter
mined
Halted
and
reset
Held*
High
• STBY
impedance • RES
Hardware Low input at
standby
STBY pin
mode
Halted
NMI
IRQ0 to IRQ2
RES
STBY
Note: * The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state
to hardware standby mode.
Legend
SYSCR: System control register
SSBY: Software standby bit
411
16.2 Register Configuration
The H8/3032 Series’ system control register (SYSCR) controls the power-down state. Table 16-2
summarizes this register.
Table 16-2 Control Register
Address*
Name
Abbreviation
R/W
Initial Value
H'FFF2
System control register
SYSCR
R/W
H'0B
Note: * Lower 16 bits of the address.
16.2.1 System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
—
RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
Reserved bit
NMI edge select
User bit enable
Standby timer select 2 to 0
These bits select the
waiting time at exit from
software standby mode
Software standby
Enables transition to
software standby mode
SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0) control
the power-down state. For information on the other SYSCR bits, see section 3.3, System Control
Register.
412
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7
SSBY
Description
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
(Initial value)
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 8 ms. See table 16-3. If an external
clock is used, any setting is permitted.
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Waiting time = 8192 states
1
Waiting time = 16384 states
0
Waiting time = 32768 states
1
Waiting time = 65536 states
0
—
Waiting time = 131072 states
1
—
Illegal setting
1
1
413
(Initial value)
16.3 Sleep Mode
16.3.1 Transition to Sleep Mode
When the SSBY bit is cleared to 0 in the system control register (SYSCR), execution of the
SLEEP instruction causes a transition from the program execution state to sleep mode.
Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal
registers are retained. The on-chip supporting modules do not halt in sleep mode.
16.3.2 Exit from Sleep Mode
Sleep mode is exited by an interrupt, or by input at the RES or STBY pin.
Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt
exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting
module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by
an NMI interrupt if masked in the CPU.
Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state.
Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby
mode.
414
16.4 Software Standby Mode
16.4.1 Transition to Software Standby Mode
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. The on-chip supporting modules are reset.
As long as the specified voltage is supplied, however, CPU register contents and on-chip RAM
data are retained. The settings of the I/O ports are also held.
16.4.2 Exit from Software Standby Mode
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ0, IRQ1, or
IRQ2 pin, or by input at the RES or STBY pin.
Exit by Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is received, the
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire H8/3032 Series chip, software standby
mode ends, and interrupt exception handling begins. Software standby mode is not exited if the
interrupt enable bits of interrupts IRQ0, IRQ1, and IRQ2 are cleared to 0, or if these interrupts are
masked in the CPU.
Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
supplied immediately to the entire H8/3032 Series chip. The RES signal must be held low long
enough for the clock oscillator to stabilize. When RES goes high, the CPU starts reset exception
handling.
Exit by STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
415
16.4.3 Selection of Waiting Time for Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR should be set as follows.
Crystal Resonator: Set STS2 to STS0 so that the waiting time (for the clock to stabilize) is at
least 8 ms. Table 16-3 indicates the waiting times that are selected by STS2 to STS0 settings at
various system clock frequencies.
External Clock: Any value may be set in the clock-halving version. Normally the minimum
value (STS2 = STS1 = STS0 = 1) is recommended. In the 1:1 clock version, any value other than
the minimum value may be set.
Table 16-3 Clock Frequency and Waiting Time for Clock to Settle
Waiting
STS2 STS1 STS0 Time
16 MHZ 12 MHz 10 MHz 8 MHz
6 MHz
4 MHz
2 MHz
Unit
0
0
0
8192
states
0.51
0.65
0.8
1.0
1.3
2.0
4.1
ms
0
0
1
16384
states
1.0
1.3
1.6
2.0
2.7
4.1
8.2
0
1
0
32768
states
2.0
2.7
3.3
4.1
5.5
8.2
16.4
0
1
1
65536
states
4.1
5.5
6.6
8.2
10.9
16.4
32.8
1
0
—
131072
states
8.2
10.9
13.1
16.4
21.8
32.8
65.5
1
1
—
Illegal setting
: Recommended setting
Note: * This setting cannot be used in the 1:1 clock version.
416
16.4.4 Sample Application of Software Standby Mode
Figure 16-1 shows an example in which software standby mode is entered at the fall of NMI and
exited at the rise of NMI.
With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an
NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit
is set to 1; then the SLEEP instruction is executed to enter software standby mode.
Software standby mode is exited at the next rising edge of the NMI signal .
Clock
oscillator
ø
NMI
NMIEG
SSBY
NMI interrupt
handler
NMIEG = 1
SSBY = 1
Software standby
mode (powerdown state)
Oscillator
settling time
(tosc2)
NMI exception
handling
SLEEP
instruction
Figure 16-1 NMI Timing for Software Standby Mode (Example)
16.4.5 Note
The I/O ports retain their existing states in software standby mode. If a port is in the high output
state, its output current is not reduced.
417
16.5 Hardware Standby Mode
16.5.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin
goes low. Hardware standby mode reduces power consumption drastically by halting all functions
of the CPU and on-chip supporting modules. All modules are reset except the on-chip RAM. As
long as the specified voltage is supplied, on-chip RAM data is retained. I/O ports are placed in the
high-impedance state.
Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data.
The inputs at the mode pins (MD1 to MD0) should not be changed during hardware standby
mode.
16.5.2 Exit from Hardware Standby Mode
Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when
STBY goes high, the clock oscillator starts running. RES should be held low long enough for the
clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a
transition to the program execution state.
16.5.3 Timing for Hardware Standby Mode
Figure 16-2 shows the timing relationships for hardware standby mode. To enter hardware standby
mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive
STBY high, wait for the clock to settle, then bring RES from low to high.
Clock
oscillator
RES
STBY
Oscillator
settling time
Reset
exception
handling
Figure 16-2 Hardware Standby Mode Timing
418
Section 17 Electrical Characteristics
17.1 Absolute Maximum Ratings
Table 17-1 lists the absolute maximum ratings.
Table 17-1 Absolute Maximum Ratings
—Preliminary—
Item
Symbol
Value
Unit
Power supply voltage
VCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +13.5
V
Input voltage (except port 7)
VIN
–0.3 to VCC +0.3
V
Input voltage (port 7)
VIN
–0.3 to AVCC +0.3
V
Reference voltage
VREF
–0.3 to AVCC +0.3
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Analog input voltage
VAN
–0.3 to AVCC +0.3
V
Operating temperature
Topr
Regular specifications: –20 to +75
°C
Wide-range specifications: –40 to +85
°C
–55 to +125
°C
Storage temperature
Tstg
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
419
17.2 Electrical Characteristics
17.2.1 DC Characteristics
Table 17-2 lists the DC characteristics. Table 17-3 lists the permissible output currents.
Table 17-2 DC Characteristics
Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V*, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Schmitt
trigger input
voltages
Input high
voltage
Input low
voltage
Output high
voltage
Symbol
Port A,
P80 to P82,
VT
–
+
VT
+
PB0 to PB3
VT – VT
RES, STBY,
NMI, MD1,
MD0
VIH
–
Min
Typ
Max
Unit Test Conditions
1.0
—
—
V
—
—
VCC × 0.7 V
0.4
—
—
V
VCC – 0.7 —
VCC + 0.3 V
EXTAL
VCC × 0.7 —
VCC + 0.3 V
Port 7
2.0
—
AVCC + 0.3 V
Ports 1, 2, 3,
5, 6, 9, P83,
PB4 to PB7
2.0
—
VCC + 0.3 V
–0.3
—
0.5
V
NMI, EXTAL,
ports 1, 2, 3, 5,
6, 7, 9, P83,
PB4 to PB7
–0.3
—
0.8
V
All output pins VOH
VCC – 0.5 —
—
V
IOH = –200 µA
3.5
—
V
IOH = –1 mA
RES, STBY,
MD1, MD0
VIL
—
Note: * If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open.
Connect AVCC and VREF to VCC, and connect AVSS to VSS.
420
Table 17-2 DC Characteristics (cont)
Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC ,
VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Output low
voltage
Symbol
Min
Typ
Max
Unit
Test Conditions
All output pins VOL
(except RESO)
—
—
0.4
V
IOL = 1.6 mA
Ports 1, 2, 5
and B
—
—
1.0
V
IOL = 10 mA
RESO
—
—
0.4
V
IOL = 2.6 mA
—
—
1.0
µA
VIN = 0.5 to
VCC – 0.5 V
—
—
1.0
µA
VIN = 0.5 to
AVCC – 0.5 V
—
—
1.0
µA
VIN = 0.5 to
VCC – 0.5 V
—
—
10.0
µA
VIN = 0.5 to
VCC – 0.5 V
Input leakage STBY, NMI,
current
RES,
MD1, MD0
|IIN|
Port 7
Three-state
leakage
current
(off state)
Ports 1, 2,
3, 4, 5, 6,
8 to B
|ITS1|
RESO
Input pull-up Ports 2 and 5
current
–IP
50
—
300
µA
VIN = 0 V
Input
NMI
capacitance
All input pins
except NMI
CIN
—
—
50
pF
—
—
15
VIN = 0 V
f = 1 MHz
Ta = 25°C
Current
Normal
dissipation*2 operation
ICC
—
45
60
mA
f = 16 MHz
Sleep mode
—
32
45
mA
f = 16 MHz
Standby
mode*3
—
0.01
5.0
µA
Ta ≤ 50°C
—
—
20.0
µA
50°C < Ta
Notes: 1. If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open.
Connect AVCC and VREF to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 4.5 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
421
Table 17-2 DC Characteristics (cont)
Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Typ
Max
Unit Test Conditions
Analog power During A/D
supply current conversion
AICC
—
1.2
2.0
mA
—
0.01
5.0
µA
—
0.3
0.6
mA
—
0.01
5.0
µA
2.0
—
—
V
Idle
Reference
current
During A/D
conversion
AICC
Idle
RAM standby voltage
VRAM
VREF = 5.0 V
Notes: 1. If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open.
Connect AVCC and VREF to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM < VCC < 4.5 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V*, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Schmitt
trigger input
voltages
Input high
voltage
Symbol
Min
Typ
Max
Unit Test Conditions
VCC × 0.2
—
—
V
—
—
VCC × 0.7
V
VCC × 0.07 —
—
V
VCC × 0.9
—
VCC + 0.3
V
EXTAL
VCC × 0.7
—
VCC + 0.3
V
Port 7
VCC × 0.7
—
AVCC + 0.3 V
Ports 1, 2, 3,
5, 6, 9, P83,
PB4 to PB7
VCC × 0.7
—
VCC + 0.3
Port A,
P80 to P82,
PB0 to PB3
RES, STBY,
NMI, MD1,
MD0
VT
–
VT
+
VT
+–
VIH
VT–
V
Note: * If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open.
Connect AVCC and VREF to VCC, and connect AVSS to VSS.
422
Table 17-2 DC Characteristics (cont)
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V*, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Typ
Max
VIL
–0.3
—
VCC × 0.1 V
NMI, EXTAL,
ports 1, 2, 3,
5, 6, 7, 9, P83,
PB4 to PB7
–0.3
—
VCC × 0.2 V
VCC < 4.0 V
0.8
V
VCC =
4.0 to 5.5 V
Output high
voltage
All output pins VOH
VCC – 0.5 —
—
V
IOH = –200 µA
VCC – 1.0 —
—
V
IOH = –1 mA
Output low
voltage
All output pins VOL
(except RESO)
—
—
0.4
V
IOL = 1.6 mA
Ports 1, 2, 5
and B
—
—
1.0
V
VCC ≤ 4 V,
IOL = 5 mA,
4 V ≤ VCC ≤ 5.5 V,
IOL = 10 mA
RESO
—
—
0.4
V
IOL = 1.6 mA
—
—
1.0
µA
VIN = 0.5 to
VCC – 0.5 V
—
—
1.0
µA
VIN = 0.5 to
AVCC – 0.5 V
—
—
1.0
µA
VIN = 0.5 to
VCC – 0.5 V
—
—
10.0
µA
VIN = 0.5 to
VCC – 0.5 V
10
—
300
µA
VCC = 2.7 V to
5.5 V,
VIN = 0 V
Input low
voltage
RES, STBY,
MD1, MD0
Input leakage STBY, NMI,
current
RES,
MD1, MD0
|IIN|
Port 7
Three-state
leakage
current
(off state)
Ports 1, 2, 3,
5, 6, 8 to B
|ITS1|
RESO
Input pull-up Ports 2
current
and 5
–IP
Unit
Test Conditions
Note: * If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open.
Connect AVCC and VREF to VCC, and connect AVSS to VSS.
423
Table 17-2 DC Characteristics (cont)
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Typ
Max
Unit Test Conditions
CIN
—
—
50
pF
—
—
15
VIN = 0 V
f = 1 MHz
Ta = 25°C
—
12
(3.0 V)
31.8
(5.5 V)
mA
f = 8 MHz
Sleep mode
—
8
(3.0 V)
23.0
(5.5 V)
mA
f = 8 MHz
Standby
mode*3
—
0.01
5.0
µA
Ta ≤ 50°C
—
—
20.0
µA
50°C < Ta
—
1.0
2.0
mA
AVCC = 3.0 V
—
1.2
—
mA
AVCC = 5.0 V
—
0.01
5.0
µA
—
0.2
0.4
mA
VREF = 3.0 V
—
0.3
—
mA
VREF = 5.0 V
—
0.01
5.0
µA
2.0
—
—
V
Input
capacitance
NMI
Current
dissipation*2
Normal
operation
All input pins
except NMI
Analog power During A/D
supply current conversion
ICC*4
AICC
Idle
Reference
current
During A/D
conversion
AICC
Idle
RAM standby voltage
VRAM
Notes: 1. If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open.
Connect AVCC and VREF to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 2.7 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
4. ICC depends on VCC and f as follows:
ICCmax = 1.0 (mA) + 0.7 (mA/MHz · V) × VCC × f [normal mode]
ICCmax = 1.0 (mA) + 0.5 (mA/MHz · V) × VCC × f [sleep mode]
424
Table 17-2 DC Characteristics (cont)
Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V*, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Schmitt
trigger input
voltages
Input high
voltage
Input low
voltage
Output high
voltage
Port A,
P80 to P82,
PB0 to PB3
Symbol
Min
Typ
Max
Unit Test Conditions
VT–
VCC × 0.2
—
—
V
VT+
—
—
VCC × 0.7
V
—
V
VT+ – VT– VCC × 0.07 —
VCC × 0.9
—
VCC + 0.3
V
EXTAL
VCC × 0.7
—
VCC + 0.3
V
Port 7
VCC × 0.7
—
AVCC + 0.3 V
Ports 1, 2, 3,
5, 6, 9, P83,
PB4 to PB7
VCC × 0.7
—
VCC + 0.3
RES, STBY,
NMI, MD1,
MD0
VIH
V
–0.3
—
VCC × 0.1 V
NMI, EXTAL,
ports 1, 2, 3,
5, 6, 7, 9, P83,
PB4 to PB7
–0.3
—
VCC × 0.2 V
VCC < 4.0 V
0.8
V
VCC =
4.0 to 5.5 V
All output pins VOH
VCC – 0.5 —
—
V
IOH = –200 µA
VCC – 1.0 —
—
V
IOH = –1 mA
RES, STBY,
MD1, MD0
VIL
Note: * If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open.
Connect AVCC and VREF to VCC, and connect AVSS to VSS.
425
Table 17-2 DC Characteristics (cont)
Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V*, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Output low
voltage
Symbol
Min
Typ
Max
Unit
Test Conditions
All output pins VOL
(except RESO)
—
—
0.4
V
IOL = 1.6 mA
Ports 1, 2, 5
and B
—
—
1.0
V
VCC ≤ 4 V
IOL = 5 mA,
4 V < VCC ≤ 5.5 V
IOL = 10 mA
RESO
—
—
0.4
V
IOL = 1.6 mA
—
—
1.0
µA
VIN = 0.5 to
VCC – 0.5 V
—
—
1.0
µA
VIN = 0.5 to
AVCC – 0.5 V
—
—
1.0
µA
VIN = 0.5 to
VCC – 0.5 V
—
—
10.0
µA
VIN = 0.5 to
VCC – 0.5 V
10
—
300
µA
VCC = 3.0 V to
5.5 V,
VIN = 0 V
Input leakage STBY, NMI,
current
RES,
MD1, MD0
|IIN|
Port 7
Three-state
leakage
current
(off state)
Ports 1, 2, 3,
5, 6, 8 to B
|ITS1|
RESO
Input pull-up Pors 2
current
and 5
–IP
Note: * If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open.
Connect AVCC and VREF to VCC, and connect AVSS to VSS.
426
Table 17-2 DC Characteristics (cont)
Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Typ
Max
Unit Test Conditions
CIN
—
—
50
pF
—
—
15
VIN = 0 V
f = 1 MHz
Ta = 25°C
—
15
(3.0 V)
39.5
(5.5 V)
mA
f = 10 MHz
Sleep mode
—
10
(3.0 V)
28.5
(5.5 V)
mA
f = 10 MHz
Standby
mode*3
—
0.01
5.0
µA
Ta ≤ 50°C
—
—
20.0
µA
50°C < Ta
—
1.0
2.0
mA
AVCC = 3.0 V
—
1.2
—
mA
AVCC = 5.0 V
—
0.01
5.0
µA
—
0.2
0.4
mA
VREF = 3.0 V
—
0.3
—
mA
VREF = 5.0 V
—
0.01
5.0
µA
2.0
—
—
V
Input
capacitance
NMI
Current
dissipation*2
Normal
operation
All input pins
except NMI
Analog power During A/D
supply current conversion
ICC*4
AICC
Idle
Reference
current
During A/D
conversion
AICC
Idle
RAM standby voltage
VRAM
Notes: 1. If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open.
Connect AVCC and VREF to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 3.0 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
4. ICC depends on VCC and f as follows:
ICCmax = 1.0 (mA) + 0.7 (mA/MHz · V) × VCC × f [normal mode]
ICCmax = 1.0 (mA) + 0.5 (mA/MHz · V) × VCC × f [sleep mode]
427
Table 17-3 Permissible Output Currents (1)
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Permissible output
low current (per pin)
Ports 1, 2, 5 and B
Permissible output
low current (total)
Total of 28 pins including
ports 1, 2, 5 and B
Symbol
Min
Typ
Max
Unit
IOL
—
—
10
mA
—
—
2.0
mA
—
—
80
mA
—
—
120
mA
Other output pins
ΣIOL
Total of all output pins,
including the above
Permissible output
high current (per pin)
All output pins
IOH
—
—
2.0
mA
Permissible output
high current (total)
Total of all output pins
ΣIOH
—
—
40
mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 17-3.
2. When driving a darlington pair or LED, always insert a current-limiting resistor in the
output line, as shown in figures 17-1 and 17-2.
428
H8/3032 Series
2 kΩ
Port
Darlington pair
Figure 17-1 Darlington Pair Drive Circuit (Example)
H8/3032 Series
Ports 5 and B
600 Ω
LED
Figure 17-2 LED Drive Circuit (Example)
429
17.2.2 AC Characteristics
Bus timing parameters are listed in table 17-4. Control signal timing parameters are listed in
table 17-5. Timing parameters of the on-chip supporting modules are listed in table 17-6.
Table 17-4 Bus Timing (1)
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition B
8 MHz
Max
Condition C
10 MHz
Min
Symbol
Min
Clock cycle time
tCYC
125
500
100
500
62.5
500
Clock low pulse width
tCL
40
—
40
—
20
—
Clock high pulse width
tCH
40
—
30
—
20
—
Clock rise time
tCR
—
20
—
15
—
10
Clock fall time
tCF
—
20
—
15
—
10
Address delay time
tAD
—
60
—
50
—
30
Address hold time
tAH
25
—
20
—
10
—
Address strobe delay
time
tASD
—
60
—
40
—
30
Write strobe delay time
tWSD
—
60
—
50
—
30
Strobe delay time
tSD
—
60
—
50
—
30
Write data strobe pulse
width 1
tWSW1*
85
—
60
—
35
—
Write data strobe pulse
width 2
tWSW2*
150
—
110
—
65
—
Address setup time 1
tAS1
20
—
15
—
10
—
Address setup time 2
tAS2
80
—
65
—
40
—
Read data setup time
tRDS
50
—
35
—
20
—
Read data hold time
tRDH
0
—
0
—
0
—
430
Max
16 MHz
Item
Min
Max
Unit
ns
Test
Conditions
Figure 17-4,
Figure 17-5
Table 17-4 Bus Timing (cont)
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition B
Condition C
8 MHz
10 MHz
16 MHz
Item
Symbol
Min
Max
Min
Max
Min
Max
Write data delay time
tWDD
—
75
—
75
—
60
Write data setup time 1
tWDS1
90
—
40
—
15
—
Write data setup time 2
tWDS2
5
—
–10
—
–5
—
Write data hold time
tWDH
25
—
20
—
20
—
Read data access
time 1
tACC1*
—
110
—
100
—
55
Read data access
time 2
tACC2*
—
230
—
200
—
115
Read data access
time 3
tACC3*
—
55
—
50
—
25
Read data access
time 4
tACC4*
—
160
—
150
—
85
Precharge time
tPCH*
85
—
60
—
40
—
Wait setup time
tWTS
40
—
40
—
25
—
Wait hold time
tWTH
10
—
10
—
5
—
Note is on next page.
431
Unit
Test
Conditions
ns
Figure 17-4,
Figure 17-5
ns
Figure 17-6
Note: At 8 MHz, the times below depend as indicated on the clock cycle time.
tACC1 = 1.5 × tcyc – 78 (ns)
tWSW1 = 1.0 × tcyc – 40 (ns)
tACC2 = 2.5 × tcyc – 83 (ns)
tWSW2 = 1.5 × tcyc – 38 (ns)
tACC3 = 1.0 × tcyc – 70 (ns)
tPCH = 1.0 × tcyc – 40 (ns)
tACC4 = 2.0 × tcyc – 90 (ns)
At 10 MHz, the times below depend as indicated on the clock cycle time.
tACC1 = 1.5 × tcyc – 50 (ns)
tWSW1 = 1.0 × tcyc – 40 (ns)
tACC2 = 2.5 × tcyc – 50 (ns)
tWSW2 = 1.5 × tcyc – 40 (ns)
tACC3 = 1.0 × tcyc – 50 (ns)
tPCH = 1.0 × tcyc – 40 (ns)
tACC4 = 2.0 × tcyc – 50 (ns)
At 16 MHz, the times below depend as indicated on the clock cycle time.
tACC1 = 1.5 × tcyc – 39 (ns)
tWSW1 = 1.0 × tcyc – 28 (ns)
tACC2 = 2.5 × tcyc – 41 (ns)
tWSW2 = 1.5 × tcyc – 28 (ns)
tACC3 = 1.0 × tcyc – 38 (ns)
tPCH = 1.0 × tcyc – 23 (ns)
tACC4 = 2.0 × tcyc – 40 (ns)
432
Table 17-5 Control Signal Timing
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition B
Condition C
8 MHz
10 MHz
16 MHz
Symbol
Min
Max
Min
Max
Min
Max
RES setup time
tRESS
200
—
200
—
200
—
ns
RES pulse width
tRESW
10
—
10
—
10
—
tCYC
RESO output delay
time
tRESD
—
100
—
100
—
100
ns
RESO output pulse
width
tRESOW
132
—
132
—
132
—
tCYC
NMI setup time
(NMI, IRQ4 to IRQ0)
tNMIS
200
—
200
—
150
—
ns
Figure 17-9
NMI hold time
(NMI, IRQ4 to IRQ0)
tNMIH
10
—
10
—
10
—
Interrupt pulse width
(NMI, IRQ4 to IRQ0
when exiting software
standby mode)
tNMIW
200
—
200
—
200
—
Clock oscillator settling
time at reset (crystal)
tOSC1
20
—
20
—
20
—
ms
Figure 17-10
Clock oscillator settling
time in software standby
(crystal)
tOSC2
8
—
8
—
8
—
433
Unit
Test
Conditions
Item
Figure 17-7
Figure 17-8
Figure 16-1
Table 17-6 Timing of On-Chip Supporting Modules
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
SCI
Condition B
Condition C
8 MHz
10 MHz
16 MHz
Symbol
Min
Max
Min
Max
Min
Max
Unit
Test
Conditions
Timer output
delay time
tTOCD
—
100
—
100
—
100
ns
Figure 17-12
Timer input
setup time
tTICS
50
—
50
—
50
—
Timer clock
input setup time
tTCKS
50
—
50
—
50
—
Timer Single
clock edge
pulse
Both
width
edges
tTCKWH
1.5
—
1.5
—
1.5
—
tTCKWL
2.5
—
2.5
—
2.5
—
tSCYC
4
—
4
—
4
—
tSCYC
6
—
6
—
6
—
Input clock rise
time
tSCKR
—
1.5
—
1.5
—
1.5
Input clock fall
time
tSCKF
—
1.5
—
1.5
—
1.5
Input clock
pulse width
tSCKW
0.4
0.6
0.4
0.6
0.4
0.6
Item
ITU
Condition A
Input Asynclock chronous
cycle
Synchronous
434
Figure 17-13
tCYC
Figure 17-14
tSCYC
Table 17-6 Timing of On-Chip Supporting Modules (cont)
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Ports
and
TPC
Condition B
Condition C
8 MHz
10 MHz
16 MHz
Symbol
Min
Max
Min
Max
Min
Max
Unit
Test
Conditions
Transmit data
delay time
tTXD
—
100
—
100
—
100
ns
Figure 17-15
Receive data
setup time
(synchronous)
tRXS
100
—
100
—
100
—
Receive data
hold time
(synchronous
clock input)
tRXH
100
—
100
—
100
—
Receive data
hold time
(synchronous
clock output)
tRXH
0
—
0
—
0
—
Output data
delay time
tPWD
—
100
—
100
—
100
ns
Figure 17-11
Input data
setup time
(synchronous)
tPRS
50
—
50
—
50
—
Input data
hold time
(synchronous)
tPRH
50
—
50
—
50
—
Item
SCI
Condition A
435
5V
RL
H8/3032 Series
output pin
C = 90 pF: ports 5, 6, 8,
A19 to A0, D7 to D0,
ø, AS , RD, WR
C = 30 pF: ports 9, A, B
R L = 2.4 kΩ
R H = 12 kΩ
C
RH
Input/output timing measurement levels
• Low: 0.8 V
• High: 2.0 V
Figure 17-3 Output Load Circuit
436
17.2.3 A/D Conversion Characteristics
Table 17-7 lists the A/D conversion characteristics.
Table 17-7 A/D Converter Characteristics
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A
Condition B
8 MHz
Condition C
10 MHz
16 MHz
Item
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Resolution
10
10
10
10
10
10
10
10
10
bits
Conversion time
—
—
16.8
—
—
13.4
—
—
8.4
µs
Analog input
capacitance
—
—
20
—
—
20
—
—
20
pF
Permissible signalsource impedance
—
—
10*1
—
—
10*1
—
—
10*4
kΩ
—
—
5*2
5*3
—
—
5*5
Nonlinearity error
—
—
±6.0
—
—
±6.0
—
—
±3.0
LSB
Offset error
—
—
±4.0
—
—
±4.0
—
—
±2.0
LSB
Full-scale error
—
—
±4.0
—
—
±4.0
—
—
±2.0
LSB
Quantization error
—
—
±0.5
—
—
±0.5
—
—
±0.5
LSB
Absolute accuracy
—
—
±8.0
—
—
±8.0
—
—
±4.0
LSB
Notes: 1.
2.
3.
4.
5.
The value is for 4.0 ≤ AVCC ≤ 5.5.
The value is for 2.7 ≤ AVCC < 4.0.
The value is for 3.0 ≤ AVCC < 4.0.
The value is for ø ≤ 12 MHz.
The value is for ø > 12 MHz.
437
17.3 Operational Timing
This section shows timing diagrams.
17.3.1 Bus Timing
Bus timing is shown as follows:
•
Basic bus cycle: two-state access
Figure 17-4 shows the timing of the external two-state access cycle.
•
Basic bus cycle: three-state access
Figure 17-5 shows the timing of the external three-state access cycle.
•
Basic bus cycle: three-state access with one wait state
Figure 17-6 shows the timing of the external three-state access cycle with one wait state
inserted.
438
T1
T2
tcyc
tCH
tCL
ø
tCF
tCR
tAD
A19 to A 0
tPCH
AS
tASD
tACC3
tSD
tAH
tASD
tACC3
tSD
tAH
tAS1
tPCH
RD
(read)
tAS1
tACC1
tRDS
tRDH
D7 to D0
(read)
tPCH
tASD
WR (write)
tSD
tAH
tAS1
tWSW1
tWDD
tWDS1
tWDH
D7 to D0
(write)
Figure 17-4 Basic Bus Cycle: Two-State Access
439
T1
T2
T3
ø
A19 to A0
tACC4
AS
tACC4
RD (read)
tRDS
tACC2
D7 to D0
(read)
tWSD
WR (write)
tWSW2
tAS2
tWDS2
D7 to D0
(write)
Figure 17-5 Basic Bus Cycle: Three-State Access
440
T1
T2
TW
T3
ø
A19 to A0
AS
RD (read)
D7 to D0
(read)
WR (write)
D7 to D0
(write)
tWTS
tWTH
tWTS
tWTH
WAIT
Figure 17-6 Basic Bus Cycle: Three-State Access with One Wait State
441
17.3.2 Control Signal Timing
Control signal timing is shown as follows:
•
Reset input timing
Figure 17-7 shows the reset input timing.
•
Reset output timing
Figure 17-8 shows the reset output timing.
•
Interrupt input timing
Figure 17-9 shows the input timing for NMI and IRQ4 to IRQ0.
ø
tRESS
tRESS
RES
tRESW
Figure 17-7 Reset Input Timing
ø
tRESD
tRESD
RESO
tRESOW
Figure 17-8 Reset Output Timing
442
ø
tNMIS
tNMIH
tNMIS
tNMIH
NMI
IRQ E
tNMIS
IRQ L
IRQ E : Edge-sensitive IRQ I
IRQ L : Level-sensitive IRQ I (I = 0 to 4)
tNMIW
NMI
IRQ J
(J = 0 to 2)
Figure 17-9 Interrupt Input Timing
443
17.3.3 Clock Timing
Clock timing is shown as follows:
•
Oscillator settling timing
Figure 17-10 shows the oscillator settling timing.
ø
VCC
STBY
tOSC1
tOSC1
RES
Figure 17-10 Oscillator Settling Timing
17.3.4 TPC and I/O Port Timing
TPC and I/O port timing is shown as follows.
T1
T2
T3
ø
tPRS
tPRH
Ports 1 to 3,
5, A, and B
(read)
tPWD
Ports 1 to 3,
5, 6, 8, 9, A,
and B (write)
Figure 17-11 TPC and I/O Port Input/Output Timing
444
17.3.5 ITU Timing
ITU timing is shown as follows:
•
ITU input/output timing
Figure 17-12 shows the ITU input/output timing.
•
ITU external clock input timing
Figure 17-13 shows the ITU external clock input timing.
ø
tTOCD
Output
compare*1
tTICS
Input
capture*2
Notes: 1. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4, TOCXA4, TOCXB4
2. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4
Figure 17-12 ITU Input/Output Timing
tTCKS
ø
tTCKS
TCLKA to
TCLKD
tTCKWL
tTCKWH
Figure 17-13 ITU Clock Input Timing
445
17.3.6 SCI Input/Output Timing
SCI timing is shown as follows:
•
SCI input clock timing
Figure 17-14 shows the SCI input clock timing.
•
SCI input/output timing (synchronous mode)
Figure 17-15 shows the SCI input/output timing in synchronous mode.
tSCKW
tSCKR
tSCKR
SCK
tSCYC
Figure 17-14 SCK Input Clock Timing
tSCYC
SCK
tTXD
TxD
(transmit
data)
tRXS
tRXH
RxD
(receive
data)
Figure 17-15 SCI Input/Output Timing in Synchronous Mode
446
Appendix A Instruction Set
A.1 Instruction List
Operand Notation
Symbol
Description
Rd
General destination register
Rs
General source register
Rn
General register
ERd
General destination register (address register or 32-bit register)
ERs
General source register (address register or 32-bit register)
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
PC
Program counter
SP
Stack pointer
CCR
Condition code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
disp
Displacement
→
Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+
Addition of the operands on both sides
–
Subtraction of the operand on the right from the operand on the left
×
Multiplication of the operands on both sides
÷
Division of the operand on the left by the operand on the right
∧
Logical AND of the operands on both sides
∨
Logical OR of the operands on both sides
⊕
Exclusive logical OR of the operands on both sides
¬
NOT (logical complement)
( ), < >
Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
447
Condition Code Notation
Symbol
Description
↕
Changed according to execution result
*
Undetermined (no guaranteed value)
0
Cleared to 0
1
Set to 1
—
Not affected by execution of the instruction
∆
Varies depending on conditions, described in notes
448
Table A-1 Instruction Set
Data transfer instructions
B
#xx:8 → Rd8
MOV.B Rs, Rd
B
Rs8 → Rd8
2
Condition Code
I
C
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
2
MOV.B #xx:8, Rd
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Normal
1.
H N
Z
V
— — ↕
↕
0 —
2
— — ↕
↕
0 —
2
MOV.B @ERs, Rd
B
@ERs → Rd8
— — ↕
↕
0 —
4
MOV.B @(d:16, ERs),
Rd
B
@(d:16, ERs) → Rd8
4
— — ↕
↕
0 —
6
MOV.B @(d:24, ERs),
Rd
B
@(d:24, ERs) → Rd8
8
— — ↕
↕
0 —
10
MOV.B @ERs+, Rd
B
@ERs → RD8
ERs32+1 → ERs32
— — ↕
↕
0 —
6
MOV.B @aa:8, Rd
B
@aa:8 → Rd8
— — ↕
↕
0 —
4
2
2
2
MOV.B @aa:16, Rd
B
@aa:16 → Rd8
4
— — ↕
↕
0 —
6
MOV.B @aa:24, Rd
B
@aa:24 → Rd8
6
— — ↕
↕
0 —
8
MOV.B Rs, @ERd
B
Rs8 → @ERd
— — ↕
↕
0 —
4
MOV.B Rs, @(d:16,
ERd)
B
Rd8 → @(d:16, ERd)
4
— — ↕
↕
0 —
6
MOV.B Rs, @(d:24,
ERd)
B
Rd8 → @(d:24, ERd)
8
— — ↕
↕
0 —
10
MOV.B Rs, @ERd
B
ERd32–1 → ERd32
Rs8 → @ERd
— — ↕
↕
0 —
6
MOV.B Rs, @aa:8
B
Rs8 → @aa:8
2
— — ↕
↕
0 —
4
MOV.B Rs, @aa:16
B
Rs8 → @aa:16
4
— — ↕
↕
0 —
6
MOV.B Rs, @aa:24
B
Rs8 → @aa:24
6
— — ↕
↕
0 —
8
— — ↕
↕
0 —
4
— — ↕
↕
0 —
2
MOV.W #xx:16, Rd
W #xx:16 → Rd16
MOV.W Rs, Rd
W Rs16 → Rd16
2
2
4
2
MOV.W @ERs, Rd
W @ERs → Rd16
— — ↕
↕
0 —
4
MOV.W @(d:16, ERs),
Rd
W @(d:16, ERs) → Rd16
4
— — ↕
↕
0 —
6
MOV.W @(d:24, ERs),
Rd
W @(d:24, ERs) → Rd16
8
— — ↕
↕
0 —
10
MOV.W @ERs+, Rd
W @ERs → Rd16
ERs32+2 → @ERd32
— — ↕
↕
0 —
6
MOV.W @aa:16, Rd
W @aa:16 → Rd16
— — ↕
↕
0 —
6
2
2
4
449
Table A-1 Instruction Set (cont)
C
Normal
Condition Code
I
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
H N
Z
V
— — ↕
↕
0 —
8
— — ↕
↕
0 —
4
MOV.W @aa:24, Rd
W @aa:24 → Rd16
MOV.W Rs, @ERd
W Rs16 → @ERd
MOV.W Rs, @(d:16,
ERd)
W Rs16 → @(d:16, ERd)
4
— — ↕
↕
0 —
6
MOV.W Rs, @(d:24,
ERd)
W Rs16 → @(d:24, ERd)
8
— — ↕
↕
0 —
10
MOV.W Rs, @–ERd
W ERd32–2 → ERd32
Rs16 → @ERd
— — ↕
↕
0 —
6
MOV.W Rs, @aa:16
W Rs16 → @aa:16
4
— — ↕
↕
0 —
6
MOV.W Rs, @aa:24
W Rs16 → @aa:24
6
— — ↕
↕
0 —
8
— — ↕
↕
0 —
6
— — ↕
↕
0 —
2
MOV.L #xx:32, Rd
L
#xx:32 → Rd32
MOV.L ERs, ERd
L
ERs32 → ERd32
6
2
2
6
2
MOV.L @ERs, ERd
L
@ERs → ERd32
— — ↕
↕
0 —
8
MOV.L @(d:16, ERs),
ERd
L
@(d:16, ERs) → ERd32
6
— — ↕
↕
0 —
10
MOV.L @(d:24, ERs),
ERd
L
@(d:24, ERs) → ERd32
10
— — ↕
↕
0 —
14
MOV.L @ERs+, ERd
L
@ERs → ERd32
ERs32+4 → ERs32
— — ↕
↕
0 —
10
MOV.L @aa:16, ERd
L
@aa:16 → ERd32
6
— — ↕
↕
0 —
10
8
— — ↕
↕
0 —
12
— — ↕
↕
0 —
8
4
4
MOV.L @aa:24, ERd
L
@aa:24 → ERd32
MOV.L ERs, @ERd
L
ERs32 → @ERd
MOV.L ERs, @(d:16,
ERd)
L
ERs32 → @(d:16, ERd)
6
— — ↕
↕
0 —
10
MOV.L ERs, @(d:24,
ERd)
L
ERs32 → @(d:24, ERd)
10
— — ↕
↕
0 —
14
MOV.L ERs, @–ERd
L
ERd32–4 → ERd32
ERs32 → @ERd
— — ↕
↕
0 —
10
MOV.L ERs, @aa:16
L
ERs32 → @aa:16
6
— — ↕
↕
0 —
10
MOV.L ERs, @aa:24
L
ERs32 → @aa:24
8
— — ↕
↕
0 —
12
POP.W Rn
W @SP → Rn16
SP+2 → SP
2 — — ↕
↕
0 —
6
POP.L ERn
L
4 — — ↕
↕
0 —
10
4
4
@SP → ERn32
SP+4 → SP
450
Table A-1 Instruction Set (cont)
C
Normal
Condition Code
I
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
H N
Z
V
2 — — ↕
↕
0 —
6
4 — — ↕
↕
0 —
10
PUSH.W Rn
W SP–2 → SP
Rn16 → @SP
PUSH.L ERn
L
SP–4 → SP
ERn32 → @SP
MOVFPE @aa:16,
Rd
B
Cannot be used in the
H8/3032 Series
4
Cannot be used in the H8/3032
Series
MOVTPE Rs,
@aa:16
B
Cannot be used in the
H8/3032 Series
4
Cannot be used in the H8/3032
Series
Arithmetic instructions
Condition Code
I
H N
Z
V
C
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
2
Rd8+Rs8 → Rd8
@–ERn/@ERn+
Rd8+#xx:8 → Rd8
B
@(d, ERn)
B
@ERn
ADD.B Rs, Rd
Rn
ADD.B #xx:8, Rd
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Normal
2.
— ↕
↕
↕
↕
↕
2
2
— ↕
↕
↕
↕
↕
2
— 1
↕
↕
↕
↕
4
2
— 1
↕
↕
↕
↕
2
— 2
↕
↕
↕
↕
6
2
— 2
↕
↕
↕
↕
2
ADD.W #xx:16, Rd
W Rd16+#xx:16 → Rd16
ADD.W Rs, Rd
W Rd16+Rs16 → Rd16
ADD.L #xx:32, ERd
L
ERd32+#xx:32 →
ERd32
ADD.L ERs, ERd
L
ERd32+ERs32 →
ERd32
ADDX.B #xx:8, Rd
B
Rd8+#xx:8 +C → Rd8
— ↕
↕
3
↕
↕
2
ADDX.B Rs, Rd
B
Rd8+Rs8 +C → Rd8
2
— ↕
↕
3
↕
↕
2
ADDS.L #1, ERd
L
ERd32+1 → ERd32
2
— — — — — —
2
ADDS.L #2, ERd
L
ERd32+2 → ERd32
2
— — — — — —
2
4
6
2
ADDS.L #4, ERd
L
ERd32+4 → ERd32
2
— — — — — —
2
INC.B Rd
B
Rd8+1 → Rd8
2
— — ↕
2
↕
↕ —
INC.W #1, Rd
W Rd16+1 → Rd16
2
— — ↕
↕
↕ —
2
INC.W #2, Rd
W Rd16+2 → Rd16
2
— — ↕
↕
↕ —
2
451
TIable A-1 Instruction Set (cont)
H N
Z
V
C
Normal
Condition Code
I
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
INC.L #1, ERd
L
ERd32+1 → ERd32
2
— — ↕
↕
↕ —
2
INC.L #2, ERd
L
ERd32+2 → ERd32
2
— — ↕
↕
↕ —
2
DAA Rd
B
Rd8 decimal adjust
→ Rd8
2
— *
↕
↕
* —
2
SUB.B Rs, Rd
B
Rd8–Rs8 → Rd8
2
— ↕
↕
↕
↕
↕
2
SUB.W #xx:16, Rd
W Rd16–#xx:16 → Rd16
— 1
↕
↕
↕
↕
4
SUB.W Rs, Rd
W Rd16–Rs16 → Rd16
— 1
↕
↕
↕
↕
2
SUB.L #xx:32, ERd
L
ERd32–#xx:32
→ ERd32
— 2
↕
↕
↕
↕
6
SUB.L ERs, ERd
L
ERd32–ERs32
→ ERd32
— 2
↕
↕
↕
↕
2
SUBX.B #xx:8, Rd
B
Rd8–#xx:8–C → Rd8
— ↕
↕
3
↕
↕
2
SUBX.B Rs, Rd
B
Rd8–Rs8–C → Rd8
2
— ↕
↕
3
↕
↕
2
SUBS.L #1, ERd
L
ERd32–1 → ERd32
2
— — — — — —
2
SUBS.L #2, ERd
L
ERd32–2 → ERd32
2
— — — — — —
2
SUBS.L #4, ERd
L
ERd32–4 → ERd32
2
— — — — — —
2
Rd8–1 → Rd8
4
2
6
2
2
DEC.B Rd
B
2
— — ↕
↕
↕ —
2
DEC.W #1, Rd
W Rd16–1 → Rd16
2
— — ↕
↕
↕ —
2
DEC.W #2, Rd
W Rd16–2 → Rd16
2
— — ↕
↕
↕ —
2
DEC.L #1, ERd
L
2
— — ↕
↕
↕ —
2
ERd32–1 → ERd32
DEC.L #2, ERd
L
ERd32–2 → ERd32
2
— — ↕
↕
↕ —
2
DAS.Rd
B
Rd8 decimal adjust
→ Rd8
2
— *
↕
↕
* —
2
MULXU. B Rs, Rd
B
Rd8 × Rs8 → Rd16
(unsigned multiplication)
2
— — — — — —
14
MULXU. W Rs, ERd
W Rd16 × Rs16 → ERd32
(unsigned multiplication)
2
— — — — — —
22
MULXS. B Rs, Rd
B
4
— — ↕
↕ — —
16
MULXS. W Rs, ERd
W Rd16 × Rs16 → ERd32
(signed multiplication)
4
— — ↕
↕ — —
24
DIVXU. B Rs, Rd
B
2
— — 6
7 — —
14
Rd8 × Rs8 → Rd16
(signed multiplication)
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(unsigned division)
452
Table A-1 Instruction Set (cont)
H N
Z
V
C
Normal
Condition Code
I
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
DIVXU. W Rs, ERd
W ERd32 ÷ Rs16 →ERd32
(Ed: remainder,
Rd: quotient)
(unsigned division)
2
— — 6
7 — —
22
DIVXS. B Rs, Rd
B
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
4
— — 8
7 — —
16
DIVXS. W Rs, ERd
W ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(signed division)
4
— — 8
7 — —
24
— ↕
↕
↕
↕
↕
2
2
— ↕
↕
↕
↕
↕
2
— 1
↕
↕
↕
↕
4
2
— 1
↕
↕
↕
↕
2
— 2
↕
↕
↕
↕
4
2
— 2
↕
↕
↕
↕
2
CMP.B #xx:8, Rd
B
Rd8–#xx:8
CMP.B Rs, Rd
B
Rd8–Rs8
CMP.W #xx:16, Rd
W Rd16–#xx:16
CMP.W Rs, Rd
W Rd16–Rs16
CMP.L #xx:32, ERd
L
ERd32–#xx:32
CMP.L ERs, ERd
L
ERd32–ERs32
NEG.B Rd
B
0–Rd8 → Rd8
NEG.W Rd
W 0–Rd16 → Rd16
2
4
6
2
— ↕
↕
↕
↕
↕
2
2
— ↕
↕
↕
↕
↕
2
NEG.L ERd
L
0–ERd32 → ERd32
2
— ↕
↕
↕
↕
↕
2
EXTU.W Rd
W 0 → (<bits 15 to 8>
of Rd16)
2
— — 0
↕
0 —
2
EXTU.L ERd
L
0 → (<bits 31 to 16>
of Rd32)
2
— — 0
↕
0 —
2
EXTS.W Rd
W (<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
2
— — ↕
↕
0 —
2
EXTS.L ERd
L
2
— — ↕
↕
0 —
2
(<bit 15> of Rd32) →
(<bits 31 to 16> of
ERd32)
453
Table A-1 Instruction Set (cont)
Logic instructions
B
Rd8∧#xx:8 → Rd8
B
Rd8∧Rs8 → Rd8
AND.W #xx:16, Rd
W Rd16∧#xx:16 → Rd16
AND.W Rs, Rd
W Rd16∧Rs16 → Rd16
AND.L #xx:32, ERd
L
ERd32∧#xx:32 → ERd32
AND.L ERs, ERd
L
ERd32∧ERs32 → ERd32
OR.B #xx:8, Rd
B
Rd8∨#xx:8 → Rd8
OR.B Rs, Rd
B
Rd8∨Rs8 → Rd8
OR.W #xx:16, Rd
W Rd16∨#xx:16 → Rd16
OR.W Rs, Rd
W Rd16∨Rs16 → Rd16
OR.L #xx:32, ERd
L
ERd32∨#xx:32 → ERd32
OR.L ERs, ERd
L
ERd32∨ERs32 → ERd32
XOR.B #xx:8, Rd
B
Rd8⊕#xx:8 → Rd8
XOR.B Rs, Rd
B
Rd8⊕Rs8 → Rd8
2
4
2
6
4
2
2
4
2
6
4
Condition Code
I
H N
Z
V
C
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
2
AND.B #xx:8, Rd
AND.B Rs, Rd
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Normal
3.
— — ↕
↕
0 —
2
— — ↕
↕
0 —
2
— — ↕
↕
0 —
4
— — ↕
↕
0 —
2
— — ↕
↕
0 —
6
— — ↕
↕
0 —
4
— — ↕
↕
0 —
2
— — ↕
↕
0 —
2
— — ↕
↕
0 —
4
— — ↕
↕
0 —
2
— — ↕
↕
0 —
6
— — ↕
↕
0 —
4
— — ↕
↕
0 —
2
2
— — ↕
↕
0 —
2
— — ↕
↕
0 —
4
2
— — ↕
↕
0 —
2
2
XOR.W #xx:16, Rd
W Rd16⊕#xx:16 → Rd16
XOR.W Rs, Rd
W Rd16⊕Rs16 → Rd16
XOR.L #xx:32, ERd
L
ERd32⊕#xx:32 → ERd32
— — ↕
↕
0 —
6
XOR.L ERs, ERd
L
ERd32⊕ERs32 → ERd32
4
— — ↕
↕
0 —
4
NOT.B Rd
B
¬ Rd8 → Rd8
2
— — ↕
↕
0 —
2
NOT.W Rd
W ¬ Rd16 → Rd16
2
— — ↕
↕
0 —
2
NOT.L ERd
L
¬ Rd32 → Rd32
2
— — ↕
↕
0 —
2
4
6
454
Table A-1 Instruction Set (cont)
Shift instructions
SHAL.B Rd
B
SHAL.W Rd
W
SHAL.L ERd
L
SHAR.B Rd
B
SHAR.W Rd
W
SHAR.L ERd
L
SHLL.B Rd
B
SHLL.W Rd
W
SHLL.L ERd
L
SHLR.B Rd
B
SHLR.W Rd
W
SHLR.L ERd
C
ROTXL.B Rd
B
W
ROTXL.L ERd
L
ROTXR.B Rd
B
ROTXR.W Rd
W
ROTXR.L ERd
L
ROTL.B Rd
B
ROTL.W Rd
W
ROTL.L ERd
L
ROTR.B Rd
B
ROTR.W Rd
W
ROTR.L ERd
L
0
MSB
LSB
C
MSB
LSB
C
0
MSB
LSB
0
C
MSB
LSB
C
MSB
LSB
C
MSB
LSB
C
MSB
LSB
C
MSB
LSB
Condition Code
I
H N
Z
V
C
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
L
ROTXL.W Rd
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Normal
4.
2
— — ↕
↕
↕
↕
2
2
— — ↕
↕
↕
↕
2
2
— — ↕
↕
↕
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
2
— — ↕
↕
0
↕
2
455
Table A-1 Instruction Set (cont)
Bit manipulation instructions
BSET #xx:3, @aa:8
B
(#xx:3 of @aa:8) ← 1
BSET Rn, Rd
B
(Rn8 of Rd8) ← 1
BSET Rn, @ERd
B
(Rn8 of @ERd) ← 1
BSET Rn, @aa:8
B
(Rn8 of @aa:8) ← 1
BCLR #xx:3, Rd
B
(#xx:3 of Rd8) ← 0
BCLR #xx:3, @ERd
B
(#xx:3 of @ERd) ← 0
BCLR #xx:3, @aa:8
B
(#xx:3 of @aa:8) ← 0
BCLR Rn, Rd
B
(Rn8 of Rd8) ← 0
BCLR Rn, @ERd
B
(Rn8 of @ERd) ← 0
BCLR Rn, @aa:8
B
(Rn8 of @aa:8) ← 0
BNOT #xx:3, Rd
B
(#xx:3 of Rd8) ←
¬ (#xx:3 of Rd8)
BNOT #xx:3, @ERd
B
(#xx:3 of @ERd) ←
¬ (#xx:3 of @ERd)
BNOT #xx:3, @aa:8
B
(#xx:3 of @aa:8) ←
¬ (#xx:3 of @aa:8)
BNOT Rn, Rd
B
(Rn8 of Rd8) ←
¬ (Rn8 of Rd8)
BNOT Rn, @ERd
B
(Rn8 of @ERd) ←
¬ (Rn8 of @ERd)
BNOT Rn, @aa:8
B
(Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
BTST #xx:3, Rd
B
(#xx:3 of Rd8) → Z
BTST #xx:3, @ERd
B
(#xx:3 of @ERd) → Z
BTST #xx:3, @aa:8
B
(#xx:3 of @aa:8) → Z
BTST Rn, Rd
B
(Rn8 of @Rd8) → Z
BTST Rn, @ERd
B
(Rn8 of @ERd) → Z
BTST Rn, @aa:8
B
(Rn8 of @aa:8) → Z
BLD #xx:3, Rd
B
(#xx:3 of Rd8) → C
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
456
Condition Code
I
H N
Z
V
C
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
(#xx:3 of @ERd) ← 1
@–ERn/@ERn+
(#xx:3 of Rd8) ← 1
B
@(d, ERn)
B
BSET #xx:3, @ERd
@ERn
BSET #xx:3, Rd
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Normal
5.
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — ↕ — —
2
— — — ↕ — —
6
— — — ↕ — —
6
— — — ↕ — —
2
— — — ↕ — —
6
— — — ↕ — —
6
— — — — — ↕
2
Table A-1 Instruction Set (cont)
BLD #xx:3, @ERd
B
(#xx:3 of @ERd) → C
BLD #xx:3, @aa:8
B
(#xx:3 of @aa:8) → C
BILD #xx:3, Rd
B
¬ (#xx:3 of Rd8) → C
BILD #xx:3, @ERd
B
¬ (#xx:3 of @ERd) → C
BILD #xx:3, @aa:8
B
¬ (#xx:3 of @aa:8) → C
BST #xx:3, Rd
B
C → (#xx:3 of Rd8)
BST #xx:3, @REd
B
C → (#xx:3 of @ERd)
BST #xx:3, @aa:8
B
C → (#xx:3 of @aa:8)
BIST #xx:3, Rd
B
C → (#xx:3 of Rd8)
BIST #xx:3, @ERd
B
C → (#xx:3 of @ERd24)
BIST #xx:3, @aa:8
B
C → (#xx:3 of @aa:8)
BAND #xx:3, Rd
B
C∧(#xx:3 of Rd8) → C
BAND #xx:3, @ERd
B
C∧(#xx:3 of @ERd24) → C
BAND #xx:3, @aa:8
B
C∧(#xx:3 of @aa:8) → C
BIAND #xx:3, Rd
B
C∧(#xx:3 of Rd8) → C
BIAND #xx:3, @ERd
B
C∧(#xx:3 of @ERd24) → C
BIAND #xx:3, @aa:8
B
C∧(#xx:3 of @aa:8) → C
BOR #xx:3, Rd
B
C∨(#xx:3 of Rd8) → C
BOR #xx:3, @ERd
B
C∨(#xx:3 of @ERd24) → C
BOR #xx:3, @aa:8
B
C∨(#xx:3 of @aa:8) → C
BIOR #xx:3, Rd
B
C∨(#xx:3 of Rd8) → C
BIOR #xx:3, @ERd
B
C∨(#xx:3 of @ERd24) → C
BIOR #xx:3, @aa:8
B
C∨(#xx:3 of @aa:8) → C
BXOR #xx:3, Rd
B
C⊕(#xx:3 of Rd8) → C
BXOR #xx:3, @ERd
B
C⊕(#xx:3 of @ERd24) → C
BXOR #xx:3, @aa:8
B
C⊕(#xx:3 of @aa:8) → C
BIXOR #xx:3, Rd
B
C⊕(#xx:3 of Rd8) → C
BIXOR #xx:3, @ERd
B
C⊕(#xx:3 of @ERd24) → C
BIXOR #xx:3, @aa:8
B
C⊕(#xx:3 of @aa:8) → C
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
457
H N
Z
V
C
Normal
Condition Code
I
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
— — — — — ↕
6
— — — — — ↕
6
— — — — — ↕
2
— — — — — ↕
6
— — — — — ↕
6
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — ↕
2
— — — — — ↕
6
— — — — — ↕
6
— — — — — ↕
2
— — — — — ↕
6
— — — — — ↕
6
— — — — — ↕
2
— — — — — ↕
6
— — — — — ↕
6
— — — — — ↕
2
— — — — — ↕
6
— — — — — ↕
6
— — — — — ↕
2
— — — — — ↕
6
— — — — — ↕
6
— — — — — ↕
2
— — — — — ↕
6
— — — — — ↕
6
Table A-1 Instruction Set (cont)
Branching instructions
BRA d:8 (BT d:8)
—
BRA d:16 (BT d:16)
—
BRN d:8 (BF d:8)
—
BRN d:16 (BF d:16)
—
BHI d:8
—
BHI d:16
—
BLS d:8
—
BLS d:16
—
BCC d:8 (BHS d:8)
—
BCC d:16 (BHS d:16)
—
BCS d:8 (BLO d:8)
—
BCS d:16 (BLO d:16)
—
BNE d:8
—
BNE d:16
—
BEQ d:8
—
BEQ d:16
—
BVC d:8
—
BVC d:16
—
BVS d:8
—
BVS d:16
—
BPL d:8
—
BPL d:16
—
BMI d:8
—
BMI d:16
—
BGE d:8
—
BGE d:16
—
BLT d:8
—
BLT d:16
—
BGT d:8
—
BGT d:16
—
If condition Always
is true then
PC ←
PC+d else Never
next;
C∨Z=0
C∨Z=1
C=0
C=1
Z=0
Z=1
V=0
V=1
N=0
N=1
N⊕V = 0
N⊕V = 1
Z ∨ (N⊕V)
=0
458
Condition Code
I
H N
Z
V
C
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Operation
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Normal
6.
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
2
— — — — — —
4
4
— — — — — —
6
Table A-1 Instruction Set (cont)
BLE d:8
—
BLE d:16
—
If condition
is true then
PC ←
PC+d else
next;
Z ∨ (N⊕V)
=1
H N
Z
V
C
Normal
Condition Code
I
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Operation
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
— — — — — —
4
4
— — — — — —
6
JMP @ERn
— PC ← ERn
JMP @aa:24
— PC ← aa:24
JMP @@aa:8
— PC ← @aa:8
— — — — — —
8
10
BSR d:8
— PC → @–SP
PC ← PC+d:8
2
— — — — — —
6
8
BSR d:16
— PC → @–SP
PC ← PC+d:16
4
— — — — — —
8
10
JSR @ERn
— PC → @–SP
PC ← @ERn
— — — — — —
6
8
JSR @aa:24
— PC → @–SP
PC ← @aa:24
— — — — — —
8
10
JSR @@aa:8
— PC → @–SP
PC ← @aa:8
— — — — — —
8
12
RTS
— PC ← @SP+
2 — — — — — —
8
10
2
4
2
2
4
2
459
— — — — — —
4
— — — — — —
6
Table A-1 Instruction Set (cont)
7.
System control instructions
C
Normal
Advanced
No. of
States *1
2 — — — — — —
14
16
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Condition Code
I
H N
Z
V
TRAPA #x:2
— PC → @–SP
CCR → @–SP
<vector> → PC
RTE
— CCR ← @SP+
PC ← @SP+
↕
↕
10
SLEEP
— Transition to powerdown state
— — — — — —
2
LDC #xx:8, CCR
B
#xx:8 → CCR
↕
↕
↕
↕
↕
↕
2
LDC Rs, CCR
B
Rs8 → CCR
↕
↕
↕
↕
↕
↕
2
LDC @ERs, CCR
W @ERs → CCR
↕
↕
↕
↕
↕
↕
6
LDC @(d:16, ERs),
CCR
W @(d:16, ERs) → CCR
6
↕
↕
↕
↕
↕
↕
8
LDC @(d:24, ERs),
CCR
W @(d:24, ERs) → CCR
10
↕
↕
↕
↕
↕
↕
12
LDC @ERs+, CCR
W @ERs → CCR
ERs32+2 → ERs32
↕
↕
↕
↕
↕
↕
8
LDC @aa:16, CCR
W @aa:16 → CCR
6
↕
↕
↕
↕
↕
↕
8
LDC @aa:24, CCR
W @aa:24 → CCR
8
↕
↕
↕
↕
↕
↕
10
2
2
4
4
CCR → Rd8
2
↕
↕
↕
↕
STC CCR, Rd
B
STC CCR, @ERd
W CCR → @ERd
— — — — — —
2
— — — — — —
6
STC CCR, @(d:16,
ERs)
W CCR → @(d:16, ERd)
6
— — — — — —
8
STC CCR, @(d:24,
ERs)
W CCR → @(d:24, ERd)
10
— — — — — —
12
STC CCR, @–ERs
W ERd32–2 → ERd32
CCR → @ERd
— — — — — —
8
STC CCR, @aa:16
W CCR → @aa:16
6
— — — — — —
8
STC CCR, @aa:24
W CCR → @aa:24
8
— — — — — —
10
ANDC #xx:8, CCR
B
CCR∧#xx:8 → CCR
2
↕
↕
↕
↕
↕
↕
2
ORC #xx:8, CCR
B
CCR∨#xx:8 → CCR
2
↕
↕
↕
↕
↕
↕
2
XORC #xx:8, CCR
B
CCR⊕#xx:8 → CCR
2
↕
↕
↕
↕
↕
↕
2
NOP
— PC ← PC+2
2 — — — — — —
2
4
4
460
Table A-1 Instruction Set (cont)
Block transfer instructions
Condition Code
I
H N
Z
V
C
EEPMOV. B
— if R4L ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until
R4L=0
else next
4 — — — — — —
8+
4n*2
EEPMOV. W
— if R4 ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4
until
R4=0
else next
4 — — — — — —
8+
4n*2
Notes: 1. The number of states is the number of states required for execution when the instruction and its
operands are located in on-chip memory. For other cases see section A.3, Number of States
Required for Execution.
2. n is the value set in register R4L or R4.
1 Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
2 Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
3 Retains its previous value when the result is zero; otherwise cleared to 0.
4 Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
5 The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
6 Set to 1 when the divisor is negative; otherwise cleared to 0.
7 Set to 1 when the divisor is zero; otherwise cleared to 0.
8 Set to 1 when the quotient is negative; otherwise cleared to 0.
461
Advanced
No. of
States *1
Implied
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Operation
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Normal
8.
A.2 Operation Code Maps
Table A-2 Operation Code Map (1)
1st byte 2nd byte
AH AL BH BL
Instruction code:
AL
AH
0
1
Instruction when most significant bit of BH is 0.
Instruction when most significant bit of BH is 1.
0
1
2
3
4
5
6
7
NOP
Table A.2
(2)
STC
LDC
ORG
XORC
ANDC
LDC
ADD
Table A.2 Table A.2
(2)
(2)
OR.B
XOR.B
AND.B
Table A.2
(2)
SUB
Table A.2 Table A.2
(2)
(2)
BCC
BCS
BNE
BEQ
BVC
RTS
BSR
RTE
TRAPA
Table A.2
(2)
Table A.2 Table A.2 Table A.2 Table A.2
(2)
(2)
(2)
(2)
8
9
A
B
C
D
E
F
MOV
ADDX
Table A.2
(2)
CMP
SUBX
Table A.2
(2)
BGT
BLE
2
3
4
462
5
BRA
BRN
BHI
BLS
MULXU.B DIVXU.B MULXU.W DIVXU.W
BST
6
OR.W
BSET
BNOT
BCLR
BTST
BOR
XOR.W
BXOR
AND.W
BAND
7
BIOR
BIXOR
BIAND
MOV.B
BIST
BLD
BVS
BPL
BMI
BGE
JMP
BSR
ADD
9
ADDX
A
CMP
B
SUBX
C
OR
D
XOR
E
AND
F
MOV
JSR
MOV
Table A.2 Table A.2
MOV.B/W
EEPMOV
(2)
(2)
BILD
8
BLT
Table A.2
(3)
Table A-2 Operation Code Map (2)
1st byte 2nd byte
AH AL BH BL
Instruction code:
BH
AH AL
0
1
01
MOV
0A
INC
0B
ADDS
0F
DAA
2
3
4
5
6
7
LDC/STC
8
9
A
B
C
D
E
SLEEP
F
Table A.2
(3)
Table A.2 Table A.2
(3)
(3)
ADD
INC
INC
ADDS
463
INC
INC
EXTS
EXTS
DEC
DEC
MOV
10
SHLL
SHLL
SHAL
SHAL
11
SHLR
SHLR
SHAR
SHAR
12
ROTXL
ROTXL
ROTL
ROTL
13
ROTXR
ROTXR
ROTR
ROTR
17
NOT
NOT
NEG
NEG
EXTU
EXTU
1A
DEC
1B
SUBS
1F
DAS
58
BRA
BRN
BHI
BLS
BCC
BCS
BNE
79
MOV
ADD
CMP
SUB
OR
XOR
AND
7A
MOV
ADD
CMP
SUB
OR
XOR
AND
SUB
DEC
SUB
DEC
CMP.L
BEQ
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
Table A-2 Operation Code Map (3)
1st byte 2nd byte 3rd byte 4th byte
AH AL BH BL CH CL DH DL
Instruction code:
Instruction when most significant bit of DH is 0.
Instruction when most significant bit of DH is 1.
C
AH
ALBH
BLCH
0
1
2
3
4
5
6
7
MULXS
MULXS
DIVXS
01D05
DIVXS
01F06
OR
464
7Cr06 * 1
BTST
7Cr07 * 1
BTST
BOR
BIOR
7Dr06 * 1
BSET
BNOT
XOR
BXOR
BIXOR
AND
BAND
BIAND
BLD
BILD
BST
BCLR
BIST
7Dr07 * 1
9
LDC
STC
01406
01C05
8
BSET
BNOT
BCLR
7Eaa6 * 2
BTST
7Eaa7 * 2
BTST
BOR
BIOR
7Faa6 * 2
BSET
BNOT
BCLR
7Faa7 * 2
BSET
BNOT
BCLR
BXOR
BIXOR
BAND
BIAND
BLD
BILD
BST
BIST
Notes: 1. r is the register designation field.
2. aa is the absolute address field.
A
B
LBC
C
D
LDC
STC
STC
E
F
LDC
STC
A.3 Number of States Required for Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8/300H CPU. Table A-3 indicates the number of instruction fetch, data
read/write, and other cycles occurring in each instruction. Table A-2 indicates the number of states
required per cycle according to the bus size. The number of states required for execution of an
instruction can be calculated from these two tables as follows:
Number of states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed with 8-bit bus width, external devices accessed in three states with one wait state and
16-bit bus width.
BSET #0, @FFFFFC7:8
From table A-3, I = L = 2 and J = K = M = N = 0
From table A-2, SI = 4 and SL = 3
Number of states = 2 × 4 + 2 × 3 = 14
JSR @@30
From table A-3, I = J = K = 2 and L = M = N = 0
From table A-2, SI = SJ = SK = 4
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
465
Table A-2 Number of States per Cycle
Access Conditions
External Device
On-Chip Supporting Module
Cycle
8-Bit Bus
16-Bit Bus
On-Chip
Memory
8-Bit
Bus
16-Bit
Bus
2-State 3-State 2-State 3-State
Access Access Access Access
2
6
3
4
6 + 2m
Instruction fetch
SI
Branch address read
SJ
Stack operation
SK
Byte data access
SL
3
2
3+m
Word data access
SM
6
4
6 + 2m
Internal operation
SN 1
Legend
m: Number of wait states inserted into external device access
466
2
3+m
Table A-3 Number of Cycles per Instruction
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
ADD
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
ADD.L ERs, ERd
1
1
2
1
3
1
ADDS
ADDS #1/2/4, ERd
1
ADDX
ADDX #xx:8, Rd
ADDX Rs, Rd
1
1
AND
AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
1
1
2
1
3
2
ANDC
ANDC #xx:8, CCR
1
BAND
BAND #xx:3, Rd
BAND #xx:3, @ERd
BAND #xx:3, @aa:8
1
2
2
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Bcc
1
1
467
Table A-3 Number of Cycles per Instruction (cont)
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Bcc
BRA d:16 (BT d:16)
BRN d:16 (BF d:16)
BHI d:16
BLS d:16
BCC d:16 (BHS d:16)
BCS d:16 (BLO d:16)
BNE d:16
BEQ d:16
BVC d:16
BVS d:16
BPL d:16
BMI d:16
BGE d:16
BLT d:16
BGT d:16
BLE d:16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BCLR
BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
1
2
2
1
2
2
BIAND #xx:3, Rd
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
1
2
2
1
1
BILD #xx:3, Rd
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
1
2
2
1
1
BIOR #xx:8, Rd
BIOR #xx:8, @ERd
BIOR #xx:8, @aa:8
1
2
2
1
1
BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
1
2
2
2
2
BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
1
2
2
1
1
BLD #xx:3, Rd
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
1
2
2
1
1
BIAND
BILD
BIOR
BIST
BIXOR
BLD
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
468
Table A-3 Number of Cycles per Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Instruction Mnemonic
BNOT
BOR
BSET
BSR
BNOT #xx:3, Rd
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
1
2
2
1
2
2
2
2
BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
1
2
2
1
1
BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
1
2
2
1
2
2
BSR d:8
Normal
2
1
Advanced
2
2
BSR d:16 Normal
Advanced
BST
2
2
2
1
2
2
2
1
2
2
BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @ERd
BTST Rn, @aa:8
1
2
2
1
2
2
BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
1
2
2
CMP
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
1
1
2
1
3
1
DAA
DAA Rd
1
DAS
DAS Rd
1
BXOR
2
2
2
BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
BTST
2
2
2
2
1
1
1
1
1
1
469
Table A-3 Number of Cycles per Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Instruction Mnemonic
DEC
DEC.B Rd
DEC.W #1/2, Rd
DEC.L #1/2, ERd
1
1
1
DIVXS
DIVXS.B Rs, Rd
DIVXS.W Rs, ERd
2
2
12
20
DIVXU
DIVXU.B Rs, Rd
DIVXU.W Rs, ERd
1
1
12
20
EEPMOV
EEPMOV.B
EEPMOV.W
2
2
EXTS
EXTS.W Rd
EXTS.L ERd
1
1
EXTU
EXTU.W Rd
EXTU.L ERd
1
1
INC
INC.B Rd
INC.W #1/2, Rd
INC.L #1/2, ERd
1
1
1
JMP
JMP @ERn
2
JMP @aa:24
2
JMP @@aa:8 Normal
2
1
Advanced 2
2
JSR
JSR @ERn
Normal
2n + 2*1
2n + 2*1
2
2
2
2
1
Advanced 2
2
JSR @aa:24 Normal
2
Advanced 2
JSR @@aa:8 Normal
LDC
1
2
2
2
2
1
1
Advanced 2
2
2
LDC #xx:8, CCR
LDC Rs, CCR
LDC @ERs, CCR
LDC @(d:16, ERs), CCR
LDC @(d:24, ERs), CCR
LDC @ERs+, CCR
LDC @aa:16, CCR
LDC @aa:24, CCR
1
1
2
3
5
2
3
4
1
1
1
1
1
1
470
2
Table A-3 Number of Cycles per Instruction (cont)
Instruction Mnemonic
MOV
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @ERs, Rd
MOV.B @(d:16, ERs), Rd
MOV.B @(d:24, ERs), Rd
MOV.B @ERs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @ERd
MOV.B Rs, @(d:16, ERd)
MOV.B Rs, @(d:24, ERd)
MOV.B Rs, @–ERd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.B Rs, @aa:24
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @ERs, Rd
MOV.W @(d:16, ERs), Rd
MOV.W @(d:24, ERs), Rd
MOV.W @ERs+, Rd
MOV.W @aa:16, Rd
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
MOV.W Rs, @(d:16, ERd)
MOV.W Rs, @(d:24, ERd)
MOV.W Rs, @–ERd
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
MOV.L #xx:32, ERd
MOV.L ERs, ERd
MOV.L @ERs, ERd
MOV.L @(d:16, ERs), ERd
MOV.L @(d:24, ERs), ERd
MOV.L @ERs+, ERd
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs, @ERd
MOV.L ERs, @(d:16, ERd)
MOV.L ERs, @(d:24, ERd)
MOV.L ERs, @–ERd
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
1
1
1
2
4
1
1
2
3
1
2
4
1
1
2
3
2
1
1
2
4
1
2
3
1
2
4
1
2
3
3
1
2
3
5
2
3
4
2
3
5
2
3
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
471
2
2
2
2
Table A-3 Number of Cycles per Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Instruction Mnemonic
MOVFPE
MOVFPE @aa:16, Rd*2 2
@aa:16*2
1
MOVTPE
MOVTPE Rs,
MULXS
MULXS.B Rs, Rd
MULXS.W Rs, ERd
2
2
2
1
12
20
MULXU
MULXU.B Rs, Rd
MULXU.W Rs, ERd
1
1
12
20
NEG
NEG.B Rd
NEG.W Rd
NEG.L ERd
1
1
1
NOP
NOP
1
NOT
NOT.B Rd
NOT.W Rd
NOT.L ERd
1
1
1
OR
OR.B #xx:8, Rd
OR.B Rs, Rd
OR.W #xx:16, Rd
OR.W Rs, Rd
OR.L #xx:32, ERd
OR.L ERs, ERd
1
1
2
1
3
2
ORC
ORC #xx:8, CCR
1
POP
POP.W Rn
POP.L ERn
1
2
1
2
2
2
PUSH
PUSH.W Rn
PUSH.L ERn
1
2
1
2
2
2
ROTL
ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
1
1
1
ROTR
ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
1
1
1
ROTXL
ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
1
1
1
ROTXR
ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
1
1
1
RTE
RTE
2
2
472
2
Table A-3 Number of Cycles per Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Instruction Mnemonic
RTS
RTS
Normal
2
1
2
SHAL
SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
Advanced 2
1
1
1
2
2
SHAR
SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
1
1
1
SHLL
SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
1
1
1
SHLR
SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
1
1
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
STC CCR, @ERd
2
STC CCR, @(d:16, ERd) 3
STC CCR, @(d:24, ERd) 5
STC CCR, @–ERd
2
STC CCR, @aa:16
3
STC CCR, @aa:24
4
1
1
1
1
1
1
2
SUB
SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
1
2
1
3
1
SUBS
SUBS #1/2/4, ERd
1
SUBX
SUBX #xx:8, Rd
SUBX Rs, Rd
1
1
TRAPA
TRAPA #x:2 Normal
2
1
2
4
Advanced 2
2
2
4
XOR
XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
1
1
2
1
3
2
XORC
XORC #xx:8, CCR
1
Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each.
2. Not available in the H8/3032 Series.
473
Appendix B Register Field
B.1 Register Addresses and Bit Names
Address Register
(low)
Name
Data
Bus
Width
Bit Names
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
H'1C
H'1D
H'1E
H'1F
H'20
—
—
—
—
—
—
—
—
—
H'21
—
—
—
—
—
—
—
—
—
H'22
—
—
—
—
—
—
—
—
—
H'23
—
—
—
—
—
—
—
—
—
H'24
—
—
—
—
—
—
—
—
—
H'25
—
—
—
—
—
—
—
—
—
H'26
—
—
—
—
—
—
—
—
—
H'27
—
—
—
—
—
—
—
—
—
H'28
—
—
—
—
—
—
—
—
—
H'29
—
—
—
—
—
—
—
—
—
H'2A
—
—
—
—
—
—
—
—
—
H'2B
—
—
—
—
—
—
—
—
—
H'2C
—
—
—
—
—
—
—
—
—
H'2D
—
—
—
—
—
—
—
—
—
H'2E
—
—
—
—
—
—
—
—
—
H'2F
—
—
—
—
—
—
—
—
—
H'30
—
—
—
—
—
—
—
—
—
H'31
—
—
—
—
—
—
—
—
—
H'32
—
—
—
—
—
—
—
—
—
H'33
—
—
—
—
—
—
—
—
—
H'34
—
—
—
—
—
—
—
—
—
H'35
—
—
—
—
—
—
—
—
—
H'36
—
—
—
—
—
—
—
—
—
H'37
—
—
—
—
—
—
—
—
—
H'38
—
—
—
—
—
—
—
—
—
H'39
—
—
—
—
—
—
—
—
—
H'3A
—
—
—
—
—
—
—
—
—
Legend
DMAC: DMA controller
(Continued on next page)
474
(Continued from preceding page)
Address Register
(low)
Name
Data
Bus
Width
Bit Names
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'3B
—
—
—
—
—
—
—
—
—
H'3C
—
—
—
—
—
—
—
—
—
H'3D
—
—
—
—
—
—
—
—
—
H'3E
—
—
—
—
—
—
—
—
—
H'3F
—
—
—
—
—
—
—
—
—
H'40
—
—
—
—
—
—
—
—
—
H'41
—
—
—
—
—
—
—
—
—
H'42
—
—
—
—
—
—
—
—
—
H'43
—
—
—
—
—
—
—
—
—
H'44
—
—
—
—
—
—
—
—
—
H'45
—
—
—
—
—
—
—
—
—
H'46
—
—
—
—
—
—
—
—
—
H'47
—
—
—
—
—
—
—
—
—
H'48
—
—
—
—
—
—
—
—
—
H'49
—
—
—
—
—
—
—
—
—
H'4A
—
—
—
—
—
—
—
—
—
H'4B
—
—
—
—
—
—
—
—
—
H'4C
—
—
—
—
—
—
—
—
—
H'4D
—
—
—
—
—
—
—
—
—
H'4E
—
—
—
—
—
—
—
—
—
H'4F
—
—
—
—
—
—
—
—
—
H'50
—
—
—
—
—
—
—
—
—
H'51
—
—
—
—
—
—
—
—
—
H'52
—
—
—
—
—
—
—
—
—
H'53
—
—
—
—
—
—
—
—
—
H'54
—
—
—
—
—
—
—
—
—
H'55
—
—
—
—
—
—
—
—
—
H'56
—
—
—
—
—
—
—
—
—
H'57
—
—
—
—
—
—
—
—
—
H'58
—
—
—
—
—
—
—
—
—
H'59
—
—
—
—
—
—
—
—
—
H'5A
—
—
—
—
—
—
—
—
—
H'5B
—
—
—
—
—
—
—
—
—
H'5C
—
—
—
—
—
—
—
—
—
H'5D
—
—
—
—
—
—
—
—
—
H'5E
—
—
—
—
—
—
—
—
—
H'5F
—
—
—
—
—
—
—
—
—
Module Name
(Continued on next page)
475
(Continued from preceding page)
Address Register
(low)
Name
Data
Bus
Width
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module Name
H'60
TSTR
8
—
—
—
STR4
STR3
STR2
STR1
STR0
H'61
TSNC
8
—
—
—
SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
ITU
(all channels)
H'62
TMDR
8
MDF
FDIR
PWM4
PWM3
PWM2
PWM1
PWM0
H'63
TFCR
8
—
—
CMD1
CMD0
BFB4
BFA4
BFB3
BFA3
H'64
TCR0
8
—
CCLR1
CCLR0
CKEG1 CKEG0 TPSC2
TPSC1
TPSC0
H'65
TIOR0
8
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
H'66
TIER0
8
—
—
—
—
—
OVIE
IMIEB
IMIEA
H'67
TSR0
8
—
—
—
—
—
OVF
IMFB
IMFA
H'68
TCNT0H
16
Bit Names
H'69
TCNT0L
H'6A
GRA0H
H'6B
GRA0L
H'6C
GRB0H
H'6D
GRB0L
H'6E
TCR1
8
—
CCLR1
CCLR0
CKEG1 CKEG0 TPSC2
TPSC1
TPSC0
H'6F
TIOR1
8
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
H'70
TIER1
8
—
—
—
—
—
OVIE
IMIEB
IMIEA
H'71
TSR1
8
—
—
—
—
—
OVF
IMFB
IMFA
H'72
TCNT1H
16
H'73
TCNT1L
H'74
GRA1H
H'75
GRA1L
H'76
GRB1H
H'77
GRB1L
H'78
TCR2
8
—
CCLR1
CCLR0
CKEG1 CKEG0 TPSC2
TPSC1
TPSC0
H'79
TIOR2
8
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
H'7A
TIER2
8
—
—
—
—
—
OVIE
IMIEB
IMIEA
H'7B
TSR2
8
—
—
—
—
—
OVF
IMFB
IMFA
H'7C
TCNT2H
16
H'7D
TCNT2L
H'7E
GRA2H
H'7F
GRA2L
H'80
GRB2H
H'81
GRB2L
ITU channel 0
16
16
ITU channel 1
16
16
ITU channel 2
16
16
Legend
ITU: 16-bit integrated timer unit
(Continued on next page)
476
(Continued from preceding page)
Address Register
(low)
Name
Data
Bus
Width
Bit 7
Bit 6
Bit 5
Bit 4
Bit 1
Bit 0
Module Name
H'82
TCR3
8
—
CCLR1
CCLR0
CKEG1 CKEG0 TPSC2
TPSC1
TPSC0
ITU channel 3
H'83
TIOR3
8
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
H'84
TIER3
8
—
—
—
—
—
OVIE
IMIEB
IMIEA
H'85
TSR3
8
—
—
—
—
—
OVF
IMFB
IMFA
H'86
TCNT3H
16
H'87
TCNT3L
H'88
GRA3H
H'89
GRA3L
H'8A
GRB3H
H'8B
GRB3L
H'8C
BRA3H
H'8D
BRA3L
H'8E
BRB3H
H'8F
BRB3L
H'90
TOER
8
—
—
EXB4
EXA4
EB3
EB4
EA4
EA3
H'91
TOCR
8
—
—
—
XTGD
—
—
OLS4
OLS3
ITU
(all channels)
H'92
TCR4
8
—
CCLR1
CCLR0
CKEG1 CKEG0 TPSC2
TPSC1
TPSC0
ITU channel 4
H'93
TIOR4
8
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
H'94
TIER4
8
—
—
—
—
—
OVIE
IMIEB
IMIEA
H'95
TSR4
8
—
—
—
—
—
OVF
IMFB
IMFA
H'96
TCNT4H
16
H'97
TCNT4L
H'98
GRA4H
H'99
GRA4L
H'9A
GRB4H
H'9B
GRB4L
H'9C
BRA4H
H'9D
BRA4L
H'9E
BRB4H
H'9F
BRB4L
Bit Names
Bit 3
Bit 2
16
16
16
16
16
16
16
16
Legend
ITU: 16-bit integrated timer unit
(Continued on next page)
477
(Continued from preceding page)
Address Register
(low)
Name
Data
Bus
Width
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
H'A0
8
—
—
—
—
G3NOV G2NOV G1NOV G0NOV
TPMR
Bit Names
Bit 2
Bit 1
Bit 0
H'A1
TPCR
8
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
H'A2
NDERB
8
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
H'A3
NDERA
8
NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
H'A4
NDRB*1
8
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
8
NDR15
NDR14
NDR13
NDR12
—
—
—
—
8
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
8
NDR7
NDR6
NDR5
NDR4
—
—
—
—
8
—
—
—
—
—
—
—
—
8
—
—
—
—
NDR11
NDR10
NDR9
NDR8
8
—
—
—
—
—
—
—
—
H'A5
H'A6
NDRA*1
NDRB*1
H'A7
NDRA*1
8
—
—
—
—
NDR3
NDR2
NDR1
NDR0
H'A8
TCSR*2
8
OVF
WT/IT
TME
—
—
CKS2
CKS1
CKS0
H'A9
TCNT*2
8
H'AA
—
—
—
—
—
—
—
—
—
H'AB
RSTCSR*3 8
WRST
RSTOE —
—
—
—
—
—
H'AC
—
—
—
—
—
—
—
—
—
H'AD
—
—
—
—
—
—
—
—
—
H'AE
—
—
—
—
—
—
—
—
—
H'AF
—
—
—
—
—
—
—
—
—
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
H'B0
SMR
8
H'B1
BRR
8
H'B2
SCR
8
H'B3
TDR
8
H'B4
SSR
8
H'B5
RDR
8
H'B6
—
—
—
—
—
—
—
—
—
H'B7
—
—
—
—
—
—
—
—
—
Module Name
TPC
WDT
SCI channel 0
Notes: 1. The address depends on the output trigger setting.
2. For write access to TCSR and TCNT, see section 10.2.4, Notes on Register Access.
3. For write access to RSTCSR, see section 10.2.4, Notes on Register Access.
Legend
TPC: Programmable timing pattern controller
WDT: Watchdog timer
SCI: Serial communication interface
(Continued on next page)
478
(Continued from preceding page)
Address Register
(low)
Name
Data
Bus
Width
Bit Names
Bit 3
Bit 2
Bit 1
Bit 0
H'B8
—
—
—
—
—
—
—
—
—
H'B9
—
—
—
—
—
—
—
—
—
H'BA
—
—
—
—
—
—
—
—
—
H'BB
—
—
—
—
—
—
—
—
—
H'BC
—
—
—
—
—
—
—
—
—
H'BD
—
—
—
—
—
—
—
—
—
H'BE
—
—
—
—
—
—
—
—
—
H'BF
—
—
—
—
—
—
—
—
—
H'C0
P1DDR
8
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Port 1
H'C1
P2DDR
8
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Port 2
H'C2
P1DR
8
P17
P16
P15
P14
P13
P12
P11
P10
Port 1
H'C3
P2DR
8
P27
P26
P25
P24
P23
P22
P21
P20
H'C4
P3DDR
8
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
H'C5
—
H'C6
P3DR
H'C7
—
H'C8
P5DDR
8
P57DDR P56DDR P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR
Port 5
H'C9
P6DDR
8
—
—
P65DDR P64DDR P63DDR —
—
P60DDR
Port 6
H'CA
P5DR
8
P57
P56
P55
P54
P53
P52
P51
P50
Port 5
H'CB
P6DR
8
—
—
P65
P64
P63
—
—
P60
Port 6
H'CC
—
—
—
—
—
—
—
—
—
H'CD
P8DDR
8
—
—
—
P84DDR P83DDR P82DDR P81DDR P80DDR
Port 8
H'CE
P7DR
8
P77
P76
P75
P74
P73
P72
P71
P70
Port 7
H'CF
P8DR
8
—
—
—
—
P83
P82
P81
P80
Port 8
H'D0
P9DDR
8
—
—
—
P94DDR —
P90DDR
Port 9
H'D1
PADDR
8
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Port A
H'D2
P9DR
8
—
—
—
P94
—
P92
—
P90
Port 9
H'D3
PADR
8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port A
H'D4
PBDDR
8
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
H'D5
PCDDR
8
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Port C
8
Bit 7
Bit 6
Bit 5
Bit 4
—
—
—
—
—
—
—
—
P37
P36
P35
P34
P33
P32
P31
P30
—
—
—
—
—
—
—
—
P92DDR —
Module Name
Port 2
Port 2
Port 3
Port B
H'D6
PBDR
8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port B
H'D7
PCDR
8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Port C
(Continued on next page)
479
(Continued from preceding page)
Address Register
(low)
Name
H'D8
P2PCR
H'D9
—
H'DA
—
H'DB
P5PCR
H'DC
Data
Bus
Width
Bit Names
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P53PCR P52PCR P51PCR P50PCR
—
—
—
—
H'DD
—
—
—
—
—
—
—
—
—
H'DE
—
—
—
—
—
—
—
—
—
H'DF
—
—
—
—
—
—
—
—
—
H'E0
ADDRAH
8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'E1
ADDRAL
8
AD1
AD0
—
—
—
—
—
—
H'E2
ADDRBH
8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'E3
ADDRBL
8
AD1
AD0
—
—
—
—
—
—
H'E4
ADDRCH
8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'E5
ADDRCL
8
AD1
AD0
—
—
—
—
—
—
H'E6
ADDRDH
8
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'E7
ADDRDL
8
AD1
AD0
—
—
—
—
—
—
H'E8
ADCSR
8
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
H'E9
ADCR
8
TRGE
—
—
—
—
—
—
—
H'EA
—
—
—
—
—
—
—
—
—
H'EB
—
—
—
—
—
—
—
—
—
H'EC
ABWCR
8
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
H'ED
ASTCR
8
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
H'EE
WCR
8
—
—
—
—
WMS1
WMS0
WC1
WC0
H'EF
WCER
8
WCE7
WCE6
WCE5
WCE4
WCE3
WCE2
WCE1
WCE0
8
—
—
Module Name
Port 2
—
Port 5
A/D
Bus controller
Legend
A/D: A/D converter
(Continued on next page)
480
(Continued from preceding page)
Address Register
(low)
Name
Data
Bus
Width
Bit Names
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
—
—
—
—
H'F0
—
H'F1
MDCR
8
—
—
—
—
—
—
MDS1
MDS0
H'F2
SYSCR
8
SSBY
STS2
STS1
STS0
UE
NMIEG
—
RAME
H'F3
—
—
—
—
—
—
—
—
—
H'F4
ISCR
8
—
—
—
IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
H'F5
IER
8
—
—
—
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
H'F6
ISR
8
—
—
—
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
H'F7
—
—
—
—
—
—
—
—
—
H'F8
IPRA
8
IPRA7
IPRA6
IPRA5
IPRA4
IPRA3
IPRA2
IPRA1
IPRA0
H'F9
IPRB
8
IPRB7
IPRB6
—
—
IPRB3
—
IPRB1
—
H'FA
—
—
—
—
—
—
—
—
—
H'FB
—
—
—
—
—
—
—
—
—
H'FC
—
—
—
—
—
—
—
—
—
H'FD
—
—
—
—
—
—
—
—
—
H'FE
—
—
—
—
—
—
—
—
—
H'FF
—
—
—
—
—
—
—
—
—
481
Module Name
System control
IInterrupt
controller
Interrupt
controller
B.2 Register Descriptions
Register
acronym
Register
name
TSTR Timer Start Register
Address to which
the register is mapped
H'60
Name of on-chip
supporting
module
ITU (all channels)
Bit
numbers
Bit
Initial bit
values
7
6
5
4
3
2
1
0
—
—
—
STR4
STR3
STR2
STR1
STR0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Names of the
bits. Dashes
(—) indicate
reserved bits.
Possible types of access
R
Read only
W
Write only
Counter start 0
0 TCNT0 is halted
1 TCNT0 is counting
R/W Read and write
Counter start 1
0 TCNT1 is halted
1 TCNT1 is counting
Full name
of bit
Counter start 2
0 TCNT2 is halted
1 TCNT2 is counting
Counter start 3
0 TCNT3 is halted
1 TCNT3 is counting
Counter start 4
0 TCNT4 is halted
1 TCNT4 is counting
482
Descriptions
of bit settings
TSTR—Timer Start Register
Bit
H'60
ITU (all channels)
7
6
5
4
3
2
1
0
—
—
—
STR4
STR3
STR2
STR1
STR0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Counter start 0
0 TCNT0 is halted
1 TCNT0 is counting
Counter start 1
0 TCNT1 is halted
1 TCNT1 is counting
Counter start 2
0 TCNT2 is halted
1 TCNT2 is counting
Counter start 3
0 TCNT3 is halted
1 TCNT3 is counting
Counter start 4
0 TCNT4 is halted
1 TCNT4 is counting
483
TSNC—Timer Synchro Register
Bit
H'61
ITU (all channels)
7
6
5
4
3
2
1
0
—
—
—
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Timer sync 0
0 TCNT0 operates independently
1 TCNT0 is synchronized
Timer sync 1
0 TCNT1 operates independently
1 TCNT1 is synchronized
Timer sync 2
0 TCNT2 operates independently
1 TCNT2 is synchronized
Timer sync 3
0 TCNT3 operates independently
1 TCNT3 is synchronized
Timer sync 4
0 TCNT4 operates independently
1 TCNT4 is synchronized
484
TMDR—Timer Mode Register
Bit
H'62
ITU (all channels)
7
6
5
4
3
2
1
0
—
MDF
FDIR
PWM4
PWM3
PWM2
PWM1
PWM0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM mode 0
0 Channel 0 operates normally
1 Channel 0 operates in PWM mode
PWM mode 1
0 Channel 1 operates normally
1 Channel 1 operates in PWM mode
PWM mode 2
0 Channel 2 operates normally
1 Channel 2 operates in PWM mode
PWM mode 3
0 Channel 3 operates normally
1 Channel 3 operates in PWM mode
PWM mode 4
0 Channel 4 operates normally
1 Channel 4 operates in PWM mode
Flag direction
0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
1 OVF is set to 1 in TSR2 when TCNT2 overflows
Phase counting mode flag
0 Channel 2 operates normally
1 Channel 2 operates in phase counting mode
485
TFCR—Timer Function Control Register
Bit
H'63
ITU (all channels)
7
6
5
4
3
2
1
0
—
—
CMD1
CMD0
BFB4
BFA4
BFB3
BFA3
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Buffer mode A3
0 GRA3 operates normally
1 GRA3 is buffered by BRA3
Buffer mode B3
0 GRB3 operates normally
1 GRB3 is buffered by BRB3
Buffer mode A4
0 GRA4 operates normally
1 GRA4 is buffered by BRA4
Buffer mode B4
0 GRB4 operates normally
1 GRB4 is buffered by BRB4
Combination mode 1 and 0
Bit 5 Bit 4
CMD1 CMD0 Operating Mode of Channels 3 and 4
0
0
Channels 3 and 4 operate normally
1
0
1
Channels 3 and 4 operate together in complementary PWM mode
1
Channels 3 and 4 operate together in reset-synchronized PWM mode
486
TCR0—Timer Control Register 0
Bit
H'64
7
6
5
4
3
ITU0
2
1
0
—
CCLR1
CCLR0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKEG1 CKEG0
Timer prescaler 2 to 0
Bit 2
Bit 0
Bit 1
TPSC2 TPSC1 TPSC0
0
0
0
1
0
1
1
0
0
1
1
0
1
1
TCNT Clock Source
Internal clock: ø
Internal clock: ø/2
Internal clock: ø/4
Internal clock: ø/8
External clock A: TCLKA input
External clock B: TCLKB input
External clock C: TCLKC input
External clock D: TCLKD input
Clock edge 1 and 0
Bit 4 Bit 3
CKEG1 CKEG0
0
0
1
1
—
Counted Edges of External Clock
Rising edges counted
Falling edges counted
Both edges counted
Counter clear 1 and 0
Bit 6
Bit 5
CCLR1 CCLR0 TCNT Clear Source
0
0
TCNT is not cleared
1
TCNT is cleared by GRA compare match or input capture
1
0
TCNT is cleared by GRB compare match or input capture
1
Synchronous clear: TCNT is cleared in synchronization
with other synchronized timers
487
TIOR0—Timer I/O Control Register 0
Bit
H'65
ITU0
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
I/O control A2 to A0
Bit 2 Bit 1 Bit 0
IOA2 IOA1 IOA0
0
0
0
1
0
1
1
0
0
1
1
0
1
1
I/O control B2 to B0
Bit 6 Bit 5 Bit 4
IOB2 IOB1 IOB0
0
0
0
1
0
1
1
0
0
1
1
0
1
1
GRA Function
GRA is an output
compare register
GRA is an input
capture register
GRB Function
GRB is an output
compare register
GRB is an input
capture register
No output at compare match
0 output at GRA compare match
1 output at GRA compare match
Output toggles at GRA compare match
GRA captures rising edge of input
GRA captures falling edge of input
GRA captures both edges of input
No output at compare match
0 output at GRB compare match
1 output at GRB compare match
Output toggles at GRB compare match
GRB captures rising edge of input
GRB captures falling edge of input
GRB captures both edges of input
488
TIER0—Timer Interrupt Enable Register 0
Bit
H'66
ITU0
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Input capture/compare match interrupt enable A
0 IMIA interrupt requested by IMFA is disabled
1 IMIA interrupt requested by IMFA is enabled
Input capture/compare match interrupt enable B
0 IMIB interrupt requested by IMFB is disabled
1 IMIB interrupt requested by IMFB is enabled
Overflow interrupt enable
0 OVI interrupt requested by OVF is disabled
1 OVI interrupt requested by OVF is enabled
489
TSR0—Timer Status Register 0
Bit
H'67
ITU0
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Input capture/compare match flag A
0 [Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA
1 [Setting conditions]
TCNT = GRA when GRA functions as a compare
match register.
TCNT value is transferred to GRA by an input capture
signal, when GRA functions as an input capture register.
Input capture/compare match flag B
0 [Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
1 [Setting conditions]
TCNT = GRB when GRB functions as a compare
match register.
TCNT value is transferred to GRB by an input capture
signal, when GRB functions as an input capture register.
Overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000
Note: * Only 0 can be written, to clear the flag.
490
TCNT0 H/L—Timer Counter 0 H/L
H'68, H'69
ITU0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
GRA0 H/L—General Register A0 H/L
H'6A, H'6B
ITU0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register
GRB0 H/L—General Register B0 H/L
H'6C, H'6D
ITU0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register
TCR1—Timer Control Register 1
Bit
H'6E
7
6
5
—
CCLR1
CCLR0
Initial value
1
0
0
0
Read/Write
—
R/W
R/W
R/W
4
3
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
0
R/W
R/W
R/W
R/W
CKEG1 CKEG0
Note: Bit functions are the same as for ITU0.
491
ITU1
TIOR1—Timer I/O Control Register 1
Bit
H'6F
ITU1
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIER1—Timer Interrupt Enable Register 1
Bit
H'70
ITU1
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TSR1—Timer Status Register 1
Bit
H'71
ITU1
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Notes: Bit functions are the same as for ITU0.
* Only 0 can be written, to clear the flag.
TCNT1 H/L—Timer Counter 1 H/L
H'72, H'73
ITU1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
492
GRA1 H/L—General Register A1 H/L
H'74, H'75
ITU1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
GRB1 H/L—General Register B1 H/L
H'76, H'77
ITU1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
TCR2—Timer Control Register 2
Bit
H'78
7
6
5
4
3
ITU2
2
1
0
—
CCLR1
CCLR0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKEG1 CKEG0
Notes: 1. Bit functions are the same as for ITU0.
2. When channel 2 is used in phase counting mode, the counter clock source selection by
bits TPSC2 to TPSC0 is ignored.
493
TIOR2—Timer I/O Control Register 2
Bit
H'79
ITU2
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
494
TIER2—Timer Interrupt Enable Register 2
Bit
H'7A
ITU2
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TSR2—Timer Status Register 2
Bit
H'7B
ITU2
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Bit functions are the
same as for ITU0.
Overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000 or underflowed from
H'0000 to H'FFFF
Note: * Only 0 can be written, to clear the flag.
TCNT2 H/L—Timer Counter 2 H/L
H'7C, H'7D
ITU2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Phase counting mode: up/down counter
Other modes:
up-counter
495
GRA2 H/L—General Register A2 H/L
H'7E, H'7F
ITU2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
GRB2 H/L—General Register B2 H/L
H'80, H'81
ITU2
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU0.
TCR3—Timer Control Register 3
Bit
H'82
ITU3
7
6
5
4
3
2
1
0
—
CCLR1
CCLR0
CKEG1
CLEG0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIOR3—Timer I/O Control Register 3
Bit
H'83
ITU3
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
496
TIER3—Timer Interrupt Enable Register 3
Bit
H'84
ITU3
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TSR3—Timer Status Register 3
Bit
H'85
ITU3
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Bit functions are the
same as for ITU0
Overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000 or underflowed from
H'0000 to H'FFFF
Note: * Only 0 can be written, to clear the flag.
TCNT3 H/L—Timer Counter 3 H/L
H'86, H'87
ITU3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Complementary PWM mode: up/down counter
Other modes:
up-counter
497
GRA3 H/L—General Register A3 H/L
H'88, H'89
ITU3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register (can be buffered)
GRB3 H/L—General Register B3 H/L
H'8A, H'8B
ITU3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Output compare or input capture register (can be buffered)
BRA3 H/L—Buffer Register A3 H/L
Bit
Initial value
Read/Write
H'8C, H'8D
ITU3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Used to buffer GRA
BRB3 H/L—Buffer Register B3 H/L
H'8E, H'8F
ITU3
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Used to buffer GRB
498
TOER—Timer Output Enable Register
Bit
H'90
ITU (all channels)
7
6
5
4
3
2
1
0
—
—
EXB4
EXA4
EB3
EB4
EA4
EA3
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Master enable TIOCA3
0 TIOCA 3 output is disabled regardless of TIOR3, TMDR, and TFCR settings
1 TIOCA 3 is enabled for output according to TIOR3, TMDR, and TFCR settings
Master enable TIOCA4
0 TIOCA 4 output is disabled regardless of TIOR4, TMDR, and TFCR settings
1 TIOCA 4 is enabled for output according to TIOR4, TMDR, and TFCR settings
Master enable TIOCB4
0 TIOCB4 output is disabled regardless of TIOR4 and TFCR settings
1 TIOCB4 is enabled for output according to TIOR4 and TFCR settings
Master enable TIOCB3
0 TIOCB 3 output is disabled regardless of TIOR3 and TFCR settings
1 TIOCB 3 is enabled for output according to TIOR3 and TFCR settings
Master enable TOCXA4
0 TOCXA 4 output is disabled regardless of TFCR settings
1 TOCXA 4 is enabled for output according to TFCR settings
Master enable TOCXB4
0 TOCXB4 output is disabled regardless of TFCR settings
1 TOCXB4 is enabled for output according to TFCR settings
499
TOCR—Timer Output Control Register
Bit
H'91
ITU (all channels)
7
6
5
4
3
2
1
0
—
—
—
XTGD
—
—
OLS4
OLS3
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
R/W
—
—
R/W
R/W
Output level select 3
0 TIOCB 3 , TOCXA 4 , and TOCXB 4 outputs are inverted
1 TIOCB 3 , TOCXA 4 , and TOCXB 4 outputs are not inverted
Output level select 4
0 TIOCA 3 , TIOCA 4, and TIOCB4 outputs are inverted
1 TIOCA 3 , TIOCA 4, and TIOCB4 outputs are not inverted
External trigger disable
0 Input capture A in channel 1 is used as an external trigger signal in
reset-synchronized PWM mode and complementary PWM mode *
1 External triggering is disabled
Note: * When an external trigger occurs, bits 5 to 0 in TOER are cleared to 0, disabling ITU
output.
500
TCR4—Timer Control Register 4
Bit
H'92
7
6
5
4
3
ITU4
2
1
0
—
CCLR1
CCLR0
TPSC2
TPSC1
TPSC0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKEG1 CKEG0
Note: Bit functions are the same as for ITU0.
TIOR4—Timer I/O Control Register 4
Bit
H'93
ITU4
7
6
5
4
3
2
1
0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
Initial value
1
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TIER4—Timer Interrupt Enable Register 4
Bit
H'94
ITU4
7
6
5
4
3
2
1
0
—
—
—
—
—
OVIE
IMIEB
IMIEA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Note: Bit functions are the same as for ITU0.
TSR4—Timer Status Register 4
Bit
H'95
ITU4
7
6
5
4
3
2
1
0
—
—
—
—
—
OVF
IMFB
IMFA
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/(W)*
R/(W)*
R/(W)*
Notes: Bit functions are the same as for ITU0.
* Only 0 can be written, to clear the flag.
501
TCNT4 H/L—Timer Counter 4 H/L
H'96, H'97
ITU4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
GRA4 H/L—General Register A4 H/L
H'98, H'99
ITU4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
GRB4 H/L—General Register B4 H/L
H'9A, H'9B
ITU4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
BRA4 H/L—Buffer Register A4 H/L
Bit
Initial value
Read/Write
H'9C, H'9D
ITU4
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
502
BRB4 H/L—Buffer Register B4 H/L
H'9E, H'9F
ITU4
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bit functions are the same as for ITU3.
TPMR—TPC Output Mode Register
Bit
H'A0
7
6
5
4
3
2
TPC
0
1
—
—
—
—
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
G3NOV G2NOV
G1NOV G0NOV
Group 0 non-overlap
0 Normal TPC output in group 0.
Output values change at compare match A in the selected ITU channel.
1 Non-overlapping TPC output in group 0, controlled by compare match
A and B in the selected ITU channel
Group 1 non-overlap
0 Normal TPC output in group 1.
Output values change at compare match A in the selected ITU channel.
1 Non-overlapping TPC output in group 1, controlled by compare match
A and B in the selected ITU channel
Group 2 non-overlap
0 Normal TPC output in group 2.
Output values change at compare match A in the selected ITU channel.
1 Non-overlapping TPC output in group 2, controlled by compare match
A and B in the selected ITU channel
Group 3 non-overlap
0 Normal TPC output in group 3.
Output values change at compare match A in the selected ITU channel.
1 Non-overlapping TPC output in group 3, controlled by compare match
A and B in the selected ITU channel
503
TPCR—TPC Output Control Register
Bit
7
6
5
H'A1
4
3
2
TPC
1
0
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Group 0 compare match select 1 and 0
Bit 1
Bit 0
G0CMS1 G0CMS0
0
0
1
1
0
1
ITU Channel Selected as Output Trigger
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 0
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 1
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 2
TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 3
Group 1 compare match select 1 and 0
Bit 3
Bit 2
G1CMS1 G1CMS0
0
0
1
1
0
1
ITU Channel Selected as Output Trigger
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 0
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 1
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 2
TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 3
Group 2 compare match select 1 and 0
Bit 5
Bit 4
G2CMS1 G2CMS0
0
0
1
1
0
1
ITU Channel Selected as Output Trigger
TPC output group 2 (TP11 to TP8 ) is triggered by compare match in ITU channel 0
TPC output group 2 (TP11 to TP8 ) is triggered by compare match in ITU channel 1
TPC output group 2 (TP11 to TP8 ) is triggered by compare match in ITU channel 2
TPC output group 2 (TP11 to TP8 ) is triggered by compare match in ITU channel 3
Group 3 compare match select 1 and 0
Bit 7
Bit 6
G3CMS1 G3CMS0
0
0
1
1
0
1
ITU Channel Selected as Output Trigger
TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 0
TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 1
TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 2
TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 3
504
NDERB—Next Data Enable Register B
Bit
7
6
H'A2
5
4
3
2
TPC
1
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
0
NDER8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 15 to 8
Bits 7 to 0
NDER15 to NDER8 Description
0
TPC outputs TP15 to TP8 are disabled
(NDR15 to NDR8 are not transferred to PB 7 to PB 0 )
TPC outputs TP15 to TP8 are enabled
1
(NDR15 to NDR8 are transferred to PB 7 to PB 0 )
NDERA—Next Data Enable Register A
Bit
H'A3
TPC
7
6
5
4
3
2
1
0
NDER7
NDER6
NDER5
NDER4
NDER3
NDER2
NDER1
NDER0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next data enable 7 to 0
Bits 7 to 0
NDER7 to NDER0 Description
0
TPC outputs TP 7 to TP0 are disabled
(NDR7 to NDR0 are not transferred to PA 7 to PA 0)
TPC outputs TP 7 to TP0 are enabled
1
(NDR7 to NDR0 are transferred to PA 7 to PA 0)
505
NDRB—Next Data Register B
•
H'A4/H'A6
TPC
Same output trigger for TPC output groups 2 and 3
Address H'FFA4
Bit
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next output data for
TPC output group 3
Next output data for
TPC output group 2
Address H'FFA6
Bit
•
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
—
Different output triggers for TPC output groups 2 and 3
Address H'FFA4
Bit
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Next output data for
TPC output group 3
Address H'FFA6
Bit
7
6
5
4
3
2
1
0
—
—
—
—
NDR11
NDR10
NDR9
NDR8
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Next output data for
TPC output group 2
506
NDRA—Next Data Register A
•
H'A5/H'A7
TPC
Same output trigger for TPC output groups 0 and 1
Address H'FFA5
Bit
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next output data for
TPC output group 1
Next output data for
TPC output group 0
Address H'FFA7
Bit
•
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
—
Different output triggers for TPC output groups 0 and 1
Address H'FFA5
Bit
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
—
—
—
—
Next output data for
TPC output group 1
Address H'FFA7
Bit
7
6
5
4
3
2
1
0
—
—
—
—
NDR3
NDR2
NDR1
NDR0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Next output data for
TPC output group 0
507
TCSR—Timer Control/Status Register
Bit
H'A8
WDT
7
6
5
4
3
2
1
0
OVF
WT/ IT
TME
—
—
CKS2
CKS1
CKS0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/(W)*
R/W
R/W
—
—
R/W
R/W
R/W
Timer enable
0 Timer disabled
• TCNT is initialized to H'00 and halted
1 Timer enabled
• TCNT is counting
• CPU interrupt requests are enabled
Timer mode select
0 Interval timer: requests interval timer interrupts
1 Watchdog timer: generates a reset signal
Overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT changes from H'FF to H'00
Note: * Only 0 can be written, to clear the flag.
508
Clock select 2 to 0
0
0
0
1
0
1
1
0
0
1
1
0
1
1
ø/2
ø/32
ø/64
ø/128
ø/256
ø/512
ø/2048
ø/4096
TCNT—Timer Counter
Bit
7
H'A9 (read),
H'A8 (write)
6
5
4
3
2
WDT
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
RSTCSR—Reset Control/Status Register
Bit
H'AB (read),
H'AA (write)
WDT
7
6
5
4
3
2
1
0
WRST
RSTOE
—
—
—
—
—
—
Initial value
0
0
1
1
1
1
1
1
Read/Write
R/(W)*
R/W
—
—
—
—
—
—
Reset output enable
0 Reset signal is not output externally
1 Reset signal is output externally
Watchdog timer reset
0 [Clearing condition]
Reset signal input at RES pin, or 0 written by software
1 [Setting condition]
TCNT overflow generates a reset signal
Note: * Only 0 can be written in bit 7, to clear the flag.
509
SMR—Serial Mode Register
H'B0
SCI
7
6
5
7
3
2
1
0
C/ A
CHR
PE
O/ E
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Multiprocessor mode
0 Multiprocessor function disabled
1 Multiprocessor format selected
Stop bit length
0 One stop bit
1 Two stop bits
Parity mode
0 Even parity
1 Odd parity
Parity enable
0 Parity bit is not added or checked
1 Parity bit is added and checked
Character length
0 8-bit data
1 7-bit data
Communication mode
0 Asynchronous mode
1 Synchronous mode
510
Clock select 1 and 0
Bit 1 Bit 0
CKS1 CKS0 Clock Source
0
0
ø clock
1
ø/4 clock
ø/16 clock
0
1
ø/64 clock
1
BRR—Bit Rate Register
H'B1
SCI
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial communication bit rate setting
511
SCR—Serial Control Register
Bit
H'B2
SCI
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock enable 1 and 0
Bit 1 Bit 2
CKE1 CKE2 Clock Selection and Output
0
0
Asynchronous mode Internal clock, SCK pin available for generic input
Synchronous mode Internal clock, SCK pin used for serial clock output
Asynchronous mode Internal clock, SCK pin used for clock output
1
Synchronous mode Internal clock, SCK pin used for serial clock output
Asynchronous mode External clock, SCK pin used for clock input
1
0
Synchronous mode External clock, SCK pin used for serial clock input
Asynchronous mode External clock, SCK pin used for clock input
1
Synchronous mode External clock, SCK pin used for serial clock input
Transmit-end interrupt enable
0 Transmit-end interrupt requests (TEI) are disabled
1 Transmit-end interrupt requests (TEI) are enabled
Multiprocessor interrupt enable
0 Multiprocessor interrupts are disabled (normal receive operation)
1 Multiprocessor interrupts are enabled
Receive enable
0 Transmitting is disabled
1 Transmitting is enabled
Transmit enable
0 Transmitting is disabled
1 Transmitting is enabled
Receive interrupt enable
0 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled
1 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
Transmit interrupt enable
0 Transmit-data-empty interrupt request (TXI) is disabled
1 Transmit-data-empty interrupt request (TXI) is enabled
512
TDR—Transmit Data Register
Bit
7
6
H'B3
5
4
3
2
SCI
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial transmit data
513
SSR—Serial Status Register
Bit
H'B4
SCI
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Multiprocessor bit
0 Multiprocessor bit value in
receive data is 0
1
Transmit end
Multiprocessor bit value in
receive data is 1
Multiprocessor bit transfer
0 Multiprocessor bit value in
transmit data is 0
1
0
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
1
[Setting conditions]
Reset or transition to standby mode.
TE is cleared to 0 in SCR.
TDRE is 1 when last bit of serial character is transmitted.
Multiprocessor bit value in
transmit data is 1
Parity error
Framing error
0
[Clearing conditions]
Reset or transition to standby mode.
Read FER when FER = 1, then write 0
in FER.
1
[Setting condition]
Framing error (stop bit is 0)
0
[Clearing conditions]
Reset or transition to standby mode.
Read PER when PER = 1, then write 0 in
PER.
1
[Setting condition]
Parity error: (parity of receive data does not
match parity setting of O/ E in SMR)
Overrun error
Receive data register full
0
[Clearing conditions]
Reset or transition to standby mode.
Read RDRF when RDRF = 1, then write 0 in
RDRF.
1
[Setting condition]
Serial data is received normally and transferred
from RSR to RDR
Transmit data register empty
0
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
1
[Setting conditions]
Reset or transition to standby mode.
TE is 0 in SCR
Data is transferred from TDR to TSR, enabling new
data to be written in TDR.
Note: * Only 0 can be written, to clear the flag.
514
0
[Clearing conditions]
Reset or transition to standby mode.
Read ORER when ORER = 1, then write 0 in
ORER.
1
[Setting condition]
Overrun error (reception of next serial data
ends when RDRF = 1)
RDR—Receive Data Register
H'B5
SCI
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Serial receive data
P1DDR—Port 1 Data Direction Register
Bit
7
6
H'C0
5
4
3
2
Port 1
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 1 input/output select
0 Generic input
1 Generic output
P2DDR—Port 2 Data Direction Register
Bit
7
6
H'C1
5
4
3
2
Port 2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 2 input/output select
0 Generic input
1 Generic output
515
P1DR—Port 1 Data Register
Bit
H'C2
Port 1
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 1 pins
P2DR—Port 2 Data Register
Bit
H'C3
Port 2
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 2 pins
P3DDR—Port 3 Data Direction Register
Bit
7
6
5
H'C4
4
3
2
Port 3
1
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 3 input/output select
0 Generic input
1 Generic output
516
P3DR—Port 3 Data Register
Bit
H'C6
Port 3
7
6
5
4
3
2
1
0
P37
P36
P35
P34
P33
P32
P31
P30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 3 pins
P5DDR—Port 5 Data Direction Register
Bit
H'C8
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
W
W
W
W
3
2
Port 5
1
0
P5 3 DDR P5 2 DDR P5 1 DDR P5 0 DDR
Port 5 input/output select
0 Generic input
1 Generic output
517
P6DDR—Port 6 Data Direction Register
Bit
H'C9
4
7
6
—
—
Initial value
1
0
0
0
Read/Write
—
W
W
W
5
3
Port 6
2
1
0
—
—
P60DDR
0
0
0
0
W
W
W
W
P65DDR P64DDR P63DDR
Port 6 input/output select
0 Generic input
1 Generic output
P5DR—Port 5 Data Register
Bit
H'CA
Port 5
7
6
5
4
3
2
1
0
—
—
—
—
P5 3
P5 2
P5 1
P5 0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Data for port 5 pins
P6DR—Port 6 Data Register
Bit
H'CB
Port 6
7
6
5
4
3
2
1
0
—
—
P6 5
P6 4
P6 3
—
—
P6 0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 6 pins
518
P8DDR—Port 8 Data Direction Register
Bit
H'CD
3
Port 8
2
1
0
7
6
5
—
—
—
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
W
W
W
W
W
4
P8 4 DDR P8 3 DDR P8 2 DDR P8 1 DDR P8 0 DDR
Port 8 input/output select
0 Generic input
1 Generic output
P7DR—Port 7 Data Register
Bit
H'CE
Port 7
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Data for port 7 pins
Note: * Determined by pins P7 7 to P7 0 .
P8DR—Port 8 Data Register
Bit
H'CF
Port 8
7
6
5
4
3
2
1
0
—
—
—
—
P8 3
P8 2
P8 1
P8 0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Data for port 8 pins
519
P9DDR—Port 9 Data Direction Register
Bit
H'D0
Port 9
7
6
5
4
3
2
1
0
—
—
—
P9 4 DDR
—
P9 2 DDR
—
P9 0 DDR
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
W
W
W
W
W
W
Port 9 input/output select
0 Generic input
1 Generic output
PADDR—Port A Data Direction Register
Bit
7
6
5
H'D1
4
3
Port A
2
1
0
PA7 DDR PA6 DDR PA5 DDR PA4 DDR PA3 DDR PA2 DDR PA1 DDR PA0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port A input/output select
0 Generic input
1 Generic output
P9DR—Port 9 Data Register
Bit
H'D2
Port 9
7
6
5
4
3
2
1
0
—
—
—
P9 4
—
P9 2
—
P9 0
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 9 pins
520
PADR—Port A Data Register
Bit
H'D3
Port A
7
6
5
4
3
2
1
0
PA 7
PA 6
PA 5
PA 4
PA 3
PA 2
PA 1
PA 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port A pins
PBDDR—Port B Data Direction Register
Bit
7
6
H'D4
5
4
3
2
Port B
1
0
PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port B input/output select
0 Generic input
1 Generic output
PBDR—Port B Data Register
Bit
H'D6
Port B
7
6
5
4
3
2
1
0
PB 7
PB 6
PB 5
PB 4
PB 3
PB 2
PB 1
PB 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port B pins
521
P2PCR—Port 2 Input Pull-Up Control Register
Bit
6
7
5
H'D8
4
3
Port 2
2
1
0
P2 7 PCR P2 6 PCR P2 5 PCR P2 4 PCR P2 3 PCR P2 2 PCR P2 1 PCR P2 0 PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 2 input pull-up control 7 to 0
0 Input pull-up transistor is off
1 Input pull-up transistor is on
Note: Valid when the corresponding P2DDR bit is cleared to 0 (designating generic input).
P5PCR—Port 5 Input Pull-Up Control Register
Bit
H'DB
7
6
5
4
Port 5
2
3
1
0
P5 3 PCR P5 2 PCR P5 1 PCR P5 0 PCR
—
—
—
—
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Port 5 input pull-up control 3 to 0
0 Input pull-up transistor is off
1 Input pull-up transistor is on
Note: Valid when the corresponding P5DDR bit is cleared to 0 (designating generic input).
ADDRA H/L—A/D Data Register A H/L
Bit
14
12
H'E0, H'E1
10
8
6
A/D
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
15
13
11
9
7
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADDRAH
ADDRAL
A/D conversion data
10-bit data giving an
A/D conversion result
522
ADDRB H/L—A/D Data Register B H/L
Bit
14
12
H'E2, H'E3
10
8
6
A/D
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
—
—
—
—
—
15
13
11
9
7
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADDRBH
ADDRBL
A/D conversion data
10-bit data giving an
A/D conversion result
ADDRC H/L—A/D Data Register C H/L
Bit
14
12
H'E4, H'E5
10
8
6
A/D
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
15
13
11
9
7
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADDRCH
ADDRCL
A/D conversion data
10-bit data giving an
A/D conversion result
ADDRD H/L—A/D Data Register D H/L
Bit
14
12
H'E6, H'E7
10
8
6
A/D
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
15
13
11
9
7
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADDRDH
ADDRDL
A/D conversion data
10-bit data giving an
A/D conversion result
523
ADCR—A/D Control Register
Bit
H'E9
A/D
7
6
5
4
3
2
1
0
TRGE
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
Trigger enable
0 A/D conversion cannot be externally triggered
1 A/D conversion starts at the fall of the external trigger signal (ADTRG )
524
ADCSR—A/D Control/Status Register
Bit
H'E8
A/D
7
6
5
4
3
2
1
0
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock select
0 Conversion time = 266 states (maximum)
1 Conversion time = 134 states (maximum)
Scan mode
0 Single mode
1 Scan mode
Channel select 2 to 0
Channel
Group
Selection
Selection
CH2
CH1
CH0
0
0
0
1
0
1
1
0
0
1
1
0
1
1
Description
Single Mode Scan Mode
AN 0
AN 0
AN 1
AN 0, AN 1
AN 2
AN 0 to AN 2
AN 3
AN 0 to AN 3
AN 4
AN 4
AN 5
AN 4, AN 5
AN 6
AN 4 to AN 6
AN 7
AN 4 to AN 7
A/D start
0 A/D conversion is stopped
1 Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends
Scan mode: A/D conversion starts and continues, cycling among the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a
transition to standby mode
A/D interrupt enable
0 A/D end interrupt request is disabled
1 A/D end interrupt request is enabled
A/D end flag
0 [Clearing condition]
Read ADF while ADF = 1, then write 0 in ADF
1 [Setting conditions]
Single mode: A/D conversion ends
Scan mode: A/D conversion ends in all selected channels
Note: * Only 0 can be written, to clear flag.
525
ASTCR—Access State Control Register
Bit
H'ED
Bus controller
7
6
5
4
3
2
1
0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Area 7 to 0 access state control
Bits 7 to 0
AST7 to AST0
Number of States in Access Cycle
0
Areas 7 to 0 are two-state access areas
Areas 7 to 0 are three-state access areas
1
WCR—Wait Control Register
Bit
H'EE
Bus controller
7
6
5
4
3
2
1
0
—
—
—
—
WMS1
WMS0
WC1
WC0
Initial value
1
1
1
1
0
0
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
Wait mode select 1 and 0
Bit 3 Bit 2
WMS1 WMS0 Wait Mode
0
0
Programmable wait mode
1
No wait states inserted by
wait-state controller
1
0
1
Wait count 1 and 0
Bit 1 Bit 0
WC1 WC0 Number of Wait States
0
0
No wait states inserted by
wait-state controller
Pin wait mode
Pin auto-wait mode
1
526
1
0
1
1 state inserted
2 states inserted
3 states inserted
WCER—Wait Controller Enable Register
Bit
H'EF
Bus controller
7
6
5
4
3
2
1
0
WCE7
WCE6
WCE5
WCE4
WCE3
WCE2
WCE1
WCE0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Wait state controller enable 7 to 0
0 Wait-state control is disabled (pin wait mode 0)
1 Wait-state control is enabled
MDCR—Mode Control Register
Bit
H'F1
System control
7
6
5
4
3
2
1
0
—
—
—
—
—
—
MDS1
MDS0
Initial value
1
1
0
0
0
1
—*
—*
Read/Write
—
—
—
—
—
—
R
R
Mode select 1 and 0
Bit 1 Bit 0
MD1 MD0 Operating mode
0
—
0
Mode 1
1
Mode 2
0
1
Mode 3
1
Note: * Determined by the state of the mode pins (MD 1 and MD0 ).
527
SYSCR—System Control Register
Bit
H'F2
System control
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
UE
NMIEG
—
RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
RAM enable
0 On-chip RAM is disabled
1 On-chip RAM is enabled
NMI edge select
0 An interrupt is requested at the falling edge of NMI
1 An interrupt is requested at the rising edge of NMI
User bit enable
0 CCR bit 6 (UI) is used as an interrupt mask bit
1 CCR bit 6 (UI) is used as a user bit
Standby timer select 2 to 0
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Standby Timer
0
0
0
Waiting time = 8192 states
1
Waiting time = 16384 states
0
Waiting time = 32768 states
1
1
Waiting time = 65536 states
Waiting time = 131072 states
0
—
1
—
Illegal setting
1
Software standby
0 SLEEP instruction causes transition to sleep mode
1 SLEEP instruction causes transition to software standby mode
528
ISCR—IRQ Sense Control Register
Bit
H'F4
Interrupt controller
7
6
5
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4
3
2
1
0
IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
IRQ 4 to IRQ 0 sense control
0 Interrupts are requested when IRQ 4 to IRQ 0 inputs are low
1 Interrupts are requested by falling-edge input at IRQ 4 to IRQ0
IER—IRQ Enable Register
Bit
H'F5
Interrupt controller
7
6
5
4
3
2
1
0
—
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
IRQ4 to IRQ 0 enable
0 IRQ 4 to IRQ 0 interrupts are disabled
1 IRQ 4 to IRQ 0 interrupts are enabled
529
ISR—IRQ Status Register
H'F6
Interrupt controller
—
—
—
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
IRQ 4 to IRQ 0 flags
Bits 4 to 0
IRQ4F to IRQ0F
0
1
Setting and Clearing Conditions
[Clearing conditions]
Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
IRQnSC = 0, IRQn input is high, and interrupt exception
handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is
carried out.
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
(n = 4 to 0)
Note: * Only 0 can be written, to clear the flag.
530
IPRA—Interrupt Priority Register A
Bit
H'F8
Interrupt controller
7
6
5
4
3
2
1
0
IPRA7
IPRA6
IPRA5
IPRA4
IPRA3
IPRA2
IPRA1
IPRA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Priority level A7 to A0
0 Priority level 0 (low priority)
1 Priority level 1 (high priority)
•
Interrupt sources controlled by each bit
Interrupt
source
Bit 7
IPRA7
Bit 6
IPRA6
Bit 5
IPRA5
Bit 4
IPRA4
Bit 3
IPRA3
Bit 2
IPRA2
Bit 1
IPRA1
Bit 0
IPRA0
IRQ0
IRQ1
IRQ2,
IRQ3
IRQ4
WDT
ITU
channel 0
ITU
channel 1
ITU
channel 2
IPRB—Interrupt Priority Register B
Bit
H'F9
Interrupt controller
7
6
5
4
3
2
1
0
IPRB7
IPRB6
—
—
IPRB3
—
IPRB1
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Priority level B7, B6, B3, and B1
0 Priority level 0 (low priority)
1 Priority level 1 (high priority)
•
Interrupt sources controlled by each bit
Interrupt
source
Bit 7
IPRB7
Bit 6
IPRB6
Bit 5
—
Bit 4
—
Bit 3
IPRB3
Bit 2
—
Bit 1
IPRB1
Bit 0
—
ITU
channel 3
ITU
channel 4
—
—
SCI
channel
—
A/D
converter
—
531
Appendix C I/O Port Block Diagrams
Mode 1/2/3
Reset
R
Q
D
P1nDDR
*
C
WP1D
Mode 2/3
Reset
R
Q
P1n
D
P1nDDR
C
Mode 1
WP1
RP1
WP1D: Write to P1DDR
WP1: Write to port 1
RP1: Read port 1
n = 0 to 7
Set priority
*:
Figure C-1 Port 1 Block Diagram
532
Internal data bus (lower)
Software standby Mode 2/3
Hardware standby
Internal data bus (upper)
C.1 Port 1 Block Diagram
C.2 Port 2 Block Diagram
Q
Software standby Mode 2/3
Hardware standby
Internal data bus (upper)
R
D
P2nPCR
C
RP2P
WP2P
Mode 1/2/3
Reset
R
Q
D
P2nDDR
*
C
WP2D
Reset
Mode 2/3
R
Q
P2n
P2nDR
C
Mode 1
WP2
RP2
WP2P: Write to P2PCR
RP2P: Read P2PCR
WP2D: Write to P2DDR
WP2: Write to port 2
RP2: Read port 2
n = 0 to 7
Set priority
*:
Figure C-2 Port 2 Block Diagram
533
D
Internal data bus (lower)
Reset
Mode 2/3
Write to external
address
R
Q
D
P3nDDR
C
WP3D
Reset
Mode 2/3
R
Q
P3n
P3nDR
C
Mode 1
WP3
RP3
Read external
address
WP3D: Write to P3DDR
WP3: Write to port 3
RP3: Read port 3
n = 0 to 7
Figure C-3 Port 3 Block Diagram
534
D
Internal data bus (lower)
Reset
Hardware
standby
Internal data bus (upper)
C.3 Port 3 Block Diagram
C.4 Port 5 Block Diagram
Software standby Mode 2/3
Hardware standby
Internal data bus (upper)
R
Q
D
P5nPCR
C
RP5P
WP5P
Mode 1 to mode 3 Reset
R
Q
D
P5nDDR
*
C
WP5D
Reset
Mode 2/3
R
Q
P5n
P5nDR
C
Mode 1
WP5
RP5
WP5P: Write to P5PCR
RP5P: Read P5PC4
WP5D: Write to P5DDR
WP5: Write to port 5
RP5: Read port 5
n = 0 to 3
Set priority
*:
Figure C-4 Port 5 Block Diagram
535
D
Internal data bus (lower)
Reset
Reset
R
Q
D
P60DDR
C
Mode 2/3
WP6D
Reset
R
P60
Q
P60DR
Internal data bus
C.5 Port 6 Block Diagram
Bus controller
WAIT
input
enable
D
C
WP6
RP6
Bus controller
WAIT
input
WP6D: Write to P6DDR
WP6: Write to port 6
RP6: Read port 6
Figure C-5 (a) Port 6 Block Diagram (Pin P60)
536
Software standby Mode 2/3
Hardware standby
R
Q
D
P6nDDR
C
WP6D
Reset
Mode 2/3
R
Q
P6n
Internal data bus
Reset
Mode 1
P6nDR
D
C
WP6
AS output
RD output
WR output
RP6
WP6D: Write to P6DDR
WP6: Write to port 6
RP6: Read port 6
n = 5 to 3
Figure C-5 (b) Port 6 Block Diagram (Pins P61 to P63)
537
RP7
P7n
Internal data bus
C.6 Port 7 Block Diagram
A/D converter
Input enable
Analog input
RP7: Read port 7
n = 0 to 7
Figure C-6 (a) Port 7 Block Diagram
538
C.7 Port 8 Block Diagram
R
Q
D
P80DDR
C
WP8D
Reset
Internal data bus
Reset
R
P80
Q
P80DR
D
C
WP8
RP8
Interrupt
controller
IRQ0
input
WP8D: Write to P8DDR
WP8: Write to port 8
RP8: Read port 8
Figure C-7 Port 8 Block Diagram (Pin P80)
539
C.8 Port 9 Block Diagram
R
Q
D
P90DDR
C
WP9D
Internal data bus
Reset
Reset
R
Q
P90
P90DR
D
SCI
C
WP9
Output enable
Serial data
RP9
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Figure C-8 (a) Port 9 Block Diagram (Pin P90)
540
R
Q
D
P92DDR
C
WP9D
Internal data bus
Reset
Reset
SCI
Input
enable
R
Q
P92
P92DR
D
C
WP9
RP9
Serial
data
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
Figure C-8 (b) Port 9 Block Diagram (Pins P92, P93)
541
R
Q
D
P94DDR
C
WP9D
Reset
Internal data bus
Reset
SCI
Clock input
enable
R
Q
P94
P94DR
D
C
WP9
Clock output
enable
Clock output
RP9
Clock input
WP9D: Write to P9DDR
WP9: Write to port 9
RP9: Read port 9
n = 4, 5
Interrupt controller
IRQ4 input
Figure C-8 (c) Port 9 Block Diagram (Pin P94)
542
Internal data bus
C.9 Port A Block Diagram
Reset
R
Q
D
PAnDDR
C
WPAD
Reset
TPC output
enable
R
PAn
Q
PAnDR
TPC
D
Next data
C
WPA
Output trigger
ITU
RPA
Counter
input
clock
WPAD: Write to PADDR
WPA: Write to port A
RPA: Read port A
n = 0, 1
Figure C-9 (a) Port A Block Diagram (Pins PA0, PA1)
543
Internal data bus
Reset
R
Q
D
PAnDDR
C
TPC
WPAD
Reset
TPC output
enable
R
Q
PAn
PAnDR
D
Next data
C
WPA
Output trigger
ITC
Output enable
Compare
match output
RPA
WPAD: Write to PADDR
WPA: Write to port A
RPA: Read port A
n = 2, 3
Figure C-9 (b) Port A Block Diagram (Pins PA2, PA3)
544
Input capture
input
Counter input
clock
Internal data bus
Reset
R
Q
D
PAnDDR
C
WPAD
Reset
TPC output
enable
R
Q
PAn
PAnDR
TPC
D
Next data
C
WPA
Output trigger
ITU
Output enable
Compare
match input
RPA
Input capture
input
WPAD: Write to PADDR
WPA: Write to port A
RPA: Read port A
n = 4 to 7
Figure C-9 (c) Port A Block Diagram (Pins PA4, PA7)
545
Internal data bus
C.10 Port B Block Diagram
Reset
R
Q
D
PBnDDR
C
TPC
WPBD
Reset
TPC output
enable
R
Q
PBn
PBnDR
D
Next data
C
WPB
Output trigger
ITC
Output enable
Compare
match output
RPB
Input capture
input
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
n = 0 to 3
Figure C-10 (a) Port B Block Diagram (Pins PB0 to PB3)
546
Internal data bus
Reset
R
Q
D
PBnDDR
C
TPC
WPBD
Reset
TPC output
enable
R
Q
PBn
PBnDR
D
Next data
C
WPB
Output trigger
ITU
Output enable
Compare
match output
RPB
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
n = 4 to 5
Figure C-10 (b) Port B Block Diagram (Pins PB4, PB5)
547
Internal data bus
Reset
R
Q
D
PB6DDR
C
TPC
WPBD
Reset
TPC output
enable
R
PB6
Q
PB6DR
D
Next data
C
WPB
Output trigger
RPB
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
Figure C-10 (c) Port B Block Diagram (Pin PB6)
548
Internal data bus
Reset
R
Q
D
PB7DDR
C
TPC
WPBD
Reset
TPC output
enable
R
PB7
Q
PB7DR
D
Next data
C
WPB
Output trigger
RPB
A/D converter
ADTRG
input
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
Figure C-10 (d) Port B Block Diagram (Pin PB7)
549
Appendix D Pin States
D.1 Port States in Each Mode
Table D-1 Port States
Hardware Software
Standby
Standby
Mode
Mode
Mode
Reset
State
ø
—
Clock output T
H
Clock output Clock output
P17 to P10
1
T
T
keep
keep
Input port
(DDR = 0)
—
—
T
keep
A7 to A0
(DDR = 1)
P27 to P20
P37 to P30
P53 to P50
2, 3
T
T
keep
keep
I/O port
1
T
T
keep
keep
Input port
(DDR = 0)
—
—
T
keep
A15 to A8
(DDR = 1)
2, 3
T
T
keep
keep
I/O port
1
T
T
T
T
D7 to D0
2, 3
T
T
keep
keep
I/O port
1
T
T
keep
keep
Input port
(DDR = 0)
—
—
T
keep
A19 to A16
(DDR = 1)
2, 3
P60
P65 to P63
Sleep
Mode
Program
Execution
Sleep Mode
Pin
Name
1
T
T
keep
keep
I/O port
WAIT pin
—
—
T
T
WAIT
Generic
I/O pin
T
T
T
T
I/O port
2, 3
T
T
T
T
I/O port
1
H
T
T
H
WR, RD, AS
2, 3
T
T
keep
keep
I/O port
Legend
H:
High
L:
Low
T:
High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
550
Table D-1 Port States (cont)
Mode
Reset
State
Hardware Software
Standby
Standby
Mode
Mode
Sleep
Mode
Program
Execution
Sleep Mode
1 to 3
T
T
T
T
Input port
P83 to P80
1 to 3
T
T
keep
keep
I/O port
P94, P92,
P90
1 to 3
T
T
keep
keep
I/O port
PA7 to PA0
1 to 3
T
T
keep
keep
I/O port
PB7 to PB0
1 to 3
T
T
keep
keep
I/O port
Pin
Name
P77 to P70
Legend
H:
High
L:
Low
T:
High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
551
D.2 Pin States at Reset
Reset in T1 State: Figure D-1 is a timing diagram for the case in which RES goes low during the
T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The
address bus is initialized to the low output level 0.5 state after the low level of RES is sampled.
Sampling of RES takes place at the fall of the system clock (ø).
Access to external address
T2
T1
T3
ø
RES
Internal
reset signal
Address bus
(mode 1)
H'000000
AS (mode 1)
High
RD (read access)
(mode 1)
High
WR (write access)
(mode 1)
High
Data bus
(write access)
(mode 1)
High impedance
I/O port
(modes 1 to 3)
High impedance
Figure D-1 Reset during Memory Access (Reset during T1 State)
552
Reset in T2 State: Figure D-2 is a timing diagram for the case in which RES goes low during the
T2 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The
address bus is initialized to the low output level 0.5 state after the low level of RES is sampled.
The same timing applies when a reset occurs during a wait state (TW).
Access to external address
T2
T1
T3
ø
RES
Internal
reset signal
Address bus
(mode 1)
H'000000
AS (mode 1)
RD (read access)
(mode 1)
WR (write access)
(mode 1)
Data bus
(write access)
(mode 1)
High impedance
High impedance
I/O port
(modes 1 to 3)
Figure D-2 Reset during Memory Access (Reset during T2 State)
553
Reset in T3 State: Figure D-3 is a timing diagram for the case in which RES goes low during the
T3 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The
address bus outputs are held during the T3 state.The same timing applies when a reset occurs in
the T2 state of an access cycle to a two-state-access area.
Access to external address
T2
T1
T3
ø
RES
Internal
reset signal
Address bus
(mode 1)
H'000000
AS (mode 1)
RD (read access)
(mode 1)
WR (write access)
(mode 1)
Data bus
(write access)
(mode 1)
High impedance
I/O port
(modes 1 to 3)
High impedance
Figure D-3 Reset during Memory Access (Reset during T3 State)
554
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10
system clock cycles before the STBY signal goes low, as shown below. RES must remain low
until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
STBY
t1 ≥ 10tcyc
t2 ≥ 0 ns
RES
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, RES does not have to be
driven low as in (1).
Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately
100 ns before STBY goes high.
STBY
t = 100 ns
RES
555
tOSC
Appendix F Package Dimensions
Figure F-1 shows the FP-80A package dimensions of the H8/3032 Series, and figure F-2 shows
the TFP-80C package dimensions.
Unit: mm
17.2 ± 0.3
14.0
41
60
40
0.65
17.2 ± 0.3
61
80
21
1
+0.08
–0.05
2.70
+0.20
–0.16
0.12 M
1.60
0.17
0.30 ± 0.10
3.05 Max
20
0.10
0–5°
0.10
0.80 ± 0.30
Figure F-1 Package Dimensions (FP-80A)
Unit: mm
14.0 ± 0.2
12.0
60
41
40
80
21
0.50
14.0 ± 0.2
61
1
20
1.00
0.10
0.50 ± 0.10
0.17 ± 0.05
1.20 Max
0.10 M
0 – 5°
0.00 Min
0.20 Max
0.20 ± 0.05
Figure F-2 Package Dimensions (TFP-80C)
556