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Hitachi Single-Chip Microcomputer H8/3297 Series H8/3297 HD6473297, HD6433297 H8/3296 HD6433296 H8/3294 HD6473294, HD6433294 H8/3292 HD6433292 Hardware Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 3rd Edition When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit accoording to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support system. Buyers of Hitachi’s products are requested to notify the relevant hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Preface The H8/3297 Series is a series of high-performance microcontrollers with a fast H8/300 CPU core and a set of on-chip supporting functions optimized for embedded control. These include ROM, RAM, three types of timers, a serial communication interface, A/D converter, I/O ports, and other functions needed in control system configurations, so that compact, high-performance systems can be implemented easily. The series includes the H8/3297 with 60-kbyte ROM and 2-kbyte RAM, the H8/3296 with 48-kbyte ROM and 2-kbyte RAM, H8/3294 with 32-kbyte ROM and 1-kbyte RAM, and the H8/3292 with 16-kbyte ROM and 512-byte RAM. The entire H8/3297 Series is available in mask-ROM versions. The H8/3297 and H8/3294 are also available in ZTAT™* (zero turn-around time) versions, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently-changing specifications. This manual describes the hardware of the H8/3297 Series. Refer to the H8/300 Series Programming Manual for a detailed description of the instruction set. Note: * ZTAT™ is a registered trademark of Hitachi, Ltd. Main Revisions and Additions in this Edition Page Item Revisions 4 Table 1-1 Features Table amended 14 Table 1-3 Pin Functions Table amended 37, 38 Notes on Bit Manipulation Instructions Description amended 69 Figure 4-3 Block Diagram of Interrupt Controller Figure amended 71 Figure 4-4 Hardware Interrupt-Handling Sequence Flow amended 90 6.2 Oscillator Circuit (2) 113 Table 7-9 Port 4 Pin Functions 133 Table 7-15 Port 7 Register Port 7 Input Register (P7PIN) Table amended Description amended 184 Bit 7—Overflow Flag (OVF) Bit 6—Timer Mode Select Table amended 202 to 205 Table 11-3 Examples of BRR Settings in Asynchronous Mode (When øP = ø) Description amended Whole table replaced 206 Table 11-4 Examples of BRR Settings in Synchronous Mode (When øP = ø) Description amended Whole table replaced 223 Figure 11-11 Example of SCI Receive Operation Figure amended 228 Figure 11-14 Example of SCI Transmit Operation Figure amended 231 Figure 11-16 Example of SCI Receive Operation Figure amended 254 13.2.2 Single-Chip Mode (Mode 3) Note added 269 15.1.1 System Control Register (SYSCR) Note Deleted 300 to 302 Table A-1 Instruction Set Table amended 317 B.1 Addresses Table amended 340 TCR—Timer Control Register Table amended 355 Figure C-4 (a) Port 4 Block Diagram (Pin P40) Figure amended 363 Figure C-6 (a) Port 6 Block Diagram (Pin P60) Figure amended 364 Figure C-6 (b) Port 6 Block Diagram (Pin P61) Figure amended 365 Figure C-6 (c) Port 6 Block Diagram (Pin P62) Figure amended 366 Figure C-6 (d) Port 6 Block Diagram (Pins P63 and P65) Figure amended 367 Figure C-6 (e) Port 6 Block Diagram (Pin P64) Figure amended 368 Figure C-6 (f) Port 6 Block Diagram (Pin P66) Figure amended 369 Figure C-6 (g) Port 6 Block Diagram (Pin P67) Figure amended ➁ Description amended Table amended Contents Section 1 1.1 1.2 1.3 Overview...................................................................................................... Overview ........................................................................................................................ Block Diagram................................................................................................................ Pin Assignments and Functions...................................................................................... 1.3.1 Pin Arrangement............................................................................................. 1.3.2 Pin Functions .................................................................................................. Section 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 CPU ............................................................................................................... Overview ........................................................................................................................ 2.1.1 Features........................................................................................................... 2.1.2 Address Space................................................................................................. 2.1.3 Register Configuration.................................................................................... Register Descriptions...................................................................................................... 2.2.1 General Registers............................................................................................ 2.2.2 Control Registers ............................................................................................ 2.2.3 Initial Register Values .................................................................................... Data Formats................................................................................................................... 2.3.1 Data Formats in General Registers ................................................................. 2.3.2 Memory Data Formats.................................................................................... Addressing Modes .......................................................................................................... 2.4.1 Addressing Mode............................................................................................ 2.4.2 Calculation of Effective Address.................................................................... Instruction Set................................................................................................................. 2.5.1 Data Transfer Instructions .............................................................................. 2.5.2 Arithmetic Operations .................................................................................... 2.5.3 Logic Operations ............................................................................................ 2.5.4 Shift Operations .............................................................................................. 2.5.5 Bit Manipulations ........................................................................................... 2.5.6 Branching Instructions.................................................................................... 2.5.7 System Control Instructions ........................................................................... 2.5.8 Block Data Transfer Instruction ..................................................................... CPU States ...................................................................................................................... 2.6.1 Overview......................................................................................................... 2.6.2 Program Execution State ................................................................................ 2.6.3 Exception-Handling State............................................................................... 2.6.4 Power-Down State .......................................................................................... Access Timing and Bus Cycle........................................................................................ 2.7.1 Access to On-Chip Memory (RAM and ROM) ............................................. 2.7.2 Access to On-Chip Register Field and External Devices ............................... 1 1 5 6 6 9 17 17 17 18 18 19 19 19 20 21 22 23 24 24 26 30 31 33 34 34 36 40 42 43 45 45 46 46 46 47 47 49 Section 3 3.1 3.2 3.3 3.4 MCU Operating Modes and Address Space ..................................... Overview ........................................................................................................................ 3.1.1 Mode Selection ............................................................................................... 3.1.2 Mode and System Control Registers ............................................................. System Control Register (SYSCR)................................................................................. Mode Control Register (MDCR) .................................................................................... Address Space Map in Each Operating Mode................................................................ Section 4 4.1 4.2 4.3 4.4 Exception Handling .................................................................................. Overview ........................................................................................................................ Reset ........................................................................................................................ 4.2.1 Overview......................................................................................................... 4.2.2 Reset Sequence ............................................................................................... 4.2.3 Disabling of Interrupts after Reset.................................................................. Interrupts ........................................................................................................................ 4.3.1 Overview......................................................................................................... 4.3.2 Interrupt-Related Registers............................................................................. 4.3.3 External Interrupts .......................................................................................... 4.3.4 Internal Interrupts ........................................................................................... 4.3.5 Interrupt Handling .......................................................................................... 4.3.6 Interrupt Response Time................................................................................. 4.3.7 Precaution ....................................................................................................... Note on Stack Handling.................................................................................................. Section 5 5.1 5.2 5.3 Wait-State Controller ............................................................................... Overview ........................................................................................................................ 5.1.1 Features........................................................................................................... 5.1.2 Block Diagram................................................................................................ 5.1.3 Input/Output Pins............................................................................................ 5.1.4 Register Configuration.................................................................................... Register Description ....................................................................................................... 5.2.1 Wait-State Control Register (WSCR)............................................................. Wait Modes..................................................................................................................... Section 6 6.1 6.2 6.3 6.4 53 53 53 54 54 56 57 61 61 61 61 61 64 64 64 66 68 68 69 74 75 76 77 77 77 77 78 78 78 78 80 Clock Pulse Generator ............................................................................. 83 Overview ........................................................................................................................ 6.1.1 Block Diagram................................................................................................ 6.1.2 Wait-State Control Register (WSCR)............................................................. Oscillator Circuit ............................................................................................................ Duty Adjustment Circuit................................................................................................. Prescaler ........................................................................................................................ 83 83 84 85 90 90 Section 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 I/O Ports ....................................................................................................... 91 Overview ........................................................................................................................ 91 Port 1 ........................................................................................................................ 93 7.2.1 Overview......................................................................................................... 93 7.2.2 Register Configuration and Descriptions........................................................ 94 7.2.3 Pin Functions in Each Mode........................................................................... 96 7.2.4 Input Pull-Up Transistors ............................................................................... 98 Port 2 ........................................................................................................................ 99 7.3.1 Overview......................................................................................................... 99 7.3.2 Register Configuration and Descriptions........................................................ 100 7.3.3 Pin Functions in Each Mode........................................................................... 102 7.3.4 Input Pull-Up Transistors ............................................................................... 105 Port 3 ........................................................................................................................ 106 7.4.1 Overview......................................................................................................... 106 7.4.2 Register Configuration and Descriptions........................................................ 107 7.4.3 Pin Functions in Each Mode........................................................................... 109 7.4.4 Input Pull-Up Transistors ............................................................................... 110 Port 4 ........................................................................................................................ 111 7.5.1 Overview......................................................................................................... 111 7.5.2 Register Configuration and Descriptions........................................................ 112 7.5.3 Pin Functions .................................................................................................. 113 Port 5 ........................................................................................................................ 115 7.6.1 Overview......................................................................................................... 115 7.6.2 Register Configuration and Descriptions........................................................ 115 7.6.3 Pin Functions .................................................................................................. 117 Port 6 ........................................................................................................................ 118 7.7.1 Overview......................................................................................................... 118 7.7.2 Register Configuration and Descriptions........................................................ 119 7.7.3 Pin Functions .................................................................................................. 121 Port 7 ........................................................................................................................ 123 7.8.1 Overview......................................................................................................... 123 7.8.2 Register Configuration and Descriptions........................................................ 124 Section 8 8.1 8.2 16-Bit Free-Running Timer ................................................................... 125 Overview ........................................................................................................................ 125 8.1.1 Features........................................................................................................... 125 8.1.2 Block Diagram................................................................................................ 126 8.1.3 Input and Output Pins ..................................................................................... 127 8.1.4 Register Configuration.................................................................................... 127 Register Descriptions...................................................................................................... 128 8.2.1 Free-Running Counter (FRC) ......................................................................... 128 8.2.2 Output Compare Registers A and B (OCRA and OCRB).............................. 129 8.2.3 Input Capture Registers A to D (ICRA to ICRD)........................................... 129 8.3 8.4 8.5 8.6 8.7 8.2.4 Timer Interrupt Enable Register (TIER)......................................................... 131 8.2.5 Timer Control/Status Register (TCSR) .......................................................... 133 8.2.6 Timer Control Register (TCR)........................................................................ 135 8.2.7 Timer Output Compare Control Register (TOCR)......................................... 137 CPU Interface ................................................................................................................. 139 Operation ........................................................................................................................ 142 8.4.1 FRC Incrementation Timing........................................................................... 142 8.4.2 Output Compare Timing................................................................................. 144 8.4.3 FRC Clear Timing .......................................................................................... 145 8.4.4 Input Capture Timing ..................................................................................... 146 8.4.5 Timing of Input Capture Flag (ICF) Setting................................................... 149 8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB) .................... 150 8.4.7 Setting of FRC Overflow Flag (OVF) ............................................................ 151 Interrupts ........................................................................................................................ 151 Sample Application ........................................................................................................ 152 Usage Notes .................................................................................................................... 153 Section 9 9.1 9.2 9.3 9.4 9.5 9.6 8-Bit Timers ................................................................................................ 159 Overview ........................................................................................................................ 159 9.1.1 Features........................................................................................................... 159 9.1.2 Block Diagram................................................................................................ 160 9.1.3 Input and Output Pins ..................................................................................... 161 9.1.4 Register Configuration.................................................................................... 161 Register Descriptions...................................................................................................... 162 9.2.1 Timer Counter (TCNT)................................................................................... 162 9.2.2 Time Constant Registers A and B (TCORA and TCORB) ............................ 162 9.2.3 Timer Control Register (TCR)........................................................................ 163 9.2.4 Timer Control/Status Register (TCSR) .......................................................... 166 9.2.5 Serial/Timer Control Register (STCR)........................................................... 168 Operation ........................................................................................................................ 169 9.3.1 TCNT Incrementation Timing........................................................................ 169 9.3.2 Compare Match Timing.................................................................................. 171 9.3.3 External Reset of TCNT ................................................................................. 173 9.3.4 Setting of TCSR Overflow Flag (OVF).......................................................... 173 Interrupts ........................................................................................................................ 174 Sample Application ........................................................................................................ 174 Usage Notes .................................................................................................................... 175 9.6.1 Contention between TCNT Write and Clear ................................................. 175 9.6.2 Contention between TCNT Write and Increment .......................................... 176 9.6.3 Contention between TCOR Write and Compare-Match ............................... 177 9.6.4 Contention between Compare-Match A and Compare-Match B ................... 178 9.6.5 Incrementation Caused by Changing of Internal Clock Source ..................... 178 Section 10 10.1 10.2 10.3 10.4 Watchdog Timer ........................................................................................ 181 Overview ........................................................................................................................ 181 10.1.1 Features........................................................................................................... 181 10.1.2 Block Diagram................................................................................................ 182 10.1.3 Register Configuration.................................................................................... 182 Register Descriptions...................................................................................................... 183 10.2.1 Timer Counter (TCNT)................................................................................... 183 10.2.2 Timer Control/Status Register (TCSR) .......................................................... 183 10.2.3 Register Access............................................................................................... 185 Operation ........................................................................................................................ 186 10.3.1 Watchdog Timer Mode................................................................................... 186 10.3.2 Interval Timer Mode....................................................................................... 187 10.3.3 Setting the Overflow Flag............................................................................... 187 Usage Notes .................................................................................................................... 188 10.4.1 Contention between TCNT Write and Increment........................................... 188 10.4.2 Changing the Clock Select Bits (CKS2 to CKS0).......................................... 188 10.4.3 Recovery from Software Standby Mode ........................................................ 188 Section 11 11.1 11.2 11.3 11.4 11.5 Overview ........................................................................................................................ 189 11.1.1 Features........................................................................................................... 189 11.1.2 Block Diagram................................................................................................ 190 11.1.3 Input and Output Pins ..................................................................................... 191 11.1.4 Register Configuration.................................................................................... 191 Register Descriptions...................................................................................................... 192 11.2.1 Receive Shift Register (RSR) ......................................................................... 192 11.2.2 Receive Data Register (RDR)......................................................................... 192 11.2.3 Transmit Shift Register (TSR)........................................................................ 192 11.2.4 Transmit Data Register (TDR) ....................................................................... 193 11.2.5 Serial Mode Register (SMR) .......................................................................... 193 11.2.6 Serial Control Register (SCR) ........................................................................ 196 11.2.7 Serial Status Register (SSR) ........................................................................... 199 11.2.8 Bit Rate Register (BRR) ................................................................................. 202 11.2.9 Serial/Timer Control Register (STCR)........................................................... 207 Operation ........................................................................................................................ 208 11.3.1 Overview......................................................................................................... 208 11.3.2 Asynchronous Mode....................................................................................... 210 11.3.3 Synchronous Mode ......................................................................................... 224 Interrupts ........................................................................................................................ 233 Usage Notes .................................................................................................................... 233 Section 12 12.1 Serial Communication Interface ........................................................... 189 A/D Converter ............................................................................................ 237 Overview ........................................................................................................................ 237 12.2 12.3 12.4 12.5 12.6 12.1.1 Features........................................................................................................... 237 12.1.2 Block Diagram................................................................................................ 238 12.1.3 Input Pins ........................................................................................................ 239 12.1.4 Register Configuration.................................................................................... 240 Register Descriptions...................................................................................................... 241 12.2.1 A/D Data Registers A to D (ADDRA to ADDRD)........................................ 241 12.2.2 A/D Control/Status Register (ADCSR) .......................................................... 242 12.2.3 A/D Control Register (ADCR) ....................................................................... 244 CPU Interface ................................................................................................................. 245 Operation ........................................................................................................................ 246 12.4.1 Single Mode (SCAN = 0) ............................................................................... 246 12.4.2 Scan Mode (SCAN = 1).................................................................................. 248 12.4.3 Input Sampling and A/D Conversion Time .................................................... 250 12.4.4 External Trigger Input Timing........................................................................ 251 Interrupts ........................................................................................................................ 251 Usage Notes .................................................................................................................... 252 Section 13 13.1 13.2 RAM ............................................................................................................. 253 Overview ........................................................................................................................ 253 13.1.1 Block Diagram................................................................................................ 253 13.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR) ................. 254 Operation ........................................................................................................................ 254 13.2.1 Expanded Modes (Modes 1 and 2) ................................................................. 254 13.2.2 Single-Chip Mode (Mode 3)........................................................................... 254 Section 14 14.1 14.2 14.3 14.4 ROM.............................................................................................................. 255 Overview ........................................................................................................................ 255 14.1.1 Block Diagram................................................................................................ 256 PROM Mode................................................................................................................... 257 14.2.1 PROM Mode Setup......................................................................................... 257 14.2.2 Socket Adapter Pin Assignments and Memory Map...................................... 257 PROM Programming ...................................................................................................... 260 14.3.1 Programming and Verifying ........................................................................... 260 14.3.2 Notes on Programming ................................................................................... 264 14.3.3 Reliability of Programmed Data..................................................................... 264 14.3.4 Erasing of Data ............................................................................................... 265 Handling of Windowed Packages................................................................................... 266 Section 15 15.1 15.2 Power-Down State .................................................................................... 267 Overview ........................................................................................................................ 267 15.1.1 System Control Register (SYSCR)................................................................. 268 Sleep Mode ..................................................................................................................... 269 15.2.1 Transition to Sleep Mode................................................................................ 269 15.3 15.4 15.2.2 Exit from Sleep Mode..................................................................................... 269 Software Standby Mode ................................................................................................. 270 15.3.1 Transition to Software Standby Mode............................................................ 270 15.3.2 Exit from Software Standby Mode ................................................................. 270 15.3.3 Clock Settling Time for Exit from Software Standby Mode.......................... 271 15.3.4 Sample Application of Software Standby Mode ............................................ 272 15.3.5 Usage Note...................................................................................................... 272 Hardware Standby Mode ................................................................................................ 273 15.4.1 Transition to Hardware Standby Mode........................................................... 273 15.4.2 Recovery from Hardware Standby Mode ....................................................... 273 15.4.3 Timing Relationships...................................................................................... 274 Section 16 16.1 16.2 16.3 Electrical Specifications.......................................................................... 275 Absolute Maximum Ratings ........................................................................................... 275 Electrical Characteristics ................................................................................................ 275 16.2.1 DC Characteristics .......................................................................................... 275 16.2.2 AC Characteristics .......................................................................................... 285 16.2.3 A/D Converter Characteristics........................................................................ 289 MCU Operational Timing............................................................................................... 290 16.3.1 Bus Timing ..................................................................................................... 290 16.3.2 Control Signal Timing .................................................................................... 292 16.3.3 16-Bit Free-Running Timer Timing ............................................................... 294 16.3.4 8-Bit Timer Timing......................................................................................... 295 16.3.5 Serial Communication Interface Timing ........................................................ 296 16.3.6 I/O Port Timing............................................................................................... 297 16.3.7 External Clock Output Timing ....................................................................... 297 Appendix A CPU Instruction Set.................................................................................. 299 A.1 A.2 A.3 Instruction Set List.......................................................................................................... 299 Operation Code Map....................................................................................................... 307 Number of States Required for Execution...................................................................... 309 Appendix B Register Field ............................................................................................. 315 B.1 B.2 Register Addresses and Bit Names................................................................................. 315 Register Descriptions...................................................................................................... 320 Appendix C I/O Port Block Diagrams ........................................................................ 352 C.1 C.2 C.3 C.4 C.5 C.6 C.7 Port 1 Block Diagram ..................................................................................................... Port 2 Block Diagram ..................................................................................................... Port 3 Block Diagram ..................................................................................................... Port 4 Block Diagrams.................................................................................................... Port 5 Block Diagrams.................................................................................................... Port 6 Block Diagrams.................................................................................................... Port 7 Block Diagrams.................................................................................................... 352 353 354 355 360 363 370 Appendix D Pin States ..................................................................................................... 371 D.1 Port States in Each Mode................................................................................................ 371 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode.............................................................. 373 Appendix F Product Code Lineup ............................................................................... 374 Appendix G Package Dimensions ................................................................................ 376 Section 1 Overview 1.1 Overview The H8/3297 Series of single-chip microcomputers features an H8/300 CPU core and a complement of on-chip supporting modules implementing a variety of system functions. The H8/300 CPU is a high-speed processor with an architecture featuring powerful bit-manipulation instructions, ideally suited for realtime control applications. The on-chip supporting modules implement peripheral functions needed in system configurations. These include ROM, RAM, three types of timers (a 16-bit free-running timer, 8-bit timers, and a watchdog timer), a serial communication interface (SCI), an A/D converter, and I/O ports. The H8/3297 Series can operate in single-chip mode or in two expanded modes, depending on the requirements of the application. The entire H8/3297 Series is available with mask ROM. The H8/3297 and H8/3294 are also available in ZTAT™ versions* that can be programmed at the user site. Note: * ZTAT™ (zero turn-around time) is a trademark of Hitachi, Ltd. Table 1-1 lists the features of the H8/3297 Series. 1 Table 1-1 Features Item Specification CPU Two-way general register configuration • Eight 16-bit registers, or • Sixteen 8-bit registers High-speed operation • Maximum clock rate (ø clock): 16 MHz at 5 V, 12 MHz at 4 V or 10 MHz at 3 V • 8- or 16-bit register-register add/subtract: 125 ns (16 MHz), 167 ns (12 MHz), 200 ns (10 MHz) • 8 × 8-bit multiply: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) • 16 ÷ 8-bit divide: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) Streamlined, concise instruction set • Instruction length: 2 or 4 bytes • Register-register arithmetic and logic operations • MOV instruction for data transfer between registers and memory Instruction set features • Multiply instruction (8 bits × 8 bits) • Divide instruction (16 bits ÷ 8 bits) • Bit-accumulator instructions • Register-indirect specification of bit positions Memory • • • • H8/3297: 60k-byte ROM; 2k-byte RAM H8/3296: 48k-byte ROM; 2k-byte RAM H8/3294: 32k-byte ROM; 1k-byte RAM H8/3292: 16k-byte ROM; 512-byte RAM 16-bit freerunning timer (1 channel) • One 16-bit free-running counter (can also count external events) • Two output-compare lines • Four input capture lines (can be buffered) 8-bit timer (2 channels) Each channel has • One 8-bit up-counter (can also count external events) • Two time constant registers Watchdog timer (WDT) (1 channel) • Overflow can generate a reset or NMI interrupt • Also usable as interval timer Serial communication interface (SCI) (1 channel) • Asynchronous or synchronous mode (selectable) • Full duplex: can transmit and receive simultaneously • On-chip baud rate generator A/D converter • • • • I/O ports • 43 input/output lines (16 of which can drive LEDs) • 8 input-only lines 10-bit resolution Eight channels: single or scan mode (selectable) Start of A/D conversion can be externally triggered Sample-and-hold function 2 Table 1-1 Features (cont) Item Specification Interrupts • Four external interrupt lines: NMI, IRQ0 to IRQ2 • 19 on-chip interrupt sources Wait control • Three selectable wait modes Operating modes • Expanded mode with on-chip ROM disabled (mode 1) • Expanded mode with on-chip ROM enabled (mode 2) • Single-chip mode (mode 3) Power-down modes • Sleep mode • Software standby mode • Hardware standby mode Other features • On-chip oscillator 3 Table 1-1 Features (cont) Item Series lineup Specification Part Number Product Name H8/3297 ZTAT H8/3297 H8/3296 H8/3294 ZTAT H8/3294 H8/3292 5-V Version (16 MHz) 4-V Version (12 MHz) 3-V Version (10 MHz) Package ROM HD6473297C16 HD6473297C16 64-pin windowed shrink DIP (DC-64S) PROM HD6473297P16 HD6473297P16 64-pin shrink DIP (DP-64S) HD6473297F16 HD6473297F16 64-pin QFP (FP-64A) HD6473297TF16 HD6473297TF16 80-pin TQFP (TFP-80C) HD6433297P16 HD6433297P12 HD6433297VP10 64-pin shrink DIP (DP-64S) HD6433297F16 HD6433297F12 HD6433297VF10 64-pin QFP (FP-64A) HD6433297TF16 HD6433297TF12 HD6433297VTF10 80-pin TQFP (TFP-80C) HD6433296P16 HD6433296P12 HD6433296VP10 64-pin shrink DIP (DP-64S) HD6433296F16 HD6433296F12 HD6433296VF10 64-pin QFP (FP-64A) HD6433296TF16 HD6433296TF12 HD6433296VTF10 80-pin TQFP (TFP-80C) HD6473294P16 HD6473294P16 64-pin shrink DIP (DP-64S) HD6473294F16 HD6473294F16 64-pin QFP (FP-64A) HD6473294TF16 HD6473294TF16 80-pin TQFP (TFP-80C) HD6433294P16 HD6433294P12 HD6433294VP10 64-pin shrink DIP (DP-64S) HD6433294F16 HD6433294F12 HD6433294VF10 64-pin QFP (FP-64A) HD6433294TF16 HD6433294TF12 HD6433294VTF10 80-pin TQFP (TFP-80C) HD6433292P16 HD6433292P12 HD6433292VP10 64-pin shrink DIP (DP-64S) HD6433292F16 HD6433292F12 HD6433292VF10 64-pin QFP (FP-64A) HD6433292TF16 HD6433292TF12 HD6433292VTF10 80-pin TQFP (TFP-80C) 4 Mask ROM Mask ROM PROM Mask ROM Mask ROM 1.2 Block Diagram RAM Port 4 ROM Port 1 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 P4 0 /IRQ 2/ADTRG P4 1 /IRQ 1 P4 2 /IRQ 0 P4 3 /RD P4 4 /WR P4 5 /AS P4 6 /Ø P4 7 /WAIT Port 3 Data bus (Low) Address bus RES STBY NMI MD0 MD1 VCC VSS CPU H8/300 Data bus (High) XTAL EXTAL Clock pulse generator Figure 1-1 shows a block diagram of the H8/3297 Series. P30/D0 P31/D1 P32/D2 P33/D3 P34/D4 P35/D5 P36/D6 P37/D7 Watchdog timer Serial communication interface 16-bit freerunning timer Figure 1-1 Block Diagram 5 P5 2 /SCK Port 5 P5 0 /TxD P70 P71 P72 P73 P74 P75 P76 P77 /AN0 /AN1 /AN2 /AN3 /AN4 /AN5 /AN6 /AN7 Port 7 P60 /FTCI/TMCI0 P61 /FTOA P6 2 /FTIA P63 /FTIB/TMRI0 P64 /FTIC/TMO0 P65 /FTID/TMCI1 P66 /FTOB/TMRI1 P67 /TMO1 Port 6 10-bit A/D converter (8 channels) P5 1 /RxD 8-bit timer (2 channels) AVCC AVSS Port 2 P20 /A8 P21 /A9 P22 /A 10 P23 /A 11 P24 /A 12 P25 /A 13 P26 /A 14 P27 /A 15 1.3 Pin Assignments and Functions 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the DC-64S and DP-64S packages. Figure 1-3 shows the pin arrangement of the FP-64A package. Figure 1-4 shows the pin arrangement of the TFP-80C package. P40/ADTRG/IRQ2 1 64 P37/D7 P41/IRQ1 2 63 P36/D6 P42/IRQ0 3 62 P35/D5 P43/RD 4 61 P34/D4 P44/WR 5 60 P33/D3 P45/AS 6 59 P32/D2 P46/Ø 7 58 P31/D1 P47/WAIT 8 57 P30/D0 P50/TxD 9 56 P10/A0 P51/RxD 10 55 P11/A1 P52/SCK 11 54 P12/A2 RES 12 53 P13/A3 NMI 13 52 P14/A4 VCC 14 51 P15/A5 STBY 15 50 P16/A6 VSS 16 49 P17/A7 XTAL 17 48 VSS EXTAL 18 47 P20/A8 MD1 19 46 P21/A9 MD0 20 45 P22/A10 AV SS 21 44 P23/A11 P70/AN0 22 43 P24/A12 P71/AN1 23 42 P25/A13 P72/AN2 24 41 P26/A14 P73/AN3 25 40 P27/A15 P74/AN4 26 39 VCC P75/AN5 27 38 P67/TMO1 P76/AN6 28 37 P66/FTOB/TMRI1 P77/AN7 29 36 P65/FTID/TMCI1 AV CC 30 35 P64/FTIC/TMO0 P60/FTCI/TMCI0 31 34 P63/FTIB/TMRI0 P61/FTOA 32 33 P62/FTIA Figure 1-2 Pin Arrangement (DC-64S and DP-64S, Top view) 6 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 VSS P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/D0 49 32 P27/A15 P31/D1 50 31 VCC P32/D2 51 30 P67/TMO1 P33/D3 52 29 P66/FTOB/TMRI1 P34/D4 53 28 P65/FTID/TMCI1 P35/D5 54 27 P64/FTIC/TMO0 P36/D6 55 26 P63/FTIB/TMRI0 13 14 15 16 AV SS P71/AN1 P72/AN2 12 P70/AN0 11 P73/AN3 MD1 P74/AN4 17 MD0 18 64 10 63 9 P46/Ø P47/WAIT XTAL P75/AN5 EXTAL P76/AN6 19 8 20 62 7 61 P45/AS VSS P44/WR STBY P77/AN7 6 AVCC 21 5 22 60 VCC 59 P43/RD NMI P42/IRQ0 4 P60/FTCI/TMCI0 3 23 RES 58 P52/SCK 24 P41/IRQ1 2 P62/FTIA P61/FTOA P51/RxD 25 57 1 56 P50/TxD P37/D7 P40/ADTRG/IRQ2 Figure 1-3 Pin Arrangement (FP-64A, Top view) 7 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 VSS P15/A5 P16/A6 P17/A7 VSS VSS VSS P20/A8 P21/A9 P22/A10 VSS P23/A11 P24/A12 P25/A13 P26/A14 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 27 AVCC 75 26 P77/AN7 VSS 76 25 P76/AN6 P44/WR 77 24 VSS P45/AS 78 23 P75/AN5 P46/Ø 79 22 P74/AN4 P47/WAIT 80 21 P73/AN3 P50/TxD 20 74 P43/RD P72/AN2 P42/IRQ0 19 P60/FTCI/TMCI0 P71/AN1 VSS 28 18 29 73 P70/AN0 72 VSS 17 P41/IRQ1 AVSS P61/FTOA 16 30 MD0 71 15 VSS P40/ADTRG/IRQ2 14 31 VSS 70 MD1 P62/FTIA VSS 13 32 12 69 VSS P63/FTIB/TMRI0 P37/D7 EXTAL 33 11 68 XTAL VSS P36/D6 10 34 VSS 67 9 P64/FTIC/TMO0 P35/D5 VSS 35 8 66 VSS P65/FTID/TMCI1 VSS 7 36 STBY 65 6 P66/FTOB/TMRI1 P34/D4 VCC 37 5 64 NMI P67/TMO1 P33/D3 4 38 RES 63 3 VCC P32/D2 P52/SCK P27/A15 39 2 40 62 1 61 P31/D1 P51/RxD P30/D0 Figure 1-4 Pin Arrangement (TFP-80C, Top view) 8 1.3.2 Pin Functions (1) Pin Assignments in Each Operating Mode: Table 1-2 lists the assignments of the pins of the DC-64S, DP-64S, FP-64A, and TFP-80C packages in each operating mode. Table 1-2 Pin Assignments in Each Operating Mode Pin No. DC-64S Expanded modes Mode 2 Single-chip mode PROM DP-64S FP-64A TFP-80C Mode 1 1 57 71 P40/IRQ2/ADTRG P40/IRQ2/ADTRG P40/IRQ2/ADTRG EA16 2 58 72 P41/IRQ1 P41/IRQ1 P41/IRQ1 EA15 — — 73 VSS VSS VSS VSS 3 59 74 P42/IRQ0 P42/IRQ0 P42/IRQ0 PGM 4 60 75 RD RD P43 NC — — 76 VSS VSS VSS VSS 5 61 77 WR WR P44 NC 6 62 78 AS AS P45 NC 7 63 79 Ø Ø P46/Ø NC 8 64 80 P47/WAIT P47/WAIT P47 NC 9 1 1 P50/TxD P50/TxD P50/TxD NC 10 2 2 P51/RxD P51/RxD P51/RxD NC 11 3 3 P52/SCK P52/SCK P52/SCK NC 12 4 4 RES RES RES VPP 13 5 5 NMI NMI NMI EA9 14 6 6 VCC VCC VCC VCC 15 7 7 STBY STBY STBY VSS 16 8 8 VSS VSS VSS VSS — — 9 VSS VSS VSS VSS — — 10 VSS VSS VSS VSS 17 9 11 XTAL XTAL XTAL NC — — 12 VSS VSS VSS VSS 18 10 13 EXTAL EXTAL EXTAL NC 19 11 14 MD1 MD1 MD1 VSS Note: Pins marked NC should be left unconnected. For details on PROM mode, refer to 14.2, PROM Mode. 9 Mode 3 mode Table 1-2 Pin Assignments in Each Operating Mode (cont) Pin No. DC-64S Expanded modes Single-chip mode PROM DP-64S FP-64A TFP-80C Mode 1 Mode 2 Mode 3 mode — — 15 VSS VSS VSS VSS 20 12 16 MD0 MD0 MD0 VSS 21 13 17 AVSS AVSS AVSS VSS 22 14 18 P70/AN0 P70/AN0 P70/AN0 NC 23 15 19 P71/AN1 P71/AN1 P71/AN1 NC 24 16 20 P72/AN2 P72/AN2 P72/AN2 NC 25 17 21 P73/AN3 P73/AN3 P73/AN3 NC 26 18 22 P74/AN4 P74/AN4 P74/AN4 NC 27 19 23 P75/AN5 P75/AN5 P75/AN5 NC — — 24 VSS VSS VSS VSS 28 20 25 P76/AN6 P76/AN6 P76/AN6 NC 29 21 26 P77/AN7 P77/AN7 P77/AN7 NC 30 22 27 AVCC AVCC AVCC VCC 31 23 28 P60/FTCI/TMCI0 P60/FTCI/TMCI0 P60/FTCI/TMCI0 NC — — 29 VSS VSS VSS VSS 32 24 30 P61/FTOA P61/FTOA P61/FTOA NC — — 31 VSS VSS VSS VSS 33 25 32 P62/FTIA P62/FTIA P62/FTIA NC 34 26 33 P63/FTIB/TMRI0 P63/FTIB/TMRI0 P63/FTIB/TMRI0 VCC — — 34 VSS VSS VSS VSS 35 27 35 P64/FTIC/TMO0 P64/FTIC/TMO0 P64/FTIC/TMO0 VCC 36 28 36 P65/FTID/TMCI1 P65/FTID/TMCI1 P65/FTID/TMCI1 NC 37 29 37 P66/FTOB/TMRI1 P66/FTOB/TMRI1 P66/FTOB/TMRI1 NC 38 30 38 P67/TMO1 P67/TMO1 P67/TMO1 NC 39 31 39 VCC VCC VCC VCC 40 32 40 A15 A27/A15 P27 CE 41 33 41 A14 P26/A14 P26 EA14 42 34 42 A13 P25/A13 P25 EA13 Note: Pins marked NC should be left unconnected. For details on PROM mode, refer to 14.2, PROM Mode. 10 Table 1-2 Pin Assignments in Each Operating Mode (cont) Pin No. DC-64S Expanded modes Single-chip mode PROM DP-64S FP-64A TFP-80C Mode 1 Mode 2 Mode 3 mode 43 35 43 A12 P24/A12 P24 EA12 44 36 44 A11 P23/A11 P23 EA11 — — 45 VSS VSS VSS VSS 45 37 46 A10 P22/A10 P22 EA10 46 38 47 A9 P21/A9 P21 OE 47 39 48 A8 P20/A8 P20 EA8 — — 49 VSS VSS VSS VSS 48 40 50 VSS VSS VSS VSS — — 51 VSS VSS VSS VSS 49 41 52 A7 P17/A7 P17 EA7 50 42 53 A6 P16/A6 P16 EA6 51 43 54 A5 P15/A5 P15 EA5 — — 55 VSS VSS VSS VSS 52 44 56 A4 P14/A4 P14 EA4 53 45 57 A3 P13/A3 P13 EA3 54 46 58 A2 P12/A2 P12 EA2 55 47 59 A1 P11/A1 P11 EA1 56 48 60 A0 P10/A0 P10 EA0 57 49 61 D0 D0 P30 EO0 58 50 62 D1 D1 P31 EO1 59 51 63 D2 D2 P32 EO2 60 52 64 D3 D3 P33 EO3 61 53 65 D4 D4 P34 EO4 — — 66 VSS VSS VSS VSS 62 54 67 D5 D5 P35 EO5 63 55 68 D6 D6 P36 EO6 64 56 69 D7 D7 P37 EO7 — — 70 VSS VSS VSS VSS Note: Pins marked NC should be left unconnected. For details on PROM mode, refer to 14.2, PROM Mode. 11 (2) Pin Functions: Table 1-3 gives a concise description of the function of each pin. Table 1-3 Pin Functions Pin No. Type Symbol DC-64S DP-64S FP-64A TFP-80C I/O Name and function Power VCC 14, 39 6, 31 6, 39 I Power: Connected to the power supply (+5 V or +3 V). Connect both VCC pins to the system power supply (+5 V or +3 V). VSS 16, 48 8, 40 8, 9, 10, I 12, 15, 24, 29, 31, 34, 45, 49, 50, 51, 55, 66, 70, 73, 76 Ground: Connected to ground (0 V). Connect all VSS pins to system ground (0 V). XTAL 17 9 11 I Crystal: Connected to a crystal oscillator. The crystal frequency should be the same as the desired system clock frequency. If an external clock is input at the EXTAL pin, a reverse-phase clock should be input at the XTAL pin. EXTAL 18 10 13 I External crystal: Connected to a crystal oscillator or external clock. The frequency of the external clock should be the same as the desired system clock frequency. See section 6.2, Oscillator Circuit for examples of connections to a crystal and external clock. ø 7 63 79 O System clock: Supplies the system clock to peripheral devices. RES 12 4 4 I Reset: A Low input causes the chip to reset. STBY 15 7 7 I Standby: A transition to the hardware standby mode (a power-down state) occurs when a Low input is received at the STBY pin. A15 to A0 40 to 47, 32 to 39, 40 to 44, 49 to 56 41 to 48 46 to 48, 52 to 54, 56 to 60 O Address bus: Address output pins. Clock System control Address bus 12 Table 1-3 Pin Functions (cont) Pin No. DC-64S DP-64S FP-64A Type Symbol Data bus D7 to D0 64 to 57 56 to 49 65 to 61, 69 to 67 I/O Data bus: 8-Bit bidirectional data bus. Bus control WAIT 8 64 80 I Wait: Requests the CPU to insert wait states into the bus cycle when an external address is accessed. RD 4 60 75 O Read: Goes Low to indicate that the CPU is reading an external address. WR 5 61 77 O Write: Goes Low to indicate that the CPU is writing to an external address. AS 6 62 78 O Address strobe: Goes Low to indicate that there is a valid address on the address bus. NMI 13 5 5 I Nonmaskable interrupt: Highestpriority interrupt request. The NMIEG bit in the system control register (SYSCR) determines whether the interrupt is recognized at the rising or falling edge of the NMI input. IRQ0 to IRQ2 1 to 3 57 to 59 71, 72, 74 I Interrupt request 0 to 2: Maskable interrupt request pins. MD1, MD0 19, 20 11, 12 I Mode: Input pins for setting the MCU operating mode according to the table below. Interrupt signals Operating mode control TFP-80C 14, 16 I/O Name and function MD1 MD0 Mode 13 Description 0 1 Mode 1 Expanded mode with on-chip ROM disabled 1 0 Mode 2 Expanded mode with on-chip ROM enabled 1 1 Mode 3 Single-chip mode Table 1-3 Pin Functions (cont) Pin No. Type Symbol 16-bit free- FTOA, running FTOB timer (FRT) FTCI 8-bit timer Serial communication interface (SCI) A/D converter DC-64S DP-64S FP-64A TFP-80C I/O Name and function 32, 37 24, 29 30, 37 O FRT output compare A and B: Output pins controlled by comparators A and B of the free-running timer. 31 23 28 I FRT counter clock input: Input pin for an external clock signal for the free-running timer. FTIA to FTID 33 to 36 25 to 28 32, 33, 35, I 36 FRT input capture A to D: Input capture pins for the free-running timer. TMO0, TMO1 35, 38 27, 30 35, 38 O 8-bit timer output (channels 0 and 1): Compare-match output pins for the 8-bit timers. TMCI0, TMCI1 31, 36 23, 28 28, 36 I 8-bit timer counter clock input (channels 0 and 1): External clock input pins for the 8-bit timer counters. TMRI0, TMRI1 34, 37 26, 29 33, 37 I 8-bit timer counter reset input (channels 0 and 1): A High input at these pins resets the 8-bit timer counters. TxD 9 1 1 O Transmit data: Data output pin for the serial communication interface. RxD 10 2 2 I Receive data: Data input pin for the serial communication interface. SCK 11 3 3 I/O Serial clock: Input/output pin for the serial clock. AN7 to AN0 29 to 22 21 to 14 26, 25, 23 to 18 I Analog input: Analog signal input pins for the A/D converter. ADTRG 1 57 71 I A/D trigger: External trigger input for starting the A/D converter. AVCC 30 22 27 I Programmable Wait Mode: The number of wait states (TW) selected by bits WC1 and WC0 are inserted in all accesses to external addresses, regardless of the WAIT pin state. AVSS 21 13 17 I Analog ground: Ground pin for the A/D converter. Connect to system ground. 14 Table 1-3 Pin Functions (cont) Pin No. DC-64S DP-64S FP-64A Type Symbol TFP-80C I/O Name and function Generalpurpose I/O P17 to P10 49 to 56 41 to 48 52 to 54, 56 to 60 I/O Port 1: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability. The direction of each bit can be selected in the port 1 data direction register (P1DDR). P27 to P20 40 to 47 32 to 39 40 to 44, 46 to 48 I/O Port 2: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability. The direction of each bit can be selected in the port 2 data direction register (P2DDR). P37 to P30 64 to 57 56 to 49 69 to 67, 65 to 61 I/O Port 3: An 8-bit input/output port with programmable MOS input pull-ups. The direction of each bit can be selected in the port 3 data direction register (P3DDR). P47 to P40 8 to 1 64 to 57 80 to 77 I/O Port 4: An 8-bit input/output port. The 75, 74, 72, direction of each bit can be selected 71 in the port 4 data direction register (P4DDR). P52 to P50 11 to 9 3 to 1 3 to 1 I/O Port 5: A 3-bit input/output port. The direction of each bit can be selected in the port 5 data direction register (P5DDR). I/O Port 6: An 8-bit input/output port. The P67 to P60 38 to 31 30 to 23 38 to 35, 33, 32, 30, direction of each bit can be selected 28 in the port 6 data direction register (P6DDR). P77 to P70 29 to 22 21 to 14 26, 25, 23 to 18 15 I Port 7: An 8-bit input port. 16 Section 2 CPU 2.1 Overview The H8/300 CPU is a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed operation. 2.1.1 Features The main features of the H8/300 CPU are listed below. • Two-way register configuration — Sixteen 8-bit general registers, or — Eight 16-bit general registers • Instruction set with 57 basic instructions, including: — Multiply and divide instructions — Powerful bit-manipulation instructions • Eight addressing modes — — — — — — — — Register direct (Rn) Register indirect (@Rn) Register indirect with displacement (@(d:16, Rn)) Register indirect with post-increment or pre-decrement (@Rn+ or @–Rn) Absolute address (@aa:8 or @aa:16) Immediate (#xx:8 or #xx:16) PC-relative (@(d:8, PC)) Memory indirect (@@aa:8) • Maximum 64-kbyte address space • High-speed operation — All frequently-used instructions are executed in two to four states • Maximum clock rate (ø clock): 16 MHz at 5 V, 12 MHz at 4 V or 10 MHz at 3 V — 8- or 16-bit register-register add or subtract: 125 ns (16 MHz), 167 ns (12 MHz), 200 ns (10 MHz) — 8 × 8-bit multiply: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) — 16 ÷ 8-bit divide: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) • Power-down mode — SLEEP instruction 17 2.1.2 Address Space The H8/300 CPU supports an address space with a maximum size of 64 kbytes for program code and data combined. The memory map differs depending on the mode (mode 1, 2, or 3). For details, see section 3.4, Address Space Map in Each Operating Mode. 2.1.3 Register Configuration Figure 2-1 shows the internal register structure of the H8/300 CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 0 7 0 R0H R0L R1H R1L R2H R2L R3H R3L R4H R4L R5H R5L R6H R6L R7H (SP) SP: Stack pointer R7L Control registers 15 0 PC CCR PC: Program counter 7 6 5 4 3 2 1 0 I UHUNZ VC CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit Figure 2-1 CPU Registers 18 2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed separately as 8-bit registers (R0H to R7H and R0L to R7L). R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and subroutine calls. In assembly-language coding, R7 can also be denoted by the letters SP. As indicated in figure 2-2, R7 (SP) points to the top of the stack. Unused area SP (R7) Stack area Figure 2-2 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). (1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit of the PC is ignored (always regarded as 0). (2) Condition Code Register (CCR): This 8-bit register contains internal status information, including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the interrupt mask bit (I). Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are masked. This bit is set to 1 automatically by a reset and at the start of interrupt handling. 19 Bit 6—User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 5—Half-Carry Flag (H): This flag is set to 1 when the ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to 0 otherwise. Similarly, it is set to 1 when the ADD.W, SUB.W, or CMP.W instruction causes a carry or borrow out of bit 11, and cleared to 0 otherwise. It is used implicitly in the DAA and DAS instructions. Bit 4—User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 3—Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result of an instruction. Bit 2—Zero Flag (Z): This flag is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result. Bit 1—Overflow Flag (V): This flag is set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): This flag is used by: • Add and subtract instructions, to indicate a carry or borrow at the most significant bit of the result • Shift and rotate instructions, to store the value shifted out of the most significant or least significant bit • Bit manipulation and bit load instructions, as a bit accumulator The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR, and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used in conditional branching instructions (BCC). For the action of each instruction on the flag bits, see the H8/300 Series Programming Manual. 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt mask bit (I) in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer and CCR should be initialized by software, by the first instruction executed after a reset. 20 2.3 Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. • Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand. • All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. • The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. • The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU (16 bits ÷ 8 bits) instructions operate on word data. 21 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. Data Format 7 1-bit data RnH 1-bit data RnL Byte data RnH Byte data RnL Word data Rn 4-bit BCD data RnH 7 0 6 5 4 3 2 1 0 Don’t care 7 Don’t care 7 7 0 MSB LSB Don’t care 0 6 5 3 2 1 0 Don’t care 7 0 MSB LSB 15 0 MSB LSB 7 4 3 Upper digit 0 Lower digit Don’t care 7 4-bit BCD data 4 Don’t care RnL 4 Upper digit Legend RnH: Upper digit of general register RnL: Lower digit of general register MSB: Most significant bit LSB: Least significant bit Figure 2-3 Register Data Formats 22 0 3 Lower digit 2.3.2 Memory Data Formats Figure 2-4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, no address error occurs but the access is performed at the preceding even address. This rule affects MOV.W instructions and branching instructions, and implies that only even addresses should be stored in the vector table. Data Type Address Data Format 7 1-bit data Address n 7 Byte data Address n MSB Even address MSB Word data Odd address Byte data (CCR) on stack Word data on stack 0 6 5 4 3 2 1 0 LSB Upper 8 bits Lower 8 bits LSB MSB CCR LSB Odd address MSB CCR* LSB Even address MSB Even address Odd address LSB Note: * Ignored on return Legend CCR: Condition code register Figure 2-4 Memory Data Formats When the stack is addressed by register R7, it must always be accessed a word at a time. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored. 23 2.4 Addressing Modes 2.4.1 Addressing Mode The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes No. Addressing Mode Symbol (1) Register direct Rn (2) Register indirect @Rn (3) Register indirect with displacement @(d:16, Rn) (4) Register indirect with post-increment Register indirect with pre-decrement @Rn+ @–Rn (5) Absolute address @aa:8 or @aa:16 (6) Immediate #xx:8 or #xx:16 (7) Program-counter-relative @(d:8, PC) (8) Memory indirect @@aa:8 (1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. In most cases the general register is accessed as an 8-bit register. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands. (2) Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand. (3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in MOV instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4) which is added to the contents of the specified general register to obtain the operand address. For the MOV.W instruction, the resulting address must be even. (4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with Post-Increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is incremented after the operand is accessed. The size of the increment is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. 24 • Register Indirect with Pre-Decrement—@–Rn The @–Rn mode is used with MOV instructions that store register contents to memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed. The size of the decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. (5) Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H'FFxx. The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to 65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. (6) Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the instruction, specifying a bit number. (7) Program-Counter-Relative—@(d:8, PC): This mode is used to generate branch addresses in the Bcc and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a signextended value to the program counter contents. The result must be an even number. The possible branching range is –126 to +128 bytes (–63 to +64 words) from the current address. (8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0 to 255). The word located at this address contains the branch address. The upper 8 bits of the absolute address are 0 (H'00), thus the branch address is limited to values from 0 to 255 (H'0000 to H'00FF). Note that some of the addresses in this range are also used in the vector table. Refer to section 3.4, Address Space Map in Each Operating Mode. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See section 2.3.2, Memory Data Formats, for further information. 25 2.4.2 Calculation of Effective Address Table 2-2 shows how the H8/300 calculates effective addresses in each addressing mode. Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, and XOR.B instructions can also use immediate addressing (6). The MOV instruction uses all the addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute (5) addressing to identify a byte operand, and 3-bit immediate addressing to identify a bit within the byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to identify the bit. 26 27 4 3 2 regm op 7 6 reg 4 3 4 3 regn 0 0 op disp 7 6 op 7 6 4 3 reg 0 0 15 op 7 6 reg 4 3 0 Register indirect with pre-decrement, @–Rn 15 4 3 reg Register indirect with post-increment, @Rn+ 15 Register indirect with displacement, @(d:16, Rn) 15 Register indirect, @Rn op 8 7 Register direct, Rn 1 15 Addressing Mode and Instruction Format No. Table 2-2 Effective Address Calculation 0 0 0 0 1 or 2 * 16-bit register contents 1 or 2 * 16-bit register contents disp 16-bit register contents 16-bit register contents 3 regm 0 Effective Address 3 regn 0 15 15 15 15 0 0 0 0 Operands are contained in registers regm and regn Note: * 1 for a byte operand, 2 for a word operand 15 15 15 15 Effective Address Calculation 28 7 6 5 No. op op 15 op PC-relative @(d:8, PC) 15 #xx:16 15 Immediate #xx:8 15 @aa:16 15 8 7 IMM op 8 7 abs op 8 7 Absolute address @aa:8 Addressing Mode and Instruction Format disp IMM abs 0 0 0 0 0 Table 2-2 Effective Address Calculation (cont) PC contents Sign extension 15 disp Effective Address Calculation 0 H'FF 8 7 0 0 15 0 Operand is 1- or 2-byte immediate data 15 15 Effective address 29 Legend reg: General register op: Operation code disp: Displacement IMM: Immediate data abs: Absolute address op 8 7 abs Memory indirect, @@aa:8 8 15 Addressing Mode and Instruction Format No. 0 Table 2-2 Effective Address Calculation (cont) 15 8 7 Memory contents (16 bits) H'00 Effective Address Calculation 0 15 Effective Address 0 2.5 Instruction Set The H8/300 CPU has 57 types of instructions, which are classified by function in table 2-3. Table 2-3 Instruction Classification Function Instructions Types Data transfer MOV, MOVTPE*3, MOVFPE*3, PUSH*1, POP*1 3 Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG 14 Logic operations AND, OR, XOR, NOT 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8 Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST 14 Branch Bcc*2, JMP, BSR, JSR, RTS 5 System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8 Block data transfer EEPMOV 1 Total 57 Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP. POP Rn is equivalent to MOV.W @SP+, Rn. 2. Bcc is a conditional branch instruction in which cc represents a condition code. 3. Not supported by the H8/3297 Series. The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. Operation Notation Rd General register (destination) #xx:3 3-Bit immediate data Rs General register (source) #xx:8 8-Bit immediate data Rn General register #xx:16 16-Bit immediate data (EAd) Destination operand disp Displacement (EAs) Source operand + Addition SP Stack pointer – Subtraction PC Program counter × Multiplication CCR Condition code register ÷ Division N N (negative) flag of CCR ∧ AND logical Z Z (zero) flag of CCR ∨ OR logical V V (overflow) flag of CCR ⊕ Exclusive OR logical C C (carry) flag of CCR → Move #imm Immediate data ¬ Not 30 2.5.1 Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction Size* Function MOV B/W (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @–Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @–R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. MOVTPE B Not supported by the H8/3437 Series. MOVFPE B Not supported by the H8/3437 Series. PUSH W Rn → @–SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @–SP. POP W @SP+ → Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. Note: * Size: Operand size B: Byte W: Word 31 15 8 7 op 0 rm 15 8 rn 0 rm 15 8 Rm→Rn 7 op rn @Rm←→Rn 7 op MOV 0 rm rn rm rn @(d:16, Rm)←→Rn disp 15 8 7 op 15 8 op 0 7 0 rn 15 @Rm+→Rn, or Rn→@–Rm abs 8 @aa:8←→Rn 7 0 op rn @aa:16←→Rn abs 15 8 op 7 0 rn 15 IMM 8 #xx:8→Rn 7 0 op rn #xx:16→Rn IMM 15 8 7 0 op rn MOVFPE, MOVTPE abs 15 8 7 0 op rn Legend op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2-5 Data Transfer Instruction Codes 32 POP, PUSH 2.5.2 Arithmetic Operations Table 2-5 describes the arithmetic instructions. See figure 2-6 in section 2.5.4, Shift Operations, for their object codes. Table 2-5 Arithmetic Instructions Instruction Size* Function ADD SUB B/W Rd ± Rs → Rd, Rd + #imm → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. ADDX SUBX B Rd ± Rs ± C → Rd, Rd ± #imm ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. INC DEC B Rd ± #1 → Rd Increments or decrements a general register. ADDS SUBS W Rd ± #imm → Rd Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2. DAA DAS B Rd decimal adjust → Rd Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the CCR. MULXU B Rd × Rs → Rd Performs 8-bit ¥ 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. DIVXU B Rd ÷ Rs → Rd Performs 16-bit ÷ 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. CMP B/W Rd – Rs, Rd – #imm Compares data in a general register with data in another general register or with immediate data. Word data can be compared only between two general registers. NEG B 0 – Rd → Rd Obtains the two’s complement (arithmetic complement) of data in a general register. Note: * Size: Operand size B: Byte W: Word 33 2.5.3 Logic Operations Table 2-6 describes the four instructions that perform logic operations. See figure 2-6 in section 2.5.4, Shift Operations, for their object codes. Table 2-6 Logic Operation Instructions Instruction Size* Function AND B Rd ∧ Rs → Rd, Rd ∧ #imm → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B Rd ∨ Rs → Rd, Rd ∨ #imm → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B Rd ⊕ Rs → Rd, Rd ⊕ #imm → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B ¬ (Rd) → (Rd) Obtains the one’s complement (logical complement) of general register contents. Note: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2-7 describes the eight shift instructions. Figure 2-6 shows the object code formats of the arithmetic, logic, and shift instructions. Table 2-7 Shift Instructions Instruction Size* Function SHAL SHAR B Rd shift → Rd Performs an arithmetic shift operation on general register contents. SHLL SHLR B Rd shift → Rd Performs a logical shift operation on general register contents. ROTL ROTR B Rd rotate → Rd Rotates general register contents. ROTXL ROTXR B Rd rotate through carry → Rd Rotates general register contents through the C (carry) bit. Note: * Size: Operand size B: Byte 34 15 8 7 op 0 rm 15 8 7 0 op 15 7 op 0 rm 8 op rn 7 MULXU, DIVXU 0 rn ADD, ADDX, SUBX, CMP (#xx:8) IMM 15 8 7 op 0 rm 15 8 op ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT rn 8 15 ADD, SUB, CMP, ADDX, SUBX (Rm) rn 7 rn 15 rn AND, OR, XOR (Rm) 0 IMM 8 AND, OR, XOR (#xx:8) 7 0 op rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Legend op: Operation field rm, rn: Register field IMM: Immediate data Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes 35 2.5.5 Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 → (<bit no.> of <EAd>) Sets a specified bit in a general register or memory to 1. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → (<bit no.> of <EAd>) Clears a specified bit in a general register or memory to 0. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (<bit no.> of <EAd>) → (<bit no.> of <EAd>) Inverts a specified bit in a general register or memory. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register BTST B ¬ (<bit no.> of <EAd>) → Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register. BAND B C ∧ (<bit no.> of <EAd>) → C ANDs the C flag with a specified bit in a general register or memory. C ∧ [¬ (<bit no.> of <EAd>)] → C ANDs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. BIAND BOR B C ∨ [¬ (<bit no.> of <EAd>)] → C ORs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. BIOR BXOR C ∨ (<bit no.> of <EAd>) → C ORs the C flag with a specified bit in a general register or memory. B C ⊕ (<bit no.> of <EAd>) → C XORs the C flag with a specified bit in a general register or memory. Note: * Size: Operand size B: Byte 36 Table 2-8 Bit-Manipulation Instructions (cont) Instruction Size* Function BIXOR B C ⊕ ¬ [(<bit no.> of <EAd>)] → C XORs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. BLD B (<bit no.> of <EAd>) → C Copies a specified bit in a general register or memory to the C flag. ¬ (<bit no.> of <EAd>) → C Copies the inverse of a specified bit in a general register or memory to the C flag. The bit number is specified by 3-bit immediate data. BILD BST B C → (<bit no.> of <EAd>) Copies the C flag to a specified bit in a general register or memory. ¬ C → (<bit no.> of <EAd>) Copies the inverse of the C flag to a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. BIST Note: * Size: Operand size B: Byte Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-modifywrite instructions. They read a byte of data, modify one bit in the byte, then write the byte back. Care is required when these instructions are applied to registers with write-only bits and to the I/O port registers. Step Description 1 Read Read one data byte at the specified address 2 Modify Modify one bit in the data byte 3 Write Write the modified data byte back to the specified address Example 1: BCLR is executed to clear bit 0 in the port 1 data direction register (P1DDR) under the following conditions. P17: Input pin, low P16: Input pin, high P15 – P10: Output pins, low The intended purpose of this BCLR instruction is to switch P10 from output to input. 37 Before Execution of BCLR Instruction P17 P16 P15 P14 P13 P12 P11 P10 Input/output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low Low DDR 0 0 1 1 1 1 1 1 DR 1 0 0 0 0 0 0 0 Execution of BCLR Instruction BCLR ;clear bit 0 in data direction register #0, @P1DDR After Execution of BCLR Instruction P17 P16 P15 P14 P13 P12 P11 P10 Input/output Output Output Output Output Output Output Output Input Pin state Low High Low Low Low Low Low High DDR 1 1 1 1 1 1 1 0 DR 1 0 0 0 0 0 0 0 Explanation: To execute the BCLR instruction, the CPU begins by reading P1DDR. Since P1DDR is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to P1DDR to complete the BCLR instruction. As a result, P10DDR is cleared to 0, making P10 an input pin. In addition, P17DDR and P16DDR are set to 1, making P17 and P16 output pins. 38 BSET, BCLR, BNOT, BTST 15 8 7 op 0 IMM 15 8 7 op 0 rm 15 8 op 8 Operand: register direct (Rn) Bit no.: register direct (Rm) rn 7 op 15 Operand: register direct (Rn) Bit no.: immediate (#xx:3) rn 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit no.: 7 immediate (#xx:3) 0 op rn 0 0 0 0 Operand: register indirect (@Rn) op rm 0 0 0 0 Bit no.: 15 8 7 0 op abs op IMM 15 8 0 Operand: absolute (@aa:8) 0 0 7 0 Bit no.: immediate (#xx:3) 0 op abs op register direct (Rm) rm 0 Operand: absolute (@aa:8) 0 0 0 Bit no.: register direct (Rm) BAND, BOR, BXOR, BLD, BST 15 8 7 op 0 IMM 15 8 7 op op 15 8 Operand: register direct (Rn) Bit no.: immediate (#xx:3) rn 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit no.: 7 0 op abs op immediate (#xx:3) IMM 0 Operand: absolute (@aa:8) 0 0 0 Bit no.: Legend op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes 39 immediate (#xx:3) 2.5.6 Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Branching Instructions Instruction Size Function Bcc — Branches if condition cc is true. Mnemonic cc field Description Condition BRA (BT) BRN (BF) BHI BLS BCC (BHS) 0000 0001 0010 0011 0100 Always Never C∨Z=0 C∨Z=1 C=0 BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Always (true) Never (false) High Low or same Carry clear (High or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 N⊕V=0 N⊕V=1 Z ∨ (N ⊕ V) = 0 Z ∨ (N ⊕ V) = 1 JMP — Branches unconditionally to a specified address. JSR — Branches to a subroutine at a specified address. BSR — Branches to a subroutine at a specified displacement from the current address. RTS — Returns from a subroutine. 40 15 8 op 7 0 cc 15 disp 8 7 op 0 rm 15 Bcc 8 0 0 0 7 0 JMP (@Rm) 0 op JMP (@aa:16) abs 15 8 7 0 op abs 15 8 JMP (@@aa:8) 7 0 op disp 15 8 7 op 0 rm 15 BSR 8 0 0 0 7 0 JSR (@Rm) 0 op JSR (@aa:16) abs 15 8 7 0 op abs 15 8 7 JSR (@@aa:8) 0 op RTS Legend op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2-8 Branching Instruction Codes 41 2.5.7 System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Inst5ruction Size Function RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to the power-down state. LDC B Rs → CCR, #imm → CCR Moves immediate data or general register contents to the condition code register. STC B CCR → Rd Copies the condition code register to a specified general register. ANDC B CCR ∧ #imm → CCR Logically ANDs the condition code register with immediate data. ORC B CCR ∨ #imm → CCR Logically ORs the condition code register with immediate data. XORC B CCR ⊕ #imm → CCR Logically exclusive-ORs the condition code register with immediate data. NOP — PC + 2 → PC Only increments the program counter. Note: * Size: Operand size B: Byte 15 8 7 0 op 15 8 RTE, SLEEP, NOP 7 0 op 15 rn 8 7 LDC, STC (Rn) 0 op IMM ANDC, ORC, XORC, LDC (#xx:8) Legend op: Operation field rn: Register field IMM: Immediate data Figure 2-9 System Control Instruction Codes 42 2.5.8 Block Data Transfer Instruction Table 2-11 describes the EEPMOV instruction. Figure 2-10 shows its object code format. Table 2-11 Block Data Transfer Instruction/EEPROM Write Operation Instruction Size Function EEPMOV — if R4L ≠ 0 then repeat @R5+ → @R6+ R4L – 1 → R4L until R4L = 0 else next; Moves a data block according to parameters set in general registers R4L, R5, and R6. R4L: size of block (bytes) R5: starting source address R6: starting destination address Execution of the next instruction starts as soon as the block transfer is completed. 15 8 7 0 op op Legend op: Operation field Figure 2-10 Block Data Transfer Instruction/EEPROM Write Operation Code 43 Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 → ← R6 R5 + R4L → 2. ← R6 + R4L When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction. R5 → R5 + R4L → ← R6 H'FFFF Not allowed 44 ← R6 + R4L 2.6 CPU States 2.6.1 Overview The CPU has three states: the program execution state, exception-handling state, and power-down state. The power-down state is further divided into three modes: sleep mode, software standby mode, and hardware standby mode. Figure 2-11 summarizes these states, and figure 2-12 shows a map of the state transitions. State Program execution state The CPU executes successive program instructions. Exception-handling state A transient state triggered by a reset or interrupt. The CPU executes a hardware sequence that includes loading the program counter from the vector table. Sleep mode Power-down state A state in which some or all of the chip functions are stopped to conserve power. Software standby mode Hardware standby mode Figure 2-11 Operating States 45 Exception handling request Exceptionhandling state RES = 1 Reset state Program execution state Exception handing Interrupt request NMI or IRQ0 to IRQ2 SLEEP instruction with SSBY bit set SLEEP instruction Sleep mode Software standby mode STBY = 1, RES = 0 Hardware standby mode Power-down state Notes: 1. A transition to the reset state occurs when RES goes low, except when the chip is in the hardware standby mode. 2. A transition from any state to the hardware standby mode occurs when STBY goes low. Figure 2-12 State Transitions 2.6.2 Program Execution State In this state the CPU executes program instructions. 2.6.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU is reset or interrupted and changes its normal processing flow. In interrupt exception handling, the CPU references the stack pointer (R7) and saves the program counter and condition code register on the stack. For further details see section 4, Exception Handling. 2.6.4 Power-Down State The power-down state includes three modes: sleep mode, software standby mode, and hardware standby mode. (1) Sleep Mode: Is entered when a SLEEP instruction is executed. The CPU halts, but CPU register contents remain unchanged and the on-chip supporting modules continue to function. 46 (2) Software Standby Mode: Is entered if the SLEEP instruction is executed while the SSBY (Software Standby) bit in the system control register (SYSCR) is set. The CPU and all on-chip supporting modules halt. The on-chip supporting modules are initialized, but the contents of the onchip RAM and CPU registers remain unchanged as long as a specified voltage is supplied. I/O port outputs also remain unchanged. (3) Hardware Standby Mode: Is entered when the input at the STBY pin goes low. All chip functions halt, including I/O port output. The on-chip supporting modules are initialized, but onchip RAM contents are held. See section 15, Power-Down State, for further information. 2.7 Access Timing and Bus Cycle The CPU is driven by the system clock (ø). The period from one rising edge of the system clock to the next is referred to as a “state.” Memory access is performed in a two- or three-state bus cycle. On-chip memory, on-chip supporting modules, and external devices are accessed in different bus cycles as described below. 2.7.1 Access to On-Chip Memory (RAM and ROM) On-chip ROM and RAM are accessed in a cycle of two states designated T1 and T2. Either byte or word data can be accessed, via a 16-bit data bus. Figure 2-13 shows the on-chip memory access cycle. Figure 2-14 shows the associated pin states. 47 Bus cycle T2 state T1 state ø Address Internal address bus Internal read signal Read data Internal data bus (read) Internal write signal Internal data bus (write) Write data Figure 2-13 On-Chip Memory Access Cycle Bus cycle T2 state T1 state ø Address Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 2-14 Pin States during On-Chip Memory Access Cycle 48 2.7.2 Access to On-Chip Register Field and External Devices The on-chip supporting module registers and external devices are accessed in a cycle consisting of three states: T1, T2, and T3. Only one byte of data can be accessed per cycle, via an 8-bit data bus. Access to word data or instruction codes requires two consecutive cycles (six states). Figure 2-15 shows the access cycle for the on-chip register field. Figure 2-16 shows the associated pin states. Figures 2-17 (a) and (b) show the read and write access timing for external devices. Bus cycle T2 state T1 state T3 state ø Internal address bus Address Internal read signal Internal data bus (read) Read data Internal write signal Internal data bus (write) Write data Figure 2-15 On-Chip Register Field Access Cycle 49 Bus cycle T2 state T1 state T3 state ø Address Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 2-16 Pin States during On-Chip Register Field Access Cycle Read cycle T2 state T1 state T3 state ø Address Address bus AS RD WR: High Data bus Read data Figure 2-17 (a) External Device Access Timing (Read) 50 Write cycle T2 state T1 state T3 state ø Address bus Address AS RD: High WR Data bus Write data Figure 2-17 (b) External Device Access Timing (Write) 51 Section 3 MCU Operating Modes and Address Space 3.1 Overview 3.1.1 Mode Selection The H8/3297 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the inputs at the mode pins (MD1 and MD0). See table 3-1. Table 3-1 Operating Modes Mode MD1 MD0 Address space On-chip ROM On-chip RAM Mode 0 Low Low — — — Mode 1 Low High Expanded Disabled Enabled* Mode 2 High Low Expanded Enabled Enabled* Mode 3 High High Single-chip Enabled Enabled Note: * If the RAME bit in the system control register (SYSCR) is cleared to 0, off-chip memory can be accessed instead. Modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices. The maximum address space supported by these externally expanded modes is 64 kbytes. In mode 3 (single-chip mode), only on-chip ROM and RAM and the on-chip register field are used. All ports are available for general-purpose input and output. Mode 0 is inoperative in the H8/3297 Series. Avoid setting the mode pins to mode 0. 53 3.1.2 Mode and System Control Registers Table 3-2 lists the registers related to the chip’s operating mode: the system control register (SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the mode pins MD1 and MD0. Table 3-2 Mode and System Control Registers Name Abbreviation Read/Write Address System control register SYSCR R/W H'FFC4 Mode control register MDCR R H'FFC5 3.2 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 XRST NMIEG — RAME Initial value 0 0 0 0 1 0 1 1 Read/Write R/W R/W R/W R/W R R/W — R/W The system control register (SYSCR) is an 8-bit register that controls the operation of the chip. Bit 7—Software Standby (SSBY): Enables transition to the software standby mode. For details, see section 15, Power-Down State. On recovery from software standby mode by an external interrupt, the SSBY bit remains set to 1. It can be cleared by writing 0. Bit 7 SSBY Description 0 The SLEEP instruction causes a transition to sleep mode. 1 The SLEEP instruction causes a transition to software standby mode. 54 (Initial value) Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. During the selected time the CPU and on-chip supporting modules continue to stand by. These bits should be set according to the clock frequency so that the settling time is at least 8 ms. For specific settings, see section 15.3.3, Clock Settling Time for Exit from Software Standby Mode. Bit 6 STS2 Bit 5 STS1 Bit 4 STS0 Description 0 0 0 Settling time = 8,192 states 0 0 1 Settling time = 16,384 states 0 1 0 Settling time = 32,768 states 0 1 1 Settling time = 65,536 states 1 0 — Settling time = 131,072 states 1 1 — Disabled (Initial value) Bit 3—External Reset (XRST): Indicates the source of a reset. A reset can be generated by input of an external reset signal, or by a watchdog timer overflow when the watchdog timer is used. XRST is a read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow. Bit 3 XRST Description 0 Reset was caused by watchdog timer overflow. 1 Reset was caused by external input. (Initial value) Bit 2—NMI Edge (NMIEG): Selects the valid edge of the NMI input. Bit 2 NMIEG Description 0 An interrupt is requested on the falling edge of the NMI input. 1 An interrupt is requested on the rising edge of the NMI input. 55 (Initial value) Bit 1—Reserved: This bit cannot be modified and is always read as 1. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by a reset, but is not initialized in the software standby mode. Bit 0 RAME Description 0 The on-chip RAM is disabled. 1 The on-chip RAM is enabled. (Initial value) 3.3 Mode Control Register (MDCR) Bit 7 6 5 4 3 2 1 0 — — — — — — MDS1 MDS0 Initial value 1 1 1 0 0 1 * * Read/Write — — — — — — R R Note: * Initialized according to MD1 and MD0 inputs. The mode control register (MDCR) is an 8-bit register that indicates the operating mode of the chip. Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1. Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0. Bit 2—Reserved: This bit cannot be modified and is always read as 1. Bits 1 and 0—Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the mode pins (MD1 and MD0), thereby indicating the current operating mode of the chip. MDS1 corresponds to MD1 and MDS0 to MD0. These bits can be read but not written. When the mode control register is read, the levels at the mode pins (MD1 and MD0) are latched in these bits. 56 3.4 Address Space Map in Each Operating Mode Figures 3-1 to 3-4 show memory maps of the H8/3297, H8/3296, H8/3294, and H8/3292 in modes 1, 2, and 3. Mode 1 Expanded Mode without On-Chip ROM H'0000 Mode 2 Expanded Mode with On-Chip ROM H'0000 Vector table Mode 3 Single-Chip Mode H'0000 Vector table H'0049 H'004A H'0049 H'004A Vector table H'0049 H'004A On-chip ROM, PROM 61,312 bytes On-chip ROM, PROM 63,360 bytes External address space H'EF7F H'EF80 External address apace H'F77F H'F780 H'FF7F H'F780 H'F77F H'F780 On-chip RAM*, 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF On-chip RAM*, 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF On-chip RAM, 2,048 bytes H'FF7F H'FF88 On-chip register field H'FFFF Note: * External memory can be accessed at these addresses when the RAME bit in the system control register (SYSCR) is cleared to 0. Figure 3-1 H8/3297 Address Space Map 57 Mode 1 Expanded Mode without On-Chip ROM H'0000 Mode 2 Expanded Mode with On-Chip ROM H'0000 Mode 3 Single-Chip Mode H'0000 Vector table Vector table H'0049 H'004A H'0049 H'004A Vector table H'0049 H'004A On-chip ROM 49,152 bytes On-chip ROM 49,152 bytes External address space H'BFFF H'BFFF H'C000 Reserved*1 Reserved*1 H'EF7F H'EF80 External address space H'F77F H'F780 H'F77F H'F780 H'F77F H'F780 On-chip RAM *2 , 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF On-chip RAM *2 , 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF On-chip RAM 2,048 bytes H'FF7F H'FF88 On-chip register field H'FFFF Notes: *1 Do not access reserved areas. *2 External memory can be accessed at these addresses when the RAME bit in the system control register (SYSCR) is cleared to 0. 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[email protected][email protected][email protected][email protected]@@[email protected]??)X??W&? ? @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@(M?I'@@@@@@@@@@(MI'@[email protected]@@@@[email protected]@@@@@@@@?eI'@@(M?I'@@V'@@([email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@(M?I'@@@@@@@@@@(MI'@[email protected]@@@@[email protected]@@@@@@@@?eI'@@(M?I'@@V'@@([email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ W.M?I/K?g?W.MI/[email protected] [email protected]?W.M?I/[email protected][email protected]? W.M?I/K?g?W.MI/[email protected] [email protected]?W.M?I/[email protected][email protected]? @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@([email protected]@@@@@@@@(Q26P'[email protected]@@@@@@@@@@@@@@[email protected]@[email protected]([email protected]'@[email protected]@[email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@([email protected]@@@@@@@@(Q26P'[email protected]@@@@@@@@@@@@@@[email protected]@[email protected]([email protected]'@[email protected]@[email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ [email protected]@@@6Xe?7H??V'@@@[email protected][email protected]@@[email protected][email protected]@[email protected]@? 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[email protected]@[email protected]@@?3L??W&@[email protected][email protected][email protected][email protected][email protected][email protected]@@[email protected]? ??? @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@[email protected]@@[email protected]@@[email protected]@@([email protected]@@[email protected][email protected][email protected]@@[email protected]@@[email protected]@[email protected]@@@[email protected]?)??&[email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@[email protected]@@[email protected]@@[email protected]@@([email protected]@@[email protected][email protected][email protected]@@[email protected]@@[email protected]@[email protected]@@@[email protected]?)??&[email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ V/[email protected][email protected]?V/[email protected][email protected][email protected][email protected][email protected][email protected]?V/[email protected][email protected][email protected]? V/[email protected][email protected]?V/[email protected][email protected][email protected][email protected][email protected][email protected]?V/[email protected][email protected][email protected]? @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)[email protected]&[email protected]@@[email protected]@@)P40Q&[email protected]@@[email protected][email protected][email protected]@<[email protected]@@[email protected]@@[email protected])[email protected]&@[email protected][email protected][email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)[email protected]&[email protected]@@[email protected]@@)P40Q&[email protected]@@[email protected][email protected][email protected]@<[email protected]@@[email protected]@@[email protected])[email protected]&@[email protected][email protected][email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ [email protected][email protected][email protected][email protected][email protected][email protected][email protected]@@[email protected][email protected]@[email protected]?([email protected]? [email protected][email protected][email protected][email protected][email protected][email protected][email protected]@@[email protected][email protected]@[email protected]?([email protected]? ? @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)K?O&@[email protected]@@[email protected]@@@)KO&@[email protected]@@[email protected][email protected]?eO&@@@[email protected]@@[email protected]@)K?O&@@[email protected]&@[email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@)K?O&@[email protected]@@[email protected]@@@)KO&@[email protected]@@[email protected][email protected]?eO&@@@[email protected]@@[email protected]@)K?O&@@[email protected]&@[email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ [email protected] [email protected] @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@[email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@[email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ [email protected] [email protected] ?? @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@[email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@[email protected]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ? @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ? @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@?? @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ? @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@? @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@? 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