HD74AC4024 7-State Binary Counter Description The HD74AC4024 is a 4-stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Feature • Outputs Source/Sink 24 mA Pin Arrangement Clock 1 14 Reset 2 13 NC Q7 3 12 Q1 Q6 4 11 Q2 Q5 5 10 NC Q4 6 9 Q3 GND 7 8 NC (Top view) VCC HD74AC4024 Logic Symbol C R Q7 Q1 Q6 Q2 Q5 Q4 Q3 Pin Names Clock Reset Q1 to Q7 Clock Input (Active Falling Edge) Master Reset Input Outputs Function Table Clock Reset Outputs State L L No change L H All outputs are low H L No change H H All outputs are low L No change H All outputs are low L Advance to next state H All outputs are low H : L : 2 High voltage level Low voltage level : Low-to-High Clock Transition : High-to-Low Clock Transition HD74AC4024 Logic Diagram Clock C Q C Q C Q C Q R Q R Q R Q R Q Reset Q1 Q2 Q3 Q4 DC Characteristics (unless otherwise specified) Item Symbol Max Unit Condition Maximum quiescent supply current I CC 80 µA VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case Maximum quiescent supply current I CC 8.0 µA VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C AC Characteristics Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum clock f max 3.3 70 — — 60 — MHz 5.0 110 — — 95 — 3.3 1.0 9.5 12.5 1.0 13.5 5.0 1.0 7.0 9.0 1.0 9.5 3.3 1.0 9.5 12.0 1.0 13.0 5.0 1.0 6.5 9.0 1.0 10.0 3.3 1.0 10.5 12.5 1.0 13.5 5.0 1.0 7.5 10.0 1.0 11.0 frequency Propagation delay t PLH Clock to Q1 Propagation delay t PHL Clock to Q1 Propagation delay Reset to outputs Note: t PHL ns ns ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V 3 HD74AC4024 AC Operating Requirements Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Reset to Clock t rec 3.3 –2.5 0.0 0.0 ns 5.0 –1.5 0.0 0.0 3.3 3.0 4.0 4.5 5.0 2.0 3.0 3.5 Pulse width Clock Note: tw 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 60 pF VCC = 5.0 V 4 ns Unit: mm 19.20 20.32 Max 8 6.30 7.40 Max 14 1.30 7 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 2.39 Max 2.54 Min 5.06 Max 1 7.62 + 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 8 5.5 14 1 0.10 ± 0.10 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7 + 0.20 7.80 – 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g Unit: mm 8.65 9.05 Max 8 1 7 *0.20 ± 0.05 0.635 Max 1.75 Max 3.95 14 + 0.10 6.10 – 0.30 1.08 *0.40 ± 0.06 0.11 0.14 +– 0.04 0° – 8° 1.27 0.67 0.60 +– 0.20 0.15 0.25 M *Pd plating Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DN Conforms Conforms 0.13 g Cautions 1. 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