HOLTEK HT46R47

HT46R47
8-Bit OTP Battery Charger Controller
Features
·
·
·
·
·
·
·
·
·
·
Operating voltage:
fSYS=4MHz: 3.3V~5.5V
fSYS=8MHz: 4.5V~5.5V
13 bidirectional I/O lines (max.)
1 interrupt input shared with an I/O line
8-bit programmable timer/event counter with
overflow interrupt and 7-stage prescaler
On-chip crystal and RC oscillator
Watchdog Timer
2048´14 program memory PROM
64´8 data memory RAM
Supports PFD for sound generation
HALT function and wake-up feature reduce
power consumption
·
·
·
·
·
·
·
·
·
·
Up to 0.5ms instruction cycle with 8MHz
system clock at VDD=5V
Six-level subroutine nesting
4 channels 9-bit resolution (8-bit accuracy)
A/D converter
1 channel (6+2)-bit PWM output shared
with an I/O line
Bit manipulation instruction
14-bit table read instruction
63 powerful instructions
All instructions in one or two machine
cycles
Low voltage reset function
18-pin DIP/SOP package
General Description
The program and option memories can be electrically programmed, making the microcontroller suitable for use in product development.
The device is an 8-bit high performance
RISC-like microcontroller designed for multiple I/O product applications. The device is particularly suitable for use in products such as
battery charger controllers and A/D applications. A HALT feature is included to reduce
power consumption.
Rev. 1.40
1
July 18, 2001
HT46R47
Block Diagram
P A 5 /IN T
In te rru p t
C ir c u it
M
T M R
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
U
P r e s c a le r
fS
Y S
P A 4 /T M R
X
T M R C
IN T C
P A 4
P A 3 /P F D
S Y S C L K /4
In s tr u c tio n
R e g is te r
M
M P
U
W D T
P r e s c a le r
D A T A
M e m o ry
X
P W
X
R C
P O R T D
P D
P D 0 /P W
O S C
M
M U X
In s tr u c tio n
D e c o d e r
4 -C h a n n e l
A /D C o n v e rte r
S T A T U S
A L U
S
S
P B C
S h ifte r
T im in g
G e n e ra to r
O S
R E
V D
V S
U
M
P D C
O S C 2
M
W D T
P A 3 , P A 5
C 1
A C C
P A C
O p tio n
P R O M
L V R
P O R T B
P B
P A
D
P O R T A
P B 0 /A N 0 ~ P B 3 /A N 3
P A 0
P A 3
P A 4
P A 5
P A 6
~ P
/P
/T
/IN
, P
A 2
F D
M R
T
A 7
Pin Assignment
P A 3 /P F D
1
1 8
P A 4 /T M R
P A 2
2
1 7
P A 5 /IN T
P A 1
3
1 6
P A 6
P A 0
P B 3 /A N 3
4
1 5
5
1 4
P A 7
O S C 2
P B 2 /A N 2
6
1 3
O S C 1
P B 1 /A N 1
7
1 2
V D D
P B 0 /A N 0
8
1 1
R E S
V S S
9
1 0
P D 0 /P W M
H T 4 6 R 4 7
1 8 D IP -A /S O P -A
Rev. 1.40
2
July 18, 2001
HT46R47
Pin Description
ROM Code
Option
Pin No.
Pin Name
I/O
Description
4~2
1
18
17
16, 15
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6, PA7
Bidirectional 8-bit input/output port. Each bit can be
configured as wake-up input by ROM code option.
Pull-high Software instructions determine the CMOS output or
I/O
Wake-up Schmitt trigger input with or without pull-high resistor
PA3 or PFD (determined by pull-high options: bit option). The PFD,
TMR and INT are pin-shared with PA3, PA4 and PA5,
respectively.
8
7
6
5
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
I/O
Pull-high
Bidirectional 4-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor
(determined by pull-high options: bit option) or A/D input.
Once a PB line is selected as an A/D input (by using
software control), the I/O function and pull-high
resistor are disabled automatically.
9
VSS
¾
¾
I/O
Pull-high
PD0 or
PWM
Negative power supply, ground.
Bidirectional I/O line. Software instructions determine the CMOS output, Schmitt trigger input with or
without a pull-high resistor (determined by pull-high
options: bit option). The PWM output function is
pin-shared with PD0 (dependent on PWM options).
10
PD0/PWM
11
RES
I
¾
Schmitt trigger reset input. Active low.
12
VDD
¾
¾
Positive power supply
13
14
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an RC network or a
Crystal (determined by ROM code option) for the internal system clock. In the case of RC operation, OSC2
is the output terminal for 1/4 system clock.
Absolute Maximum Ratings
Supply Voltage ...............VSS-0.3V to VSS+5.5V
Storage Temperature ................-50°C to 125°C
Input Voltage.................VSS-0.3V to VDD+0.3V
Operating Temperature ..............-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.40
3
July 18, 2001
HT46R47
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD1
Operating Voltage
¾
fSYS=4MHz
3.3
¾
5.5
V
VDD2
Operating Voltage
¾
fSYS=8MHz
4.5
¾
5.5
V
IDD1
Operating Current
(Crystal OSC)
3.3V No load, f
SYS=4MHz
ADC
disable
5V
¾
1.3
3
mA
¾
3
5
mA
IDD2
Operating Current
(RC OSC)
3.3V No load, f
SYS=4MHz
5V ADC disable
¾
1.3
3
mA
¾
3
5
mA
IDD3
Operating Current
5V
¾
4
8
mA
IADC
Only ADC Enable,
Others Disable
3.3V
¾
1
2
mA
¾
2
4
mA
ISTB1
Standby Current
(WDT Enabled)
3.3V
¾
¾
5
mA
¾
¾
10
mA
ISTB2
Standby Current
(WDT Disabled)
3.3V
¾
¾
1
mA
¾
¾
2
mA
VAD
A/D Input Voltage
¾
¾
0
¾
VDD
V
VIL1
3.3V
Input Low Voltage for
I/O Ports, TMR and INT 5V
¾
0
¾
0.3VDD
V
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for 3.3V
I/O Ports, TMR and INT 5V
¾
0.7VDD
¾
VDD
V
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage
(RES)
3.3V
¾
0
¾
0.4VDD
V
5V
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage
(RES)
3.3V
¾
0.9VDD
¾
VDD
V
5V
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
¾
2.7
3.0
3.3
V
IOL
I/O Port Sink Current
3.3V VOL=0.1VDD
4
8
¾
mA
VOL=0.1VDD
10
20
¾
mA
IOH
I/O Port Source
Current
3.3V VOH=0.9VDD
-2
-4
¾
mA
VOH=0.9VDD
-5
-10
¾
mA
Rev. 1.40
5V
5V
5V
5V
5V
No load, fsys=8MHz
ADC disable
No load
No load, system HALT
No load, system HALT
4
July 18, 2001
HT46R47
Symbol
Parameter
RPH
Pull-high Resistance
EAD
A/D Conversion Error
Test Conditions
Min.
Typ.
Max.
Unit
¾
40
60
80
kW
5V
¾
10
30
50
kW
5V
¾
¾
±0.5
±1
LSB
VDD
Conditions
3.3V
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
Min. Typ. Max. Unit
VDD
Conditions
3.3V
¾
400
¾
4000
kHz
5V
¾
400
¾
8000
kHz
3.3V
¾
400
¾
4000
kHz
5V
¾
400
¾
8000
kHz
3.3V
¾
0
¾
4000
kHz
5V
¾
0
¾
8000
kHz
fSYS1
System Clock
(Crystal OSC)
fSYS2
System Clock (RC OSC)
fTIMER
Timer I/P Frequency (TMR)
tAD
A/D Clock Period
5V
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tWDTOSC
Watchdog Oscillator
3.3V
¾
43
86
168
ms
5V
¾
36
72
144
ms
tWDT1
Watchdog Time-out Period
(RC)
2.8
5.6
11
s
2.3
4.7
9.4
s
tWDT2
Watchdog Time-out Period
(System Clock)
¾
¾
217
¾
218
tSYS
tRES
External Reset Low Pulse
Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer
Period
¾
Wake-up from HALT
¾
1024
¾
*tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
3.3V
¾
5V
Note: *tSYS=1/fSYS
Rev. 1.40
5
July 18, 2001
HT46R47
Functional Description
When executing a jump instruction, conditional
skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC
manipulates the program transfer by loading
the address corresponding to each instruction.
Execution flow
The system clock for the microcontroller is derived from either a crystal or an RC oscillator.
The system clock is internally divided into four
non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current
instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction.
Instruction fetching and execution are
pipelined in such a way that a fetch takes an instruction cycle while decoding and execution
takes the next instruction cycle. However, the
pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to complete the instruction.
The lower byte of the program counter (PCL) is
a readable and writeable register (06H).
Moving data into the PCL performs a short
jump. The destination will be within 256 locations.
Program counter - PC
The program counter (PC) controls the sequence in which the instructions stored in program PROM are executed and its contents
specify full range of program memory.
When a control transfer takes place, an additional dummy cycle is required.
After accessing a program memory word to fetch
an instruction code, the contents of the program
counter are incremented by one. The program
counter then points to the memory word containing the next instruction code.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
Program memory - PROM
The program memory is used to store the program instructions which are to be executed. It
also contains data, table, and interrupt entries,
and is organized into 2048´14 bits, addressed
by the program counter and table pointer.
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 1
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
P C + 2
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution flow
Rev. 1.40
6
July 18, 2001
HT46R47
0 0 0 H
Certain locations in the program memory are
reserved for special usage:
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
· Location 000H
This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H.
0 0 8 H
E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
0 0 C H
A /D
· Location 004H
P ro g ra m
M e m o ry
This area is reserved for the external interrupt service program. If the INT input pin is
activated, the interrupt is enabled and the
stack is not full, the program begins execution
at location 004H.
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
· Location 008H
7 0 0 H
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a timer/event counter
overflow, and if the interrupt is enabled and the
stack is not full, the program begins execution
at location 008H.
L o o k - u p T a b le ( 2 5 6 w o r d s )
7 F F H
1 4 b its
N o te : n ra n g e s fro m
0 to 7
Program memory
· Table location
· Location 00CH
Any location in the PROM space can be used
as look-up tables. The instructions "TABRDC
[m]" (the current page, 1 page=256 words)
and "TABRDL [m]" (the last page) transfer
the contents of the lower-order byte to the
specified data memory, and the higher-order
byte to TBLH (08H). Only the destination of
the lower-order byte in the table is
This area is reserved for the A/D converter interrupt service program. If an A/D converter
interrupt results from an end of A/D conversion, and if the interrupt is enabled and the
stack is not full, the program begins execution
at location 00CH.
Mode
C o n v e r te r In te r r u p t S u b r o u tin e
Program Counter
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
1
0
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
1
1
0
0
Skip
PC+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program counter
Note: *10~*0: Program counter bits
S10~S0: Stack register bits
#10~#0: Instruction code bits
Rev. 1.40
@7~@0: PCL bits
7
July 18, 2001
HT46R47
a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the program counter is restored to its previous value
from the stack. After a chip reset, the SP will
point to the top of the stack.
well-defined, the other bits of the table word
are transferred to the lower portion of TBLH,
and the remaining 2 bits are read as "0". The
Table Higher-order byte register (TBLH) is
read only. The table pointer (TBLP) is a
read/write register (07H), which indicates the
table location. Before accessing the table, the
location must be placed in TBLP. The TBLH
is read only and cannot be restored. If the
main routine and the ISR (Interrupt Service
Routine) both employ the table read instruction, the contents of the TBLH in the main
routine are likely to be changed by the table
read instruction used in the ISR. Errors can
occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if
the table read instruction has to be applied in
both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. All table
related instructions require two cycles to complete the operation. These areas may function
as normal program memory depending upon
the requirements.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be
recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by
RET or RETI), the interrupt will be serviced.
This feature prevents stack overflow allowing
the programmer to use the structure more easily. In a similar case, if the stack is full and a
"CALL" is subsequently executed, stack overflow occurs and the first entry will be lost (only
the most recent 6 return addresses are stored).
Data memory - RAM
The data memory is designed with 85´8 bits.
The data memory is divided into two functional groups: special function registers and
general purpose data memory (64´8). Most are
read/write, but some are read only.
The special function registers include the indirect addressing register (00H), timer/event
counter (TMR;0DH), timer/event counter control register (TMRC;0EH), program counter
lower-order byte register (PCL;06H), memory
pointer register (MP;01H), accumulator
(ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status
register (STATUS;0AH), interrupt control register (INTC;0BH), PWM data register
(PWM;1AH), the A/D result lower-order byte
register (ADRL;20H), the A/D result
higher-order byte register (ADRH;21H), the
A/D control register (ADCR;22H), the A/D
Stack register - STACK
This is a special part of the memory which is
used to save the contents of the program counter (PC) only. The stack is organized into 6 levels and is neither part of the data nor part of the
program space, and is neither readable nor
writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledgment, the contents of the program
counter are pushed onto the stack. At the end of
Instruction
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *10~*0: Table location bits
P10~P8: Current program counter bits
@7~@0: Table pointer bits
Rev. 1.40
8
July 18, 2001
HT46R47
All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate
operations directly. Except for some dedicated
bits, each bit in the data memory can be set and
reset by "SET [m].i" and "CLR [m].i". They are
also indirectly accessible through memory
pointer register (MP;01H).
clock setting register (ACSR;23H), I/O registers (PA;12H, PB;14H, PD;18H) and I/O control registers (PAC;13H, PBC;15H, PDC;19H).
The remaining space before the 40H is reserved for future expanded usage and reading
these locations will get "00H". The general
purpose data memory, addressed from 40H to
7FH, is used for data and control information
under instruction commands.
0 0 H
In d ir e c t A d d r e s s in g R e g is te r
0 1 H
M P
Indirect addressing register
Location 00H is an indirect addressing register
that is not physically implemented. Any
read/write operation of [00H] accesses data memory pointed to by MP (01H). Reading location 00H
itself indirectly will return the result 00H. Writing indirectly results in no operation.
0 2 H
0 3 H
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
The memory pointer register MP (01H) is a 7-bit
register. The bit 7 of MP is undefined and reading
will return the result ²1². Any writing operation to
MP will only transfer the lower 7-bit data to MP.
0 9 H
0 A H
S T A T U S
0 B H
IN T C
S p e c ia l P u r p o s e
D A T A M E M O R Y
0 C H
0 D H
T M R
0 E H
T M R C
Accumulator
The accumulator is closely related to ALU operations. It is also mapped to location 05H of the
data memory and can carry out immediate data
operations. The data movement between two
data memory locations must pass through the
accumulator.
0 F H
1 0 H
1 1 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
Arithmetic and logic unit - ALU
1 6 H
1 7 H
1 8 H
This circuit performs 8-bit arithmetic and logic
operations. The ALU provides the following functions:
P D
1 9 H
P D C
: U n u s e d
1 A H
1 B H
P W M
R e a d a s "0 0 "
· Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
1 C H
1 D H
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
1 E H
1 F H
2 0 H
A D R L
2 1 H
A D R H
2 2 H
2 3 H
2 4 H
A D C R
3 F H
4 0 H
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but also changes the status register.
A C S R
Status register - STATUS
G e n e ra l P u rp o s e
D A T A M E M O R Y
(6 4 B y te s )
This 8-bit register (0AH) contains the zero flag
(Z), carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PD), and
watchdog time-out flag (TO). It also records the
7 F H
RAM mapping
Rev. 1.40
9
July 18, 2001
HT46R47
ternal timer/event counter interrupt and A/D
converter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt
control bits to set the enable/disable and the interrupt request flags.
status information and controls the operation
sequence.
With the exception of the TO and PD flags,
bits in the status register can be altered by
instructions like most other registers. Any
data written into the status register will not
change the TO or PD flag. In addition operations related to the status register may give
different results from those intended. The
TO flag can be affected only by system
power-up, a WDT time-out or executing the
"CLR WDT" or "HALT" instruction. The PD
flag can be affected only by executing the
"HALT" or "CLR WDT" instruction or a system power-up.
Once an interrupt subroutine is serviced, all
the other interrupts will be blocked (by clearing
the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a
certain interrupt requires servicing within the
service routine, the EMI bit and the corresponding bit of INTC may be set to allow interrupt
nesting. If the stack is full, the interrupt request
will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack must
be prevented from becoming full.
The Z, OV, AC and C flags generally reflect the
status of the latest operations.
In addition, on entering the interrupt sequence
or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are
important and if the subroutine can corrupt the
status register, precautions must be taken to
save it properly.
All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control
transfer occurs by pushing the program counter
onto the stack, followed by a branch to a subroutine at specified location in the program
memory. Only the program counter is pushed
onto the stack. If the contents of the register or
status register (STATUS) are altered by the interrupt service program which corrupts the de-
Interrupt
The device provides an external interrupt, inLabels
Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or no
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared by system power-up or executing the "CLR WDT" instruction. PD
is set by executing the "HALT" instruction.
TO
5
TO is cleared by system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out.
¾
6, 7
Unused bit, read as "0"
Status register
Rev. 1.40
10
July 18, 2001
HT46R47
cleared to disable further interrupts.
sired control sequence, the contents should be
saved in advance.
During the execution of an interrupt subroutine,
other interrupt acknowledgments are held until
the "RETI" instruction is executed or the EMI
bit and the related interrupt control bit are set to
1 (of course, if the stack is not full). To return
from the interrupt subroutine, "RET" or "RETI"
may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
External interrupts are triggered by a high to
low transition of INT and the related interrupt
request flag (EIF; bit 4 of INTC) will be set.
When the interrupt is enabled, the stack is not
full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be
cleared to disable other interrupts.
Interrupts, occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the
following table shows the priority that is applied. These can be masked by resetting the
EMI bit.
The internal timer/event counter interrupt is
initialized by setting the timer/event counter
interrupt request flag (TF; bit 5 of INTC),
caused by a timer overflow. When the interrupt
is enabled, the stack is not full and the TF bit is
set, a subroutine call to location 08H will occur.
The related interrupt request flag (TF) will be
reset and the EMI bit cleared to disable further
interrupts.
No. Interrupt Source Priority Vector
The A/D converter interrupt is initialized by
setting the A/D converter request flag (ADF; bit
6 of INTC), caused by an end of A/D conversion.
When the interrupt is enabled, the stack is not
full and the ADF is set, a subroutine call to location 0CH will occur. The related interrupt request flag (ADF) will be reset and the EMI bit
Register
INTC
(0BH)
Bit No.
a
External Interrupt
1
04H
b
Timer/event
Counter Overflow
2
08H
c
A/D Converter
Interrupt
3
0CH
The timer/event counter interrupt request flag
(TF), external interrupt request flag (EIF), A/D
Label
Function
0
EMI
Controls the master (global) interrupt
(1= enabled; 0= disabled)
1
EEI
Controls the external interrupt
(1= enabled; 0= disabled)
2
ETI
Controls the timer/event counter interrupt
(1= enabled; 0= disabled)
3
EADI
4
EIF
External interrupt request flag
(1= active; 0= inactive)
5
TF
Internal timer/event counter request flag
(1= active; 0= inactive)
6
ADF
7
¾
Controls the A/D converter interrupt
(1= enabled; 0= disabled)
A/D converter request flag
(1= active; 0= inactive)
Unused bit, read as "0"
INTC register
Rev. 1.40
11
July 18, 2001
HT46R47
mode stops the system oscillator and ignores an
external signal to conserve power.
c o n v e r t er r eq ues t f l a g ( AD F ) , e n a b l e
timer/event counter bit (ETI), enable external
interrupt bit (EEI), enable A/D converter interrupt bit (EADI) and enable master interrupt bit
(EMI) constitute an interrupt control register
(INTC) which is located at 0BH in the data
memory. EMI, EEI, ETI, EADI are used to control the enabling/disabling of interrupts. These
bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (TF,
EIF, ADF) are set, they will remain in the INTC
register until the interrupts are serviced or
cleared by a software instruction.
If an RC oscillator is used, an external resistor
between OSC1 and VSS is required and the resistance must range from 30kW to 750kW. The
system clock, divided by 4, is available on
OSC2, which can be used to synchronize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency
of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing
sensitive operations where an accurate oscillator frequency is desired.
It is recommended that a program does not
use the "CALL subroutine" within the interrupt subroutine. Interrupts often occur in an
unpredictable manner or need to be serviced
immediately in some applications. If only one
stack is left and enabling the interrupt is not
well controlled, the original control sequence will
be damaged once the "CALL" operates in the interrupt subroutine.
If the Crystal oscillator is used, a crystal across
OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator,
and no other external components are required.
Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors
in OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz).
Oscillator configuration
The WDT oscillator is a free running on-chip RC
oscillator, and no external components are required. Even if the system enters the power down
mode, the system clock is stopped, but the WDT
oscillator still works with a period of approximately 72ms/5V. The WDT oscillator can be disabled by ROM code option to conserve power.
There are two oscillator circuits in the
microcontroller.
O S C 1
O S C 1
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
N M O S O p e n D r a in
O S C 2
R C
Watchdog Timer - WDT
O s c illa to r
The clock source of WDT is implemented by a
dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by ROM code option. This timer is
designed to prevent a software malfunction or
sequence from jumping to an unknown location
with unpredictable results. The Watchdog
System oscillator
Both are designed for system clocks, namely
the RC oscillator and the Crystal oscillator,
which are determined by the ROM code option.
No matter what oscillator type is selected, the
signal provides the system clock. The HALT
S y s te m
C lo c k /4
W D T
O S C
R O M
C o d e
O p tio n
S e le c t
fs
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
T
T
W D T T im e - o u t
1 5
1 6
fs/2 ~ fs/2
C L R
W D T
Watchdog Timer
Rev. 1.40
12
July 18, 2001
HT46R47
Timer can be disabled by a ROM code option. If
the Watchdog Timer is disabled, all the executions related to the WDT result in no operation.
· The contents of the on chip RAM and regis-
ters remain unchanged.
· WDT will be cleared and recounted again (if
the WDT clock is from the WDT oscillator).
Once the internal oscillator (RC oscillator with
a period of 72ms/5V normally) is selected, it is
first divided by 256 (8-stage) to get the nominal
time-out period of approximately 18.6ms/5V.
This time-out period may vary with temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can
be realized and the maximum time-out period
is 2.3s/5V~4.7s/5V seconds. If the WDT oscillator is disabled, the WDT clock may still come
from the instruction clock and operate in the
same manner except that in the HALT state the
WDT may stop counting and lose its protecting
purpose. In this situation the logic can only be
restarted by external logic.
· All of the I/O ports maintain their original sta-
tus.
· The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means
of an external reset, an interrupt, an external
falling edge signal on port A or a WDT overflow.
An external reset causes a device initialization
and the WDT overflow performs a ²warm reset². After the TO and PD flags are examined,
the reason for chip reset can be determined.
The PD flag is cleared by system power-up or
executing the ²CLR WDT² instruction and is
set when executing the ²HALT² instruction.
The TO flag is set if the WDT time-out occurs,
and causes a wake-up that only resets the PC
and SP; the others keep their original status.
If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is
strongly recommended, since the HALT will stop
the system clock.
The port A wake-up and interrupt methods can
be considered as a continuation of normal execution. Each bit in port A can be independently
selected to wake up the device by the ROM code
option. Awakening from an I/O port stimulus,
the program will resume execution of the next
instruction. If it is awakening from an interrupt, two sequences may happen. If the related
interrupt is disabled or the interrupt is enabled
but the stack is full, the program will resume
execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an
interrupt request flag is set to ²1² before entering the HALT mode, the wake-up function of
the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation.
In other words, a dummy period will be inserted
after wake-up. If the wake-up results from an
interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the
next instruction execution, this will be executed
immediately after the dummy period is finished.
The WDT overflow under normal operation will
initialize ²chip reset² and set the status bit
²TO². But in the HALT mode, the overflow will
initialize a ²warm reset², and only the PC and
SP are reset to zero. To clear the contents of
WDT, three methods are adopted; external reset (a low level to RES), software instruction
and a "HALT" instruction. The software instruction include ²CLR WDT² and the other set
- ²CLR WDT1² and ²CLR WDT2². Of these two
types of instruction, only one can be active depending on the ROM code option - ²CLR WDT
times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times equal one), any execution of the ²CLR WDT² instruction will clear
the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. CLRWDT times
equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out.
Power down operation - HALT
The HALT mode is initialized by the ²HALT²
instruction and results in the following...
· The system oscillator will be turned off but
To minimize power consumption, all the I/O
pins should be carefully managed before entering the HALT status.
the WDT oscillator keeps running (if the
WDT oscillator is selected).
Rev. 1.40
13
July 18, 2001
HT46R47
Reset
V
D D
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
R E S
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a ²warm reset² that resets only the PC
and SP, leaving the other circuits in their original state. Some registers remain unchanged
during other reset conditions. Most registers
are reset to the ²initial condition² when the reset conditions are met. By examining the PD
and TO flags, the program can distinguish between different ²chip resets².
TO PD
Reset circuit
H A L T
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
R e s e t
W D T
R E S
RESET Conditions
0
W a rm
O S C 1
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
Reset configuration
The functional unit chip reset status are shown
below.
Note: ²u² means ²unchanged²
To guarantee that the system oscillator is
started and stabilized, the SST (System
Start-up Timer) provides an extra-delay of
1024 system clock pulses when the system reset
(power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
PC
000H
Interrupt
Disable
WDT
Clear. After master reset,
WDT begins counting
Timer/Event
Off
Counter
Input/output
Input mode
Ports
When a system reset occurs, the SST delay is
added during the reset period. Any wake-up
from HALT will enable the SST delay.
SP
Points to the top of the
stack
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset timing chart
Rev. 1.40
14
July 18, 2001
HT46R47
The registers¢ states are summarized in the following table.
Reset
(Power On)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
000H
000H
000H
000H
000H
MP
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PBC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PD
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
PDC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
PWM
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRL
x--- ----
x--- ----
x--- ----
x--- ----
u--- ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --00
u---- --uu
Register
Program
Counter
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Rev. 1.40
15
July 18, 2001
HT46R47
Timer/Event Counter
measure time intervals or pulse widths, or to
generate an accurate time base.
A timer/event counter (TMR) is implemented in
the microcontroller. The timer/event counter
contains an 8-bit programmable count-up counter and the clock may come from an external
source or the system clock.
There are 2 registers related to the timer/event
counter; TMR ([0DH]), TMRC ([0EH]). Two physical registers are mapped to TMR location; writing TMR makes the starting value be placed in
the timer/event counter preload register and
reading TMR gets the contents of the timer/event
counter. The TMRC is a timer/event counter control register, which defines some options.
Using the internal system clock, there is only
one reference time-base. The internal clock
source comes from fSYS. The external clock input allows the user to count external events,
Label (TMRC)
PSC0~PSC2
Bits
0~2
Function
To define the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
TE
3
To define the TMR active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer counting
(0=disabled; 1=enabled)
5
Unused bit, read as ²0²
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
¾
TM0
TM1
TMRC register
P W M
(6 + 2 ) c o m p a re
fS
Y S
to P D 0 c ir c u it
8 - s ta g e p r e s c a le r
f IN
8 -1 M U X
P S C 2 ~ P S C 0
D a ta B u s
T
T M 1
T M 0
T M R
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T im e r /E v e n t
C o u n te r
O v e r flo w
to In te rru p t
1 /2
P F D
Timer/Event Counter
Rev. 1.40
16
July 18, 2001
HT46R47
counter is turned on, data written to it will only
be kept in the timer/event counter preload register. The timer/event counter will still operate
until overflow occurs. When the timer/event
counter (reading TMR) is read, the clock will be
blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into
consideration by the programmer.
The TM0, TM1 bits define the operating mode.
The event count mode is used to count external
events, which means the clock source comes from
an external (TMR) pin. The timer mode functions
as a normal timer with the clock source coming
from the fINT clock. The pulse width measurement
mode can be used to count the high or low level duration of the external signal (TMR). The counting
is based on the fINT.
The bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock
sources of timer/event counter. The definitions
are as shown. The overflow signal of
timer/event counter can be used to generate the
PFD signal. The timer prescaler is also used as
the PWM counter.
In the event count or timer mode, once the
timer/event counter starts counting, it will count
from the current contents in the timer/event
counter to FFH. Once overflow occurs, the counter is reloaded from the timer/event counter
preload register and generates the interrupt request flag (TF; bit 5 of INTC) at the same time.
Input/output ports
In the pulse width measurement mode with
the TON and TE bits equal to one, once the
TMR has received a transient from low to high
(or high to low if the TE bits is ²0²) it will start
counting until the TMR returns to the original
level and resets the TON. The measured result
will remain in the timer/event counter even if
the activated transient occurs again. In other
words, only one cycle measurement can be
done. Until setting the TON, the cycle measurement will function again as long as it receives
further transient pulse. Note that, in this operating mode, the timer/event counter starts
counting not according to the logic level but according to the transient edges. In the case of
counter overflows, the counter is reloaded from
the timer/event counter preload register and issues the interrupt request just like the other
two modes. To enable the counting operation,
the timer ON bit (TON; bit 4 of TMRC) should
be set to 1. In the pulse width measurement
mode, the TON will be cleared automatically after the measurement cycle is completed. But in
the other two modes the TON can only be reset
by instructions. The overflow of the timer/event
counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to
ETI can disable the interrupt service.
There are 13 bidirectional input/output lines in
the microcontroller, labeled as PA, PB and PD,
which are mapped to the data memory of [12H],
[14H] and [18H] respectively. All of these I/O
ports can be used for input and output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at
the T2 rising edge of instruction ²MOV A,[m]²
(m=12H, 14H or 18H). For output operation, all
the data is latched and remains unchanged until
the output latch is rewritten.
Each I/O line has its own control register (PAC,
PBC, PDC) to control the input/output configuration. With this control register, CMOS output
or Schmitt trigger input with or without
pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the
corresponding latch of the control register must
write ²1². The input source also depends on the
control register. If the control register bit is ²1²,
the input will read the pad state. If the control
register bit is ²0², the contents of the latches
will move to the internal bus. The latter is possible in the ²read-modify-write² instruction.
For output function, CMOS is the only configuration. These control registers are mapped to
locations 13H, 15H and 19H.
In the case of timer/event counter OFF condition, writing data to the timer/event counter
preload register will also reload that data to
the timer/event counter. But if the timer/event
Rev. 1.40
After a chip reset, these input/output lines remain at high levels or floating state (dependent
17
July 18, 2001
HT46R47
erated by timer/event counter overflow signal.
The input mode always remaining its original
functions. Once the PFD option is selected, the
PFD output signal is controlled by PA3 data
register only. Writing ²1² to PA3 data register
will enable the PFD output function and writing ²0² will force the PA3 to remain at ²0². The
I/O functions of PA3 are shown below.
on pull-high options). Each bit of these input/output latches can be set or cleared by ²SET
[m].i² and ²CLR [m].i² (m=12H, 14H or 18H) instructions.
Some instructions first input data and then follow the output operations. For example, ²SET
[m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or the accumulator.
I/O
I/P
O/P
I/P
Mode (Normal) (Normal) (PFD)
Logical
Input
PA3
Each line of port A has the capability of waking-up the device. The highest 4-bit of port B and
7 bits of port D are not physically implemented;
on reading them a ²0² is returned whereas writing then results in a no-operation. See Application note.
Note:
The PFD frequency is the timer/event
counter overflow frequency divided by 2.
The PB can also be used as A/D converter inputs. The A/D function will be described later.
There is a PWM function shared with PD0. If
the PWM function is enabled, the PWM signal
will appear on PD0 (if PD0 is operating in output mode). The I/O functions of PD0 are as
shown.
The PA3 is pin-shared with the PFD signal. If
the PFD option is selected, the output signal in
output mode of PA3 will be the PFD signal gen-
V
Q
D
D a ta B u s
W r ite C o n tr o l R e g is te r
C K
C h ip R e s e t
R e a d C o n tr o l R e g is te r
C K
(P D 0 o r P W M )
Q B
S
P A 0
P A 3
P A 4
P A 5
P A 6
P B 0
P D 0
S y s te m W a k e -u p
( P A o n ly )
~ P
/P
/T
/IN
, P
/A
/P
A 2
F D
M R
T
A 7
N 0 ~ P B 3 /A N 3
W M
Q B
S
M
P A 3
P F D
M
R e a d D a ta R e g is te r
D D
P U
D a ta B it
Q
D
W r ite D a ta R e g is te r
Logical Logical
PFD
Output Input (Timer on)
The PA5 and PA4 are pin-shared with INT and
TMR pins respectively.
Each I/O line has a pull-high option. Once the
pull-high option is selected, the I/O line has a
pull-high resistor, otherwise, there¢s none.
Take note that a non-pull-high I/O line operating in input mode will cause a floating state.
C o n tr o l B it
O/P
(PFD)
U
U
X
P F D E N
(P A 3 )
X
O P 0 ~ O P 7
IN T fo r P A 5 O n ly
T M R fo r P A 4 O n ly
Input/output ports
Rev. 1.40
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July 18, 2001
HT46R47
In a PWM cycle, the duty cycle of each modulation cycle is shown in the table.
I/O
I/P
O/P
I/P
O/P
Mode (Normal) (Normal) (PWM) (PWM)
Logical
Input
PD0
Logical
Output
Logical
Input
Parameter
PWM
It is recommended that unused or not bonded
out I/O lines should be set as output pins by
software instruction to avoid consuming power
under input floating state.
Modulation cycle i
(i=0~3)
The microcontroller provides 1 channel (6+2)
bits PWM output shared with PD0. The PWM
channel has its data register denoted as PWM
(1AH). The frequency source of the PWM counter comes from fSYS. The PWM register is an
eight bits register. The waveforms of PWM output are as shown. Once the PD0 is selected as
the PWM output and the output function of
PD0 is enabled (PDC.0=²0²), writing 1 to PD0
data register will enable the PWM output function and writing ²0² will force the PD0 to stay
at ²0².
DC + 1
64
i³AC
DC
64
PWM
Modulation
Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
fSYS/64
fSYS/256
[PWM]/256
A/D converter
The 4 channels and 9-bit resolution A/D (8-bit
accuracy) converter are implemented in this
microcontroller. The reference voltage is VDD.
The A/D converter contains 4 special registers
which are; ADRL (20H), ADRH (21H), ADCR
(22H) and ACSR (23H). The ADRH and ADRL
are A/D result register higher-order byte and
lower-order byte and are read-only. After the
A/D conversion is completed, the ADRH and
ADRL should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel
number, analog channel select, start A/D con-
A PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock
period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two
groups. Group 1 of the PWM register is denoted
by DC which is the value of PWM.7~PWM.2.
The group 2 is denoted by AC which is the value
of PWM.1~PWM.0.
Y S
i<AC
The modulation frequency, cycle frequency and
cycle duty of the PWM output signal are summarized in the following table.
PWM
fS
AC (0~3) Duty Cycle
/2
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
Y S
P W M
c y c le : 2 5 6 /fS
Y S
PWM
Rev. 1.40
19
July 18, 2001
HT46R47
PB line is selected as an analog input, the I/O
functions and pull-high resistor of this I/O line
are disabled, and the A/D converter circuit is
power on. The EOC bit (bit6 of the ADCR) is
end of A/D conversion flag. Check this bit to
know when A/D conversion is completed. The
START bit of the ADCR is used to begin the
conversion of A/D converter. Give START bit a
raising edge and falling edge that means the
A/D conversion has started. In order to ensure
the A/D conversion is completed, the START
should stay at ²0² until the EOC is cleared to
²0² (end of A/D conversion).
version control bit and the end of A/D conversion flag. If the users want to start an A/D
conversion, define PB configuration, select the
converted analog channel, and give START bit
a raising edge and a falling edge (0®1®0). At
the end of A/D conversion, the EOC bit is
cleared and an A/D converter interrupt occurs
(if the A/D converter interrupt is enabled). The
ACSR is A/D clock setting register, which is
used to select the A/D clock source.
The A/D converter control register is used to
control the A/D converter. The bit2~bit0 of the
ADCR are used to select an analog input channel. There are a total of four channels to select.
The bit5~bit3 of the ADCR are used to set PB
configurations. PB can be an analog input or as
digital I/O line decided by these 3 bits. Once a
Label (ADCR)
The bit 7 of the ACSR is used for testing purpose only. It can not be used for the users. The
bit1 and bit0 of the ACSR are used to select A/D
clock sources.
Bits
Function
0
1
2
ACS2, ACS1, ACS0: Select A/D channel
0, 0, 0: AN0
0, 0, 1: AN1
0, 1, 0: AN2
0, 1, 1: AN3
1, X, X: undefined, cannot be used
PCR0
PCR1
PCR2
3
4
5
PCR2, PCR1, PCR0: PB3~PB0 configurations
0, 0, 0: PB3 PB2 PB1 PB0 (The ADC circuit is power off to reduce
power consumption.)
0, 0, 1: PB3 PB2 PB1 AN0
0, 1, 0: PB3 PB2 AN1 AN0
0, 1, 1: PB3 AN2 AN1 AN0
1, x, x: AN3 AN2 AN1 AN0
EOC
6
End of A/D conversion flag.
(0: end of A/D conversion)
START
7
Start the A/D conversion
0®1®0: Start
0®1: Reset A/D converter and set EOC to ²1²
ACS0
ACS1
ACS2
Bits
ADCS0
ADCS1
0
1
¾
2~6
TEST
7
Rev. 1.40
Function
ADCS1, ADCS0: Select the A/D converter clock source.
0, 0: fSYS/2
0, 1: fSYS/8
1, 0: fSYS/32
1, 1: Undefined, cannot be used.
Unused bit, read as ²0².
For internal test only.
20
July 18, 2001
HT46R47
· The LVR uses the ²OR² function with the exter-
When the A/D conversion is completed, the A/D
interrupt request flag is set. The EOC bit is set
to ²1² when the START bit is set from ²0² to ²1².
nal RES signal to perform chip reset.
The relationship between VDD and VLVR is
shown below.
Bit Bit Bit Bit Bit Bit Bit Bit
Register
7 6 5 4 3 2 1 0
ADRL
D0 ¾
ADRH
D8 D7 D6 D5 D4 D3 D2 D1
¾
¾
¾
¾
¾
V D D
5 .5 V
¾
V
O P R
5 .5 V
* D0~D8 is A/D conversion result data bit
LSB~MSB.
V
L V R
3 .3 V
Low voltage reset - LVR
3 .0 V
The microcontroller provides low voltage reset
circuit in order to monitor the supply voltage of
the device. If the supply voltage of the device is
within the range 0.9V~3.3V, such as changing a
battery, the LVR will automatically reset the
device internally.
0 .9 V
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
The LVR includes the following specifications:
· The low voltage (0.9V~3.3V) has to remain in
their original state to exceed 1ms. If the low
voltage state does not exceed 1ms, the LVR
will ignore it and do not perform a reset function.
S T A R T
E O C
*7 6 T A D
P C R 0 ~ P C R 2
A C S 0 ~ A C S 2
1 0 0 B
1 0 0 B
0 0 0 B
0 0 0 B
0 1 0 B
0 0 0 B
**X X X B
P o w e r
O n
R e s e t
1 : D
2 : S
***3
(E x
fS Y
N o te :
Rev. 1.40
*7 6 T A D
0 0 0 B
e fin
e le c
: S e
a m p
S /8 )
e P
t a
le c
le :
B c o n fig u
n a lo g c h a
t A D C c lo
4 c h a n n e
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
r a tio n
n n e l
c k
l, A N 2 ,
" * " A /D c o n v e r tin g tim e is 7 6 T A D
" * * " X X X B m e a n s d o n 't c a r e
" * * * " A D C c lo c k m u s t b e fS Y S /2 , fS
Y S
/8 , fS
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e rte r
Y S
1 : A ll P B lin e is d ig ita l in p u t
2 : A /D c o n v e r te r is p o w e r o ff
to r e d u c e p o w e r c o n s u m p tio n
E n d o f A /D
c o n v e rte r
/3 2
21
July 18, 2001
HT46R47
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low voltage reset
Note:
*1:To make sure that the system oscillator has stabilized, the SST provides an extra delay of
1024 system clock pulses before entering the normal operation.
*2:Since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms
delay enter the reset mode.
ROM code option
The following table shows all kinds of ROM code option in the microcontroller. All of the ROM code
options must be defined to ensure proper system functioning.
Items
Option
1
WDT clock source: WDTOSC/fTID
2
WDT enable/disable: enable/disable
3
CLRWDT instruction(s)
: one/two clear WDT
instruction(s)
4
System oscillator: RC/Crystal
5
Pull-high resistors (PA, PB, PD):
none/pull-high
6
PWM enable/disable
7
PA0~PA7 wake-up: disable/enable
8
PFD enable/disable
9
Lock: unlock/lock
10
Low voltage reset selection: Enable or disable LVR function.
Rev. 1.40
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July 18, 2001
HT46R47
Application Circuits
Battery charger for 1-set battery charger applications
O S C 1
O S C
C ir c u it
P A 3 /P F D
P A 4 /T M R
O S C 2
S e e b e lo w
P A 5 /IN T
P A 6 , P A 7
H T 4 6 R 4 7
5 V
V D D
1 0 0 k W
0 .1 m F
1 2 V
P A 0 , P A 1
5 V
P D 0 /P W M
V
P B 0 /A N 0
R E S
R t
V b a t
P B 1 /A N 1
0 .1 m F
V S S
P A 2
If
P B 2 /A N 2
P B 3 /A N 3
N o te : T h e r e s is ta n c e a n d c a p a c ita n c e fo r r e s e t c ir c u it s h o u ld b e d e s ig n e d
to e n s u r e th a t th e V D D is s ta b le a n d r e m a in s in a v a lid r a n g e o f th e
o p e r a tin g v o lta g e b e fo r e b r in g in g R E S to h ig h .
V b a t: 3 .6 V ( N iC d , N iM H ) o r 4 .1 V ( L i+ )
Rev. 1.40
23
July 18, 2001
HT46R47
Battery charger for 2-set battery charger applications
1 2 V
P A 0
O S C 1
P A 3 /P F D
O S C
C ir c u it
P A 4 /T M R
O S C 2
P A 5 /IN T
S e e b e lo w
P D 0 /P W M
5 V
V D D
H T 4 6 R 4 7
1 0 0 k W
0 .1 m F
P A 6
R E S
0 .1 m F
P A 7
V S S
C H 0
C H 1
V b a t0
P B 0 /A N 0
V b a t1
P B 1 /A N 1
P B 3 /A N 3
P A 1
P A 2
P B 2 /A N 2
V
If
D D
2 7 0 p F
R
O S C
O S C 1
fS
Y S /4
R C s y s te m o s c illa to r
3 0 k W < R O S C < 7 5 0 k W
O S C 2
O S C 1
C 1
C 2
O S C 2
C r y s ta l s y s te m o s c illa to r
C 1 = C 2 = 3 0 0 p F , if fS Y S < 1 M H z
O th e r w is e , C 1 = C 2 = 0
V b a t0 , V b a t1 : 3 .6 V ( N iC d , N iM H ) o r 4 .1 V ( L i+ )
Rev. 1.40
24
July 18, 2001
HT46R47
Instruction Set Summary
Mnemonic
Description
Instruction
Cycle
Flag
Affected
1
1(1)
1
1
1(1)
1
1
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
1
1(1)
Z,C,AC,OV
Z,C,AC,OV
1(1)
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1(1)
1
1(1)
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to register with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data
memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result
in data memory
Decimal adjust ACC for addition with result in data
memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.40
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
25
July 18, 2001
HT46R47
Instruction
Cycle
Flag
Affected
1
1(1)
1
None
None
C
1(1)
1
1(1)
1
C
None
None
C
1(1)
C
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement
ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result
ACC
Skip if decrement data memory is zero with result
ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data
ACC
Return from interrupt
to
2
1(2)
1(2)
None
None
None
in
1(2)
1(2)
1(3)
1(3)
1(2)
None
None
None
None
None
in
1(2)
None
to
2
2
2
None
None
None
2
None
Mnemonic
Description
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in
ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in
ACC
Rotate data memory left through carry
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Rev. 1.40
26
July 18, 2001
HT46R47
Mnemonic
Description
Instruction
Cycle
Flag
Affected
2(1)
None
2(1)
None
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PD
TO(4),PD(4)
TO(4),PD(4)
None
None
TO,PD
Table Read
TABRDC [m] Read ROM code (current page) to data memory and
TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
x: 8 bits immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed
for one more cycle (four system clocks).
(2)
: If a skipping to next instruction occurs, the execution cycle of instructions will be delayed
one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.40
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by
executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared.
Otherwise the TO and PD flags remain unchanged.
27
July 18, 2001
HT46R47
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator.
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory.
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator.
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator.
Description
The contents of the accumulator and the specified data are added, leaving
the result in the accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
28
July 18, 2001
HT46R47
ADDM A,[m]
Add the accumulator to the data memory.
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
AND A,[m]
Logical AND accumulator with data memory.
Description
Data in the accumulator and the specified data memory perform a bitwise
logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC "AND" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator.
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC "AND" x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator.
Description
Data in the specified data memory and the accumulator perform a bitwise
logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC "AND" [m]
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
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July 18, 2001
HT46R47
CALL addr
Subroutine call.
Description
The instruction unconditionally calls a subroutine located at the indicated
address. The program counter increments once to obtain the address of the
next instruction, and pushes this onto the stack. The indicated address is
then loaded. Program execution continues with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory.
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m].i
Clear bit of data memory.
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer.
Description
The WDT and the WDT Prescaler are cleared (re-counting from 0). The
power down bit (PD) and time-out bit (TO) are cleared.
Operation
WDT and WDT Prescaler ¬ 00H
PD and TO ¬ 0
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
0
¾
¾
¾
¾
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July 18, 2001
HT46R47
CLR WDT1
Preclear Watchdog Timer.
Description
The TO, PD flags, WDT and the WDT Prescaler has cleared (re-counting
from 0), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction just sets the
indicated flag which implies this instruction has been executed and the TO
and PD flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer.
Description
The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting
from 0), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and
PD flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory.
Description
Each bit of the specified data memory is logically complemented (1's complement). Bits which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
31
July 18, 2001
HT46R47
CPLA [m]
Complement data memory and place result in the accumulator.
Description
Each bit of the specified data memory is logically complemented (1's complement). Bits which previously contained a 1 are changed to 0 and vice-versa.
The complemented result is stored in the accumulator and the contents of
the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition.
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code.
The accumulator is divided into two nibbles. Each nibble is adjusted to the
BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the
original value if the original value is greater than 9 or a carry (AC or C) is set;
otherwise the original value remains unchanged. The result is stored in the
data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory.
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
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HT46R47
DECA [m]
Decrement data memory and place result in the accumulator.
Description
Data in the specified data memory is decremented by 1, leaving the result in
the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
HALT
Enter power down mode.
Description
This instruction stops program execution and turns off the system clock. The
contents of the RAM and registers are retained. The WDT and prescaler are
cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is
cleared.
Operation
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
INC [m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
1
¾
¾
¾
¾
Increment data memory.
Description
Data in the specified data memory is incremented by 1.
Operation
[m] ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator.
Description
Data in the specified data memory is incremented by 1, leaving the result in
the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
33
July 18, 2001
HT46R47
JMP addr
Directly jump.
Description
Bits of the program counter are replaced with the directly-specified address
unconditionally, and control is passed to this destination.
Operation
PC ¬ addr
Affected flag(s)
MOV A,[m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Move data memory to the accumulator.
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,x
Move immediate data to the accumulator.
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory.
Description
The contents of the accumulator are copied to the specified data memory (one
of the data memory).
Operation
[m] ¬ ACC
Affected flag(s)
NOP
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
No operation.
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
34
July 18, 2001
HT46R47
OR A,[m]
Logical OR accumulator with data memory.
Description
Data in the accumulator and the specified data memory (one of the data
memory) perform a bitwise logical_OR operation. The result is stored in the
accumulator.
Operation
ACC ¬ ACC "OR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator.
Description
Data in the accumulator and the specified data perform a bitwise logical_OR
operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC "OR" x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator.
Description
Data in the data memory (one of the data memory) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ ACC "OR" [m]
Affected flag(s)
RET
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
Return from subroutine.
Description
The program counter is restored from the stack. This is a 2 cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
35
July 18, 2001
HT46R47
RET A,x
Return and place immediate data in the accumulator.
Description
The program counter is restored from the stack and the accumulator loaded
with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt.
Description
The program counter is restored from the stack, and interrupts are enabled
by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0;
register INTC).
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left.
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator.
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into
bit 0, leaving the rotated result in the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
36
July 18, 2001
HT46R47
RLC [m]
Rotate data memory left through carry.
Description
The contents of the specified data memory and the carry flag are rotated 1 bit
left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0
position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator.
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit
7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the
data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right.
Description
The contents of the specified data memory are rotated 1 bit right with bit 0
rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
37
July 18, 2001
HT46R47
RRA [m]
Rotate right and place result in the accumulator.
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into
bit 7, leaving the rotated result in the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry.
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated
into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RRCA [m]
Rotate right through carry and place result in the accumulator.
Description
Data of the specified data memory and the carry flag are rotated 1 bit right.
Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7
position. The rotated result is stored in the accumulator. The contents of the
data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
38
July 18, 2001
HT46R47
SBC A,[m]
Subtract data memory and carry from the accumulator.
Description
The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator.
Description
The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the data
memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0.
Description
The contents of the specified data memory are decremented by 1. If the result
is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0.
Description
The contents of the specified data memory are decremented by 1. If the result
is 0, the next instruction is skipped. The result is stored in the accumulator
but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and
a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
39
July 18, 2001
HT46R47
SET [m]
Set data memory.
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m].i
Set bit of data memory.
Description
Bit ²i² of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0.
Description
The contents of the specified data memory are incremented by 1. If the result
is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction
(2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0.
Description
The contents of the specified data memory are incremented by 1. If the result
is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and
a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
40
July 18, 2001
HT46R47
SNZ [m].i
Skip if bit ²i² of the data memory is not 0.
Description
If bit ²i² of the specified data memory is not 0, the next instruction is skipped.
If bit ²i² of the data memory is not 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the
next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SUB A,[m]
Subtract data memory from the accumulator.
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator.
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator.
Description
The immediate data specified by the code is subtracted from the contents of
the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
41
July 18, 2001
HT46R47
SWAP [m]
Swap nibbles within the data memory.
Description
The low-order and high-order nibbles of the specified data memory (one of
the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator.
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m]
Skip if data memory is 0.
Description
If the contents of the specified data memory are 0, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0.
Description
The contents of the specified data memory are copied to the accumulator. If
the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1
cycle).
Operation
Skip if [m]=0, ACC ¬ [m]
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
42
July 18, 2001
HT46R47
SZ [m].i
Skip if bit ²i² of the data memory is 0.
Description
If bit ²i² of the specified data memory is 0, the following instruction, fetched
during the current instruction execution, is discarded and a dummy cycle is
replaced to get the proper instruction (2 cycles). Otherwise proceed with the
next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory.
Description
The low byte of ROM code (current page) addressed by the table pointer
(TBLP) is moved to the specified data memory and the high byte transferred
to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory.
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP)
is moved to the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
XOR A,[m]
Logical XOR accumulator with data memory.
Description
Data in the accumulator and the indicated data memory perform a bitwise
logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC "XOR" [m]
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
43
July 18, 2001
HT46R47
XORM A,[m]
Logical XOR data memory with the accumulator.
Description
Data in the indicated data memory and the accumulator perform a bitwise
logical Exclusive_OR operation. The result is stored in the data memory. The
0 flag is affected.
Operation
[m] ¬ ACC "XOR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator.
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is
affected.
Operation
ACC ¬ ACC "XOR" x
Affected flag(s)
Rev. 1.40
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
44
July 18, 2001
HT46R47
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holtek Semiconductor (Shanghai) Ltd.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
Holmate Technology Corp.
48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539
Tel: 510-252-9880
Fax: 510-252-9885
Copyright Ó 2001 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.40
45
July 18, 2001