HOLTEK HT48CA5

HT48RA5/HT48CA5
Remote Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
- HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
- HA0041E Using the HT48CA0 to Generate the HT6221 Output Signals
- HA0075E MCU Reset and Oscillator Circuits Application Note
- HA0076E HT48RAx/HT48CAx Software Application Note
- HA0082E HT48xA0-1 and HT48xA0-2 Power-on Reset Timing
Features
· Operating voltage: 2.0V~5.5V
· HALT function and wake-up feature reduce power
consumption
· 23 bidirectional I/O lines (max.)
· 1 interrupt input shared with an I/O line
· 8-level subroutine nesting
· 8-bit programmable timer/event counter with
· Up to 1ms instruction cycle with 4MHz system clock at
VDD=3V
overflow interrupt and 8-stage prescaler (TMR0)
· Bit manipulation instruction
· 16-bit programmable timer/event counter and
· 16-bit table read instruction
overflow interrupts (TMR1)
· On-chip crystal and RC oscillator
· 63 powerful instructions
· Watchdog Timer
· All instructions in one or two machine cycles
· 40K´16 program memory (8K´16 bits´5 banks)
· Low voltage reset function
· 224´8 data memory RAM
· 28-pin SOP/SSOP (209mil) package
· PFD supported
General Description
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, watchdog timer,
programmable frequency divider, HALT and wake-up
functions, as well as low cost, enhance the versatility of
these devices to suit a wide range of application possibilities such as industrial control, consumer products,
subsystem controllers, and particularly suitable for use
in products such as universal remote controller (URC).
The HT48RA5/HT48CA5 are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for multiple I/O control product applications.
The data ROM can be used to store remote control
codes. The mask version HT48CA5 is fully pin and functionally compatible with the OTP version HT48RA5 device.
Rev. 1.20
1
June 10, 2005
HT48RA5/HT48CA5
Block Diagram
T M R 1 C
P F 0 /IN T
M
T M R 1
fS
U
X
In te rru p t
C ir c u it
P ro g ra m
R O M
P ro g ra m
C o u n te r
S T A C K
IN T C
/4
P C 5 /T M R 1
M
T M R 0
Y S
U
P r e s c a le r
fS
Y S
P C 0 /T M R 0
X
T M R 0 C
B P
E N /D IS
In s tr u c tio n
R e g is te r
M
M P
U
W D T S
X
D A T A
M e m o ry
W D T P r e s c a le r
W D T
M
U
fS
Y S
/4
X
W D T O S C
P A C
M U X
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
O S C 1
P A 0 ~ P A 7
P F D
S T A T U S
P B C
S h ifte r
P O R T B
P B
P C C
O S C 2
P O R T A
P A
P O R T C
P C
A C C
R E S
V D D
V S S
P F C
P F
P O R T F
P B 0 /P F D
P B 1 ~ P B 7
P C 0 /T M R 0
P C 1 ~ P C 4
P C 5 /T M R 1
P F 0 /IN T
Pin Assignment
P B 5
1
2 8
P B 6
P B 4
2
2 7
P B 7
P A 3
3
2 6
P A 4
P A 2
4
2 5
P A 5
P A 1
5
2 4
P A 6
P A 0
6
2 3
P A 7
P B 3
7
2 2
O S C 2
P B 2
8
2 1
O S C 1
P B 1
9
2 0
V D D
P B 0 /P F D
1 0
1 9
R E S
V S S
1 1
1 8
P C 5 /T M R 1
P F 0 /IN T
1 2
1 7
P C 4
P C 0 /T M R 0
1 3
1 6
P C 3
P C 1
1 4
1 5
P C 2
H T 4 8 R A 5 /H T 4 8 C A 5
2 8 S O P -A /S S O P -A
Rev. 1.20
2
June 10, 2005
HT48RA5/HT48CA5
Pin Description
Pin Name
PA0~PA7
PB0/PFD
PB1~PB7
I/O
ROM Code
Option
Description
I/O
Wake-up*
Pull-high***
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by a option. Software instructions determine the CMOS output or Schmitt trigger input with/without pull-high resistor. The pull-high resistor of each input/output
line is also optional.
Pull-high**
PB0 or PFD
Bidirectional 8-bit input/output port. Software instructions determine the CMOS
output or Schmitt trigger input with/without pull-high resistor. The pull-high resistor of each input/output line is also optional. The output mode of PB0 can be
used as an internal PFD signal output and it can be used as a various frequency
carrier signal.
I/O
PC0/TMR0
PC1~PC4
PC5/TMR1
I/O
Pull-high*
Bidirectional 6-bit input/output port. Software instructions determine the CMOS
output or Schmitt trigger input with/without pull-high resistor. The pull-high resistor of each input/output line is also optional. PC0 and PC5 are pin shared with
TMR0 and TMR1 function pins.
PF0/INT
I/O
Pull-high*
Bidirectional 1-bit input/output port. Software instructions determine the CMOS
output or Schmitt trigger input with/without pull-high resistor. The pull-high resistor of this input/output line is also optional. PF0 is pin shared with the INT function pin.
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an RC network or Crystal (determined by option)
for the internal system clock. In the case of RC operation, OSC2 is the output
terminal for 1/4 system clock.
RES
I
¾
Schmitt trigger reset input, active low.
VSS
¾
¾
Negative power supply, ground
VDD
¾
¾
Positive power supply
Note:
* Bit option
** Nibble option
*** Byte option
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.20
3
June 10, 2005
HT48RA5/HT48CA5
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Operating Voltage
IDD1
Operating Current
VDD
Conditions
¾
¾
3V
No load, fSYS=4MHz
5V
IDD2
Operating Current
(Crystal OSC, RC OSC)
ISTB1
Standby Current (WDT Enabled and
WDT RC OSC On)
ISTB2
5V
No load, fSYS=8MHz
3V
No load, system HALT
5V
3V
Standby Current (WDT Disabled)
No load, system HALT
5V
Min.
Typ.
Max.
Unit
2.0
¾
5.5
V
¾
0.6
1.5
mA
¾
2
4
mA
¾
4
8
mA
¾
1.1
5
mA
¾
4
10
mA
¾
0.1
1
mA
¾
0.2
2
mA
VIL1
Input Low Voltage for I/O Ports
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
¾
LVR=2.0V
1.8
1.9
2.0
V
Low Voltage Reset
LVR=3.0V
2.7
3.0
3.3
V
IOL
4
8
¾
mA
I/O Port Sink Current
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
20
60
100
kW
10
30
50
kW
3V
VOL=0.1VDD
5V
IOH
3V
I/O Port Source Current
VOH=0.9VDD
5V
RPH
3V
¾
Pull-high Resistance
5V
Rev. 1.20
4
June 10, 2005
HT48RA5/HT48CA5
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
fSYS1
fSYS2
fTIMER
System Clock (Crystal OSC)
System Clock (RC OSC)
Typ.
Max.
Unit
¾
2.0V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.0V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
0
¾
4000
kHz
0
¾
8000
kHz
45
90
180
ms
32
65
130
ms
11
23
46
ms
8
17
33
ms
3V
Timer I/P Frequency (TMR0/TMR1)
50% duty
5V
tWDTOSC
Min.
Conditions
VDD
3V
¾
Watchdog Oscillator Period
5V
tWDT1
Watchdog Time-out Period
(WDT OSC)
3V
tWDT2
Watchdog Time-out Period (fSYS/4)
¾
Without WDT prescaler
¾
1024
¾
tSYS
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
tSYS
tLVR
Low Voltage Width to Reset
¾
¾
1
¾
¾
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tACC
Data ROM Access Time
¾
¾
1
¾
¾
ms
Without WDT prescaler
5V
Power-up reset or
wake-up from HALT
Note: tSYS=1/(fSYS)
Rev. 1.20
5
June 10, 2005
HT48RA5/HT48CA5
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the MCU is derived from either a
crystal or an RC oscillator. The system clock is internally
divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading register, subroutine call or return from
subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed to the next instruction.
Program Counter - PC
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 1
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*15~*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
00000000
0
0
0
0
0
0
0
0
External Interrupt
00000000
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
00000000
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
00000000
0
0
0
0
1
1
0
0
Skip
*15~*13 (*12~*0+2)=(within-current bank)
Loading PCL
*15~*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#15~#8
#7
#6
#5
#4
#3
#2
#1
#0
Return (RET, RETI)
S15~S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*15~*0: Program counter bits
S15~S0: Stack register bits
#15~#0: Instruction code bits
1 bank: 8K words
@7~@0: PCL bits
Rev. 1.20
6
June 10, 2005
HT48RA5/HT48CA5
Program Memory - ROM
0 0 0 H
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits´5 banks, addressed by the program counter and table pointer.
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r 0
In te r r u p t S u b r o u tin e
0 0 C H
T im e r /E v e n t C o u n te r 1
In te r r u p t S u b r o u tin e
Certain locations in the program memory are reserved
for special usage:
P ro g ra m
M e m o ry
n 0 0 H
· Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
· Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
L o o k - u p T a b le ( 2 5 6 w o r d s )
9 F F F H
1 6 b its
N o te : n ra n g e s fro m
· Location 008H
0 to 9 F
Program Memory
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 008H .
terrupt(s) is supposed to be disabled prior to the table
read instruction. It (They) will not be enabled until the
TBLH in the main routine has been backup. All table
related instructions require 2 cycles to complete the
operation.
· Location 00CH
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at location 00CH.
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
· Table location
Any location in the program memory can be used as
look-up tables. The instructions ²TABRDC [m]² (page
specified by TBHP) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the higher-order byte to
TBLH (08H). The higher-order byte table pointer
TBHP (1FH) and lower-order byte table pointer TBLP
(07H) are read/write registers, which indicate the table
locations. Before accessing the table, the location has
to be placed in TBHP and TBLP. The TBLH is read
only and cannot be restored. If the main routine and
the ISR (interrupt service routine) both employ the table read instruction, the contents of TBLH in the main
routine are likely to be changed by the table read instruction used in the ISR. Errors are thus brought
about. Given this, using the table read instruction in
the main routine and the ISR simultaneously should
be avoided. However, if the table read instruction has
to be applied in both main routine and the ISR, the in-
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subTable Location
Instruction
*15~*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TBHP
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
10011111
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *15~*0: Table location bits
Rev. 1.20
@7~@0: Table pointer bits
7
June 10, 2005
HT48RA5/HT48CA5
0 0 H
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return addresses are stored).
Data Memory - RAM
The data memory is designed with 250´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(224´8). Most are read/write, but some are read only.
The special function registers include the indirect addressing registers (R0;00H, R1;02H), bank pointer
(BP;04H), Timer/Event Counter 0 (TMR0;0DH),
Timer/Event Counter 0 control register (TMR0C;0EH),
Timer/Event Counter 1 higher order byte register
(TMR1H;0FH), Timer/Event Counter 1 lower order byte
register (TMR1L;10H), Timer/Event Counter 1 control
register (TMR1C;11H), program counter lower-order
byte register (PCL;06H), memory pointer registers
(MP0;01H, MP1;03H), accumulator (ACC;05H), table
pointer (TBLP;07H, TBHP;1FH), table higher-order
byte register (TBLH;08H), status register (STATUS;
0AH), interrupt control register (INTC;0BH), Watchdog
Timer option setting register (WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H, PF;1CH), and I/O control registers (PAC;13H, PBC;15H, PCC;17H,
PFC;1DH). The remaining space before the 20H is reserved for future expanded usage and reading these
locations will get ²00H². The general purpose data
memory, addressed from 20H to FFH, is used for data
and control information under instruction commands.
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
S p e c ia l P u r p o s e
D A T A M E M O R Y
1 8 H
1 9 H
: U n u s e d
1 A H
1 B H
1 C H
P F
1 D H
P F C
R e a d a s "0 0 "
1 E H
1 F H
2 0 H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
T B H P
G e n e ra l P u rp o s e
D A T A M E M O R Y
(2 2 4 B y te s )
F F H
Indirect Addressing Register
RAM Mapping
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] ([02H]) will access data memory pointed
to by MP0 (MP1). Reading location 00H (02H) itself indirectly will return the result 00H. Writing indirectly results
in no operation.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
The memory pointer registers (MP0 and MP1) are 8-bit
registers.
· Logic operations (AND, OR, XOR, CPL)
· Increment and decrement (INC, DEC)
Accumulator
· Rotation (RL, RR, RLC, RRC)
The accumulator is closely related to ALU operations. It
is also mapped to location of the data memory and can
carry out immediate data operations. The data movement between two data memory locations must pass
through the accumulator.
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
Rev. 1.20
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June 10, 2005
HT48RA5/HT48CA5
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be prevented from becoming full.
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or
during a system power-up.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
External interrupts are triggered by a high to low transition of the INT and the related interrupt request flag (EIF;
bit 4 of INTC) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of INTC), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further interrupts.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to set the enable/disable and the interrupt request flags.
The internal Timer/Even Counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (T1F;bit 6 of INTC), caused by a timer 1 overflow.
When the interrupt is enabled, the stack is not full and
the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset
and the EMI bit cleared to disable further interrupts.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.20
9
June 10, 2005
HT48RA5/HT48CA5
Oscillator Configuration
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
There are 2 oscillator circuits implemented in the
microcontroller.
O S C 1
O S C 2
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
O S C 1
C r y s ta l O s c illa to r
fS Y S /4
N M O S O p e n D r a in
O S C 2
R C O s c illa to r
System Oscillator
Both of them are designed for system clocks, namely
the RC oscillator and the crystal oscillator, which are determined by options. No matter what oscillator type is
selected, the signal provides the system clock. The
HALT mode stops the system oscillator and resists the
external signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance should
range from 100kW to 820kW. The system clock, divided
by 4, is available on OSC2, which can be used to synchronize external logic. The internal RC oscillator provides the most cost effective solution. However, the
frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is,
therefore, not suitable for timing sensitive operations
where an accurate oscillator frequency is desired.
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), external interrupt request flag (EIF), enable
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), enable external interrupt bit (EEI) and enable master interrupt bit (EMI) constitute an interrupt control register
(INTC) which is located at 0BH in the data memory. EMI,
EEI, ET0I and ET1I are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request
flags (T0F, T1F, EIF) are set, they will remain in the INTC
register until the interrupts are serviced or cleared by a
software instruction.
If the crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are demanded. Instead of a crystal, the
resonator can also be connected between OSC1 and
OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 90ms. The WDT oscillator can
be disabled by ROM code option to conserve power.
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI
Controls the external interrupt (1= enabled; 0= disabled)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled)
4
EIF
External interrupt request flag (1= active; 0= inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)
7
¾
Unused bit, read as ²0²
INTC (0BH) Register
Rev. 1.20
10
June 10, 2005
HT48RA5/HT48CA5
Watchdog Timer - WDT
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset² and only
the program counter and SP are reset to zero. To clear
the contents of WDT (including the WDT prescaler),
three methods are adopted; external reset (a low level to
RES), software instruction and a ²HALT² instruction.
The software instruction include ²CLR WDT² and the
other set ²CLR WDT1² and ²CLR WDT2². Of these two
types of instruction, only one can be active depending
on the ROM code option ²CLR WDT² times selection
option. If the ²CLR WDT² is selected (i.e. ²CLR WDT²
times equal one), any execution of the ²CLR WDT² instruction will clear the WDT. In the case that ²CLR
WDT1² and ²CLR WDT2² are chosen (i.e. ²CLR WDT²
times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), instruction clock (system
clock divided by 4), determines the ROM code option.
This timer is designed to prevent a software malfunction
or sequence from jumping to an unknown location with
unpredictable results. The Watchdog Timer can be disabled by ROM code option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no
operation.
Once the internal WDT oscillator (RC oscillator with a
period of 90ms@3V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 23ms@3V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.9s@3V
seconds. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and operates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by
external logic. The high nibble and bit 3 of the WDTS are
reserved for user¢s defined flags, which can be used to
indicate some specified status.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected).
· The contents of the on chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and re-
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
counted again (if the WDT clock is from the WDT oscillator).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and SP; the others remain in their
original status.
WDTS Register
S y s te m
C lo c k /4
W D T
O S C
R O M
C o d e
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.20
11
June 10, 2005
HT48RA5/HT48CA5
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence
may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to
²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
The functional unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/event Counter
Off
Input/output Ports
Input mode
SP
Points to the top of the stack
V D D
R E S
tS
C h ip
R e s e t
Reset Timing Chart
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
V
There are three ways in which a reset can occur:
1 0 0 k W
· RES reset during HALT
R E S
· WDT time-out reset during normal operation
1 0 k W
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
PDF
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
D D
0 .0 1 m F *
· RES reset during normal operation
TO
S T
S S T T im e - o u t
0 .1 m F *
Reset Circuit
Note:
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
RESET Conditions
H A L T
W a rm
R e s e t
W D T
R E S
Note: ²u² stands for unchanged
O S C 1
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
C o ld
R e s e t
R e s e t
Reset Configuration
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
Rev. 1.20
12
June 10, 2005
HT48RA5/HT48CA5
The states of the registers is summarized in the table.
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000H
0000H
0000H
0000H
0000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
Register
Program
Counter
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PCC
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PF
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
PFC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.20
13
June 10, 2005
HT48RA5/HT48CA5
0 preload register and issues the interrupt request just
like the other two modes.
Timer/Event Counter
Two timer/event counters (TMR0, TMR1) are implemented in the device. The Timer/Event Counter 0 contains an 8-bit programmable count-up counter and the
clock may come from an external source or the system
clock. The Timer/Event Counter 1 contains an 16-bit
programmable count-up counter and the clock may
come from an external source or the system clock divided by 4.
To enable the counting operation, the timer ON bit
(T0ON; bit 4 of TMR0C) should be set to 1. In the pulse
width measurement mode, the T0ON will be cleared automatically after the measurement cycle is complete.
But in the other two modes the T0ON can only be reset
by instructions. The overflow of the Timer/Event Counter 0 is one of the wake-up sources. No matter what the
operation mode is, writing a 0 to ET0I can disabled the
corresponding interrupt service.
Of the two timer/event counters, using external clock input allows the user to count external events, measure
time internals or pulse widths, or generate an accurate
time base. While using the internal clock allows the user
to generate an accurate time base.
In the case of Timer/Event Counter 0 OFF condition,
writing data to the Timer/Event Counter 0 preload register will also load the data to Timer/Event Counter 0. But
if the Timer/Event Counter 0 is turned on, data written to
the Timer/Event Counter 0 will only be kept in the
Timer/Event Counter 0 preload register. The
Timer/Event Counter 0 will still operate until the overflow
occurs (a Timer/Event Counter 0 reloading will occur at
the same time).
Only the Timer/Event Counter 0 can generate PFD signal by using external or internal clock, and PFD frequency is determine by the equation fINT/[2´(256-N)].
There are 2 registers related to Timer/Event Counter 0;
TMR0(0DH), TMR0C(0EH). In Timer/Event Counter 0
counting mode (T0ON=1), writing TMR0 will only put the
written data to preload register (8 bits). The Timer/Event
Counter 0 preload register is changed by each writing
TMR0 operations. Reading TMR0 will also latch the
TMR0 to the destination. The TMR0C is the Timer/Event
Counter 0 control register, which defines the operating
mode, counting enable or disable and active edge.
When the Timer/Event Counter 0 (reading TMR0) is
read, the clock will be blocked to avoid errors. As this
may results in a counting error, this must be taken into
consideration by the programmer.
The bit 0~2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of
Timer/Event Counter 0. The definitions are as shown.
The T0M0, T0M1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR0) pin. The timer mode functions as a normal timer
with the clock source coming from the fINT clock. The
pulse width measurement mode can be used to count
the high or low level duration of the external signal
(TMR0). The counting is based on the fINT clock.
Bit
No.
Function
To define the prescaler stages,
T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS/2
001: fINT=fSYS/4
T0PSC0
010: fINT=fSYS/8
0~2 T0PSC1
011: fINT=fSYS/16
T0PSC2
100: fINT=fSYS/32
101: fINT=fSYS/64
110: fINT=fSYS/128
111: fINT=fSYS/256
In the event count or timer mode, once the Timer/Event
Counter 0 starts counting, it will count from the current
contents in the Timer/Event Counter 0 to FFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter 0 preload register and generates
the corresponding interrupt request flag (T0F; bit 5 of
INTC) at the same time.
In pulse width measurement mode with the T0ON and
T0E bits are equal to one, once the TMR0 has received
a transition from low to high (or high to low if the T0E bit
is 0) it will start counting until the TMR0 returns to the
original level and reset the T0ON. The measured result
will remain in the Timer/Event Counter 0 even if the activated transition occurs again. In other words, only one
cycle measurement can be done. Until setting the
T0ON, the cycle measurement will function again as
long as it receives further transition pulse. Note that, in
this operating mode, the Timer/Event Counter 0 starts
counting not according to the logic level but according to
the transition edges. In the case of counter overflows,
the counter 0 is reloaded from the Timer/Event Counter
Rev. 1.20
Label
3
T0E
To define the TMR0 active edge of
Timer/Event Counter 0
(0=active on low to high;
1=active on high to low)
4
T0ON
To enable/disable timer 0 counting
(0=disabled; 1=enabled)
5
¾
6
7
T0M0
T0M1
Unused bit, read as ²0²
To define the operating mode
(T0M1, T0M0)
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
14
June 10, 2005
HT48RA5/HT48CA5
In pulse width measurement mode with the T1ON and
T1E bits are equal to one, once the TMR1 has received
a transition from low to high (or high to low if the T1E bit
is 0) it will start counting until the TMR1 returns to the
original level and reset the T1ON. The measured result
will remain in the Timer/Event Counter 1 even if the activated transition occurs again. In other words, only one
cycle measurement can be done. Until setting the
T1ON, the cycle measurement will function again as
long as it receives further transition pulse. Note that, in
this operating mode, the Timer/Event Counter 1 starts
counting not according to the logic level but according to
the transition edges. In the case of counter overflows,
the counter 1 is reloaded from the Timer/Event Counter
1 preload register and issues the interrupt request just
like the other two modes.
There are 3 registers related to Timer/Event Counter 1;
TMR1H(0FH), TMR1L(10H), TMR1C(11H). Writing
TMR1L will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMR1H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L preload
registers, respectively. The Timer/Event Counter 1
preload register is changed by each writing TMR1H operations. Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destination and the
lower-order byte buffer, respectively. Reading the
TMR1L will read the contents of the lower-order byte
buffer. The TMR1C is the Timer/Event Counter 1 control
register, which defines the operating mode, counting enable or disable and active edge.
The T1M0, T1M1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR1) pin. The timer mode functions as a normal timer
with the clock source coming from the instruction clock.
The pulse width measurement mode can be used to
count the high or low level duration of the external signal
(TMR1). The counting is based on the instruction clock.
To enable the counting operation, the timer ON bit
(T1ON; bit 4 of TMR1C) should be set to 1. In the pulse
width measurement mode, the T1ON will be cleared automatically after the measurement cycle is complete.
But in the other two modes the T1ON can only be reset
by instructions. The overflow of the Timer/Event Counter 1 is one of the wake-up sources. No matter what the
operation mode is, writing a 0 to ET1I can disabled the
corresponding interrupt service.
In the event count or timer mode, once the Timer/Event
Counter 1 starts counting, it will count from the current
contents in the Timer/Event Counter 1 to FFFFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter 1 preload register and generates
the corresponding interrupt request flag (T1F; bit 6 of
INTC) at the same time.
In the case of Timer/Event Counter 1 OFF condition,
writing data to the Timer/Event Counter 1 preload register will also load the data to Timer/Event Counter 1. But
if the Timer/Event Counter 1 is turned on, data written to
the Timer/Event Counter 1 will only be kept in the
(1 /2 ~ 1 /2 5 6 )
fS
Y S
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
T 0 P S C 2 ~ T 0 P S C 0
D a ta B u s
T
T 0 M 1
T 0 M 0
T M R 0
T im e r /E v e n t C o u n te r 0
P r e lo a d R e g is te r
R e lo a d
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
8 - b it
T im e r /E v e n t C o u n te r
(T M R 0 )
O v e r flo w
¸ 2
to In te rru p t
P F D
Timer/Event Counter 0
D a ta B u s
T 1 M 1
fS Y S /4
T 1 M 0
T M R 1
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
1 6 - b it
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
L o w B y te
B u ffe r
R e lo a d
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
1 6 - b it
T im e r /E v e n t C o u n te r
(T M R 1 H /T M R 1 L )
O v e r flo w
to In te rru p t
Timer/Event Counter 1
Rev. 1.20
15
June 10, 2005
HT48RA5/HT48CA5
Timer/Event Counter 1 preload register. The
Timer/Event Counter 1 will still operate until the overflow
occurs (a Timer/Event Counter 1 reloading will occur at
the same time).
Input/Output Ports
There are 23 bi-directional input/output lines in the micro-controller, labeled from PA to PC and PF, which are
mapped to the data memory of [12H], [14H], [16H] and
[1CH], respectively. All of these I/O ports can be used as
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction ²MOV A,[m]² (m =
12H, 14H, 16H or 1CH). For output operation, all the
data is latched and remains unchanged until the output
latch is rewritten.
When the Timer/Event Counter 1 (reading TMR1H) is
read, the clock will be blocked to avoid errors. As this
may results in a counting error, this must be taken into
consideration by the programmer.
The definitions of the TMR1C are as shown.
Bit
No.
Label
0~2
¾
3
T1E
4
T1ON
5
¾
6
7
T1M0
T1M1
Function
Each I/O line has its own control register (PAC, PBC,
PCC, PFC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trigger input with or without (depends on options) pull-high
resistor structures can be reconfigured dynamically (i.e.,
on-the fly) under software control. To function as an input, the corresponding latch of the control register has to
be set as ²1². The pull-high resistor (if the pull-high resistor is enabled) will be exhibited automatically. The input sources also depends on the control register. If the
control register bit is ²1², the input will read the pad state
(²mov² and read-modify-write instructions”). If the control register bit is 0, the contents of the latches will move
to internal data bus (²mov² and read-modify-write instructions). The input paths (pad state or latches) of
read-modify-write instructions are dependent on the
control register bits. For output function, CMOS is the
only configuration. These control registers are mapped
to locations 13H, 15H, 17H and 1DH.
Unused bit, read as ²0²
To define the active edge of TMR1 pin
input signal
(0/1: active on low to high/high to low)
To enable/disable timer 1 counting
(0/1: disabled/enabled)
Unused bit, read as ²0²
To define the operating mode
(T1M1, T1M0)
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
V
C o n tr o l B it
D a ta B u s
P U
Q
D
Q
C K
W r ite C o n tr o l R e g is te r
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
P A 0
P B 0
P B 1
P C 0
P F 0
D a ta B it
Q
D
S
( P B 0 o n ly )
R e a d D a ta R e g is te r
S y s te m
P B 0
E X T
~ P A 7
/P F D
~ P B 7
~ P C 5
Q
C K
W r ite D a ta R e g is te r
D D
M
M
U
U
X
P F D E N
( P B 0 o n ly )
X
W a k e - u p ( P A o n ly )
P A W a k e - u p O p tio n
IN T fo r P F 0 O n ly
P F D
fo r P B 0 O n ly , C o n tr o l= P B 0 D a ta R e g is te r
Input/Output Ports
Rev. 1.20
16
June 10, 2005
HT48RA5/HT48CA5
When calling a subroutine or an interrupt event occurring, the contents of the program counter are save into
stack registers. If a returning from subroutine occurs,
the contents of the program counter will restore from
stack registers.
After a chip reset, these input/output lines stay at high
levels (pull-high options) or floating state (non-pull-high
options). Each bit of these input/output latches can be
set or cleared by ²SET [m].i² (m=12H, 14H, 16H or 1CH)
instructions. Some instructions first input data and then
follow the output operations. For example, ²SET [m].i²,
²CLR [m].i², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or the accumulator.
Each line of port A has the capability of waking-up the
device. The highest 2 bits of port C and 7 bits of port F
are not physically implemented; on reading them a ²0² is
returned whereas writing then results in a no-operation.
Pull-high resistors of each port are decided by a option
bit.
O
O
O
PB0/PFD Option
x
PB0
PFD
PFD
PB0 (14H) Bit0
x
D
0
1
PB0 Pad Status
I
D
0
PFD
Note:
BP.5
ROM
Address
0
0
Bank0
0000H~1FFFH
0
0
1
Bank1
2000H~3FFFH
0
1
0
Bank2
4000H~5FFFH
0
1
1
Bank3
6000H~7FFFH
1
0
1
Bank4
8000H~9FFFH
Low Voltage Reset - LVR
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally.
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
The truth table of PB0/PFD is as shown.
I
BP.6
0
Bank Pointer
The PB0 is pin-shared with PFD signal, respectively. If
the PFD option is selected, the output signal in output
mode of PB0 will be the PFD signal. The input mode always remain its original functions. The PF0 and PC0 are
pin-shared with INT and TMR0. The INT signal is directly connected to PF0. The PFD output signal (in output mode) are controlled by the PB0 data register only.
The truth table of PB0/PFD is listed below.
PBC (15H) Bit0
BP.7
· The LVR uses the ²OR² function with the external
RES signal to perform chip reset.
The relationship between VDD and VLVR is shown below.
V D D
5 .5 V
I: Input; O: Output; D: Data
Bank Pointer
There is a bank pointer used to control the program flow
to go to any banks. A bank contains 8K´16 address
space. The contents of bank pointer are load into program counter when the JMP or CALL instruction is executed. The program counter is a 16-bit register whose
contents are used to specify the executed instruction
addresses.
Rev. 1.20
V
L V R
1 .8 V
0 .9 V
17
June 10, 2005
HT48RA5/HT48CA5
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
²*1² To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
²*2² Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters
the reset mode.
Options
The following table shows all kinds of code option in the MCU. All of the mask options must be defined to ensure proper
system functioning.
Function
PA0~PA7 wake-up enable or disable options
PC pull-high enable or disable
PA pull-high enable or disable: Byte option
PF pull-high enable or disable
PB pull-high (PB0~PB3, PB4~PB7) enable or disable: Nibble option
PB0 or PFD
CLR WDT instructions
System oscillators: RC or crystal
WDT enable or disable
WDT clock source: WDTOSC or system clock/4
LVR function: enable or disable
LVR voltage: 2.0V or 3.0V
Rev. 1.20
18
June 10, 2005
HT48RA5/HT48CA5
Application Circuits
RC Oscillator for Multiple I/O Applications
V
Crystal or Ceramic Resonator for Multiple I/O
Applications
V
D D
D D
V D D
V D D
P A 0 ~ P A 7
0 .0 1 m F *
1 0 0 k W
R E S
0 .1 m F
P B 1 ~ P B 7
0 .1 m F *
R
O S C
O S C 1
P C 1 ~ P C 4
P C 5 /T M R 1
0 .1 m F *
C
0 .0 1 m F *
0 .1 m F *
C
+
1 0 k W
P C 0 /T M R 0
P C 1 ~ P C 4
P C 5 /T M R 1
O S C 2
P F 0 /IN T
H T 4 8 R A 5 /H T 4 8 C A 5
= 3 V
1 0 0 k W
1 W
P B 1 ~ P B 7
V S S
V S S
D D
O S C 1
C ry s ta l
(S e e N o te )
H T 4 8 R A 5 /H T 4 8 C A 5
V
C
1 0 k W
P F 0 /IN T
O S C 2
N M O S
o p e n d r a in
P B 0 /P F D
R E S
0 .1 m F
P C 0 /T M R 0
1 0 k W
P A 0 ~ P A 7
0 .0 1 m F *
1 0 0 k W
P B 0 /P F D
4 7 m F
C ry s ta l
(s e e N o te )
C
V D D
P A 0
R E S
P A 1
P A 2
O S C 1
P A 3
P A 4
O S C 2
P A 5
V S S
P A 6
P A 7
1 2 0 W
R e c e iv e r
P B 2
P B 0 /P F D
P B 3
P B 4
P F 0 /IN T
( L e a r n in g In p u t)
P B 5
P B 6
P C 2
E E P R O M
P B 7
P C 3
P C 0 /T M R 0
P C 4
P C 1
P C 5 /T M R 1
H T 4 8 R A 5 /H T 4 8 C A 5
Note:
The resistance and capacitance for reset circuit should be designed to ensure that the VDD is stable and remains in a valid range of the operating voltage before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
The following table shows the C value according different crystal values. (For reference only)
Crystal or Resonator
Rev. 1.20
C
4MHz Crystal
0pF
4MHz Resonator
10pF
3.58MHz Crystal
0pF
3.58MHz Resonator
25pF
2MHz Crystal & Resonator
25pF
1MHz Crystal
35pF
480kHz Resonator
300pF
455kHz Resonator
300pF
429kHz Resonator
300pF
19
June 10, 2005
HT48RA5/HT48CA5
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.20
20
June 10, 2005
HT48RA5/HT48CA5
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.20
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
21
June 10, 2005
HT48RA5/HT48CA5
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
22
June 10, 2005
HT48RA5/HT48CA5
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
23
June 10, 2005
HT48RA5/HT48CA5
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
24
June 10, 2005
HT48RA5/HT48CA5
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
25
June 10, 2005
HT48RA5/HT48CA5
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
26
June 10, 2005
HT48RA5/HT48CA5
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
27
June 10, 2005
HT48RA5/HT48CA5
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
28
June 10, 2005
HT48RA5/HT48CA5
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
29
June 10, 2005
HT48RA5/HT48CA5
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
June 10, 2005
HT48RA5/HT48CA5
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
31
June 10, 2005
HT48RA5/HT48CA5
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
32
June 10, 2005
HT48RA5/HT48CA5
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
June 10, 2005
HT48RA5/HT48CA5
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
34
June 10, 2005
HT48RA5/HT48CA5
Package Information
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.20
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
35
June 10, 2005
HT48RA5/HT48CA5
28-pin SSOP (209mil) Outline Dimensions
1 5
2 8
A
B
1 4
1
C
C '
G
H
D
E
Symbol
Rev. 1.20
a
F
Dimensions in mil
Min.
Nom.
Max.
A
291
¾
323
B
196
¾
220
C
9
¾
15
C¢
396
¾
407
D
65
¾
73
E
¾
25.59
¾
F
4
¾
10
G
26
¾
34
H
4
¾
8
a
0°
¾
8°
36
June 10, 2005
HT48RA5/HT48CA5
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
Dimensions in mm
330±1.0
62±1.5
13.0+0.5
-0.2
C
Spindle Hole Diameter
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.20
37
June 10, 2005
HT48RA5/HT48CA5
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.20
21.3
38
June 10, 2005
HT48RA5/HT48CA5
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
39
June 10, 2005