LATTICE ISPLSI2128V

®
ispLSI 2128V
3.3V High Density Programmable Logic
Features
Functional Block Diagram*
• HIGH DENSITY PROGRAMMABLE LOGIC
fmax = 80 MHz Maximum Operating Frequency
tpd = 10 ns Propagation Delay
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
C6
S
A1
A2
A3
Logic
Array
A4
A5
D
Q
D
Q
D
Q
D
Q
C5
C4
GLB
C3
C2
A6
A7
Output Routing Pool (ORP)
D0
C7
C1
Global Routing Pool (GRP)
B0
B1
B2
B3
Output Routing Pool (ORP)
*128 I/O Version Shown
• IN-SYSTEM PROGRAMMABLE
D1
A0
N
—
—
—
—
—
—
D2
B4
B5
C0
B6
B7
Output Routing Pool (ORP)
• HIGH PERFORMANCE E CMOS TECHNOLOGY
D4
CLK 0
CLK 1
CLK 2
®
D3
D5
ES
IG
N
2
Output Routing Pool (ORP)
— Interfaces with Standard 5V TTL Devices
— The 128 I/O Pin Version is Fuse Map Compatible
with 5V ispLSI 2128
Output Routing Pool (ORP)
D6
D
• 3.3V LOW VOLTAGE 2128 ARCHITECTURE
Output Routing Pool (ORP)
D7
EW
6000 PLD Gates
128 and 64 I/O Pin Versions, Eight Dedicated Inputs
128 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
Output Routing Pool (ORP)
—
—
—
—
—
Output Routing Pool (ORP)
0139A/2128V
R
Description
FO
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
12
8
VE
The ispLSI 2128V is a High Density Programmable Logic
Device available in 128 and 64 I/O-pin versions. The
device contains 128 Registers, eight Dedicated Input
pins, three Dedicated Clock Input pins, two dedicated
Global OE input pins and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between
all of these elements. The ispLSI 2128V features insystem programmability through the Boundary Scan
Test Access Port (TAP). The ispLSI 2128V offers nonvolatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
I2
Enhanced Pin Locking Capability
Three Dedicated Clock Input Pins
Synchronous and Asynchronous Clocks
Programmable Output Slew Rate Control
Flexible Pin Placement
Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 2128V device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
pL
S
—
—
—
—
—
—
SE
is
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
U
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2128v_14
1
September 2000
Specifications ispLSI 2128V
Functional Block Diagram
RESET
IN 7*
IN 6*
I/O 51
I/O 50
I/O 49
I/O 48
I/O 55
I/O 54
I/O 53
I/O 52
I/O 59
I/O 58
I/O 57
I/O 56
I/O 63
I/O 62
I/O 61
I/O 60
IN 7
IN 6
I/O 99
I/O 98
I/O 97
I/O 96
I/O 103
I/O 102
I/O 101
I/O 100
I/O 107
I/O 106
I/O 105
I/O 104
I/O 111
I/O 110
I/O 109
I/O 108
I/O 115
I/O 114
I/O 113
I/O 112
I/O 119
I/O 118
I/O 117
I/O 116
I/O 123
I/O 122
I/O 121
I/O 120
I/O 127
I/O 126
I/O 125
I/O 124
Figure 1. ispLSI 2128V Functional Block Diagram (128-I/O and 64-I/O Versions)
RESET
Input Bus
GOE 0
GOE 1
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Megablock
Megablock
IN 5
IN 4
A5
C1
I/O 75
I/O 74
I/O 73
I/O 72
I/O 8
I/O 9
I/O 10
I/O 11
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
A6
C0
B0
B1
B2
B3
B5
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
S
A4
Input Bus
C3
C2
A5
A7
TDI/IN 0
TMS/IN 1
ispEN
C4
Global
Routing
Pool
(GRP)
A3
I/O 12
I/O 13
I/O 14
I/O 15
B7
B6
A2
A6
A7
TDI/IN 0
TMS/IN 1
IN 5*
IN 4*
D0
D1
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
C5
B0
N
B1
B2
C0
B3
I/O 39
I/O 38
I/O 37
I/O 36
C1
B5
B4
B6
I/O 35
I/O 34
I/O 33
I/O 32
B7
Output Routing Pool (ORP)
Input Bus
Y0
Y1
Y2
I/O 28
I/O 29
I/O 30
I/O 31
I/O 24
I/O 25
I/O 26
I/O 27
TDO/IN 2
TCK/IN 3
R
0139B/2128V
0139B/2128V.64IO
*Not available on 84-PLCC Device
FO
Y0
Y1
Y2
I/O 60
I/O 61
I/O 62
I/O 63
I/O 56
I/O 57
I/O 58
I/O 59
I/O 52
I/O 53
I/O 54
I/O 55
I/O 48
I/O 49
I/O 50
I/O 51
I/O 44
I/O 45
I/O 46
I/O 47
I/O 40
I/O 41
I/O 42
I/O 43
I/O 36
I/O 37
I/O 38
I/O 39
I/O 32
I/O 33
I/O 34
I/O 35
TDO/IN 2
TCK/IN 3
ispEN
I/O 20
I/O 21
I/O 22
I/O 23
I/O 28
I/O 29
I/O 30
I/O 31
C2
D2
D3
C6
I/O 16
I/O 17
I/O 18
I/O 19
I/O 24
I/O 25
I/O 26
I/O 27
A4
D4
A1
I/O 79
I/O 78
I/O 77
I/O 76
C3
D5
A0
I/O 4
I/O 5
I/O 6
I/O 7
I/O 83
I/O 82
I/O 81
I/O 80
C4
Global
Routing
Pool
(GRP)
A3
I/O 20
I/O 21
I/O 22
I/O 23
I/O 87
I/O 86
I/O 85
I/O 84
A2
D6
Input Bus
C5
Input Bus
I/O 16
I/O 17
I/O 18
I/O 19
Output Routing Pool (ORP)
I/O 12
I/O 13
I/O 14
I/O 15
A1
Input Bus
I/O 8
I/O 9
I/O 10
I/O 11
I/O 0
I/O 1
I/O 2
I/O 3
CLK 0
CLK 1
CLK 2
I/O 4
I/O 5
I/O 6
I/O 7
D7
C7
I/O 91
I/O 90
I/O 89
I/O 88
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C6
Output Routing Pool (ORP)
C7
A0
Generic Logic
Blocks (GLBs)
I/O 95
I/O 94
I/O 93
I/O 92
Output Routing Pool (ORP)
D0
D1
CLK 0
CLK 1
CLK 2
D2
D3
ES
IG
N
D4
D
D5
EW
D6
Input Bus
D7
Output Routing Pool (ORP)
Generic Logic
Blocks (GLBs)
I/O 0
I/O 1
I/O 2
I/O 3
Input Bus
GOE 0
GOE 1
Output Routing Pool (ORP)
The 128-I/O 2128V contains 128 I/O cells, while the 64I/O version contains 64 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually programmed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control. The signal
levels are TTL compatible voltages and the output drivers
can source 4mA or sink 8mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 5V signal levels to support
mixed-voltage systems.
VE
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
28
Programmable Open-Drain Outputs
SI
21
In addition to the standard output configuration, the
outputs of the ispLSI 2128V are individually programmable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a programmable fuse. When this fuse is erased (JEDEC “1”),
the output is configured as a totem-pole output. When
this fuse is programmed (JEDEC “0”), the output is
configured as an open-drain. The default configuration
when the device is in bulk erased state is totem-pole
configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
SE
is
pL
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
the two or one ORPs. Each ispLSI 2128V device contains
four Megablocks.
U
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2128V device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
2
Specifications ispLSI 2128V
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +5.6V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
S
Storage Temperature ................................ -65 to 150°C
ES
IG
N
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
D
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
SYMBOL
EW
DC Recommended Operating Condition
PARAMETER
VIL
VIH
Input Low Voltage
Commercial
TA = 0°C to + 70°C
Industrial
TA = -40°C to + 85°C
N
Supply Voltage
UNITS
3.0
3.6
V
3.0
3.6
V
0.8
V
2.0
FO
Input High Voltage
MAX.
VSS – 0.5
R
VCC
MIN.
5.25
V
Table 2-0005/2128V
VE
Capacitance (TA=25°C, f=1.0 MHz)
TYPICAL
UNITS
Dedicated Input Capacitance
10
pf
VCC = 3.3V, VIN = 2.0V
I/O Capacitance
10
pf
VCC = 3.3V, VI/O = 2.0V
15
pf
VCC = 3.3V, VY = 2.0V
21
C1
C2
C3
PARAMETER
28
SYMBOL
Clock and Global Output Enable Capacitance
TEST CONDITIONS
SI
Table 2-0006/2128V
pL
Data Retention Specifications
is
PARAMETER
MINIMUM
MAXIMUM
UNITS
20
–
Years
10000
–
Cycles
Data Retention
SE
ispLSI Erase/Reprogram Cycles
U
Table 2-0008/2128V
3
Specifications ispLSI 2128V
Switching Test Conditions
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
≤ 3ns 10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
+ 3.3V
R1
See Figure 2
Device
Output
Test
Point
ES
IG
N
3-state levels are measured 0.5V from steady-state
Table 2 - 0003/2000
active level.
S
Input Rise and Fall Time
R2
Output Load Conditions (see Figure 2)
CL
35pF
Active High
∞
348Ω
35pF
Active Low
C
316Ω
348Ω
35pF
Active High to Z
at VOH -0.5V
∞
348Ω
5pF
Active Low to Z
at VOL +0.5V
316Ω
348Ω
5pF
0213A/2128V
D
R2
348Ω
EW
B
*CL includes Test Fixture and Probe Capacitance.
R1
316Ω
N
TEST CONDITION
A
CL*
FO
R
Table 2-0004/2128V
DC Electrical Characteristics
SYMBOL
PARAMETER
CONDITION
IOL= 8 mA
28
Output Low Voltage
IOH = -4 mA
Output High Voltage
Input or I/O Low Leakage Current
21
VOL
VOH
IIL
VE
Over Recommended Operating Conditions
3
MIN.
TYP.
MAX. UNITS
–
–
0.4
V
2.4
–
–
V
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
µA
(VCC – 0.2)V ≤ VIN ≤ VCC
–
–
10
µA
VCC ≤ VIN ≤ 5.25V
–
–
50
mA
Input or I/O High Leakage Current
IIL-isp
IIL-PU
IOS1
ispEN Input Low Leakage Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
Output Short Circuit Current
VCC = 3.3V, VOUT = 0.5V
–
–
-100
mA
ICC2, 4
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
–
195
–
mA
is
pL
SI
IIH
fCLOCK = 1 MHz
U
SE
Table 2-0007/2128V
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at VCC = 3.3V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC .
4
Specifications ispLSI 2128V
External Timing Parameters
Over Recommended Operating Conditions
4
-80
1
-60
MIN. MAX. MIN. MAX.
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
A
2
Data Propagation Delay
A
3
Clock Frequency with Internal Feedback 3
–
4
–
–
–
10.0
–
15.0
UNITS
ns
15.0
–
20.0
–
61.7
–
MHz
Clock Frequency with External Feedback ( tsu2 + tco1)
64.5
–
51.3
–
MHz
5
Clock Frequency, Max. Toggle
100
–
71.4
–
MHz
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
7.0
–
9.0
–
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
6.5
–
8.5
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
ns
–
9
GLB Reg. Setup Time before Clock
9.0
–
11.0
–
ns
–
10 GLB Reg. Clock to Output Delay
–
11 GLB Reg. Hold Time after Clock
A
12 Ext. Reset Pin to Output Delay
–
13 Ext. Reset Pulse Duration
EW
D
ES
IG
N
1
–
7.5
–
9.5
ns
0.0
–
0.0
–
ns
–
14.0
–
16.0
ns
7.0
–
8.0
–
ns
–
15.0
–
18.0
ns
–
15.0
–
18.0
ns
–
10.0
–
12.0
ns
–
10.0
–
12.0
ns
5.0
–
7.0
–
ns
–
7.0
–
ns
14 Input to Output Enable
15 Input to Output Disable
B
16 Global OE Output Enable
C
17 Global OE Output Disable
–
18 External Synchronous Clock Pulse Duration, High
–
19 External Synchronous Clock Pulse Duration, Low
5.0
N
B
C
28
VE
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
SI
pL
is
SE
U
5
ns
S
–
80.0
21
1.
2.
3.
4.
DESCRIPTION
R
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
TEST
2
#
COND.
FO
PARAMETER
Table 2-0030/2128V
Specifications ispLSI 2128V
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
2
#
-80
DESCRIPTION
-60
MIN. MAX. MIN. MAX.
UNITS
Inputs
20 Input Buffer Delay
–
0.4
–
0.6
21 Dedicated Input Delay
–
1.3
–
1.4
22 GRP Delay
–
1.2
–
2.1
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
–
5.8
–
9.6
ns
24 4 Product Term Bypass Path Delay (Registered)
–
7.5
–
10.3
ns
25 1 Product Term/XOR Path Delay
–
9.2
–
12.3
ns
–
9.5
–
12.3
ns
–
11.3
–
14.4
ns
–
0.3
–
1.3
ns
0.2
–
0.2
–
ns
5.4
–
8.0
–
ns
–
1.6
–
1.6
ns
–
2.5
–
2.8
ns
–
5.6
–
9.3
ns
GRP
tgrp
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
27 XOR Adjacent Path Delay 3
28 GLB Register Bypass Delay
N
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
R
31 GLB Register Clock to Output Delay
FO
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
–
8.5
–
10.4
ns
5.6
6.5
9.3
ns
–
1.4
–
1.5
ns
–
0.4
–
0.5
ns
38 Output Buffer Delay
–
2.2
–
2.2
ns
39 Output Slew Limited Delay Adder
–
VE
28
36 ORP Delay
37 ORP Bypass Delay
21
Outputs
12.2
–
12.2
ns
40 I/O Cell OE to Output Enabled
–
4.9
–
4.9
ns
41 I/O Cell OE to Output Disabled
–
4.9
–
4.9
ns
42 Global Output Enable
–
5.1
–
7.1
ns
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
2.3
2.3
4.2
4.2
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.3
2.3
4.2
4.2
ns
–
7.9
–
9.5
ns
SE
is
pL
SI
tob
tsl
toen
todis
tgoe
ns
3.8
35 GLB Product Term Clock Delay
torp
torpbp
tgy0
tgy1/2
EW
26 20 Product Term/XOR Path Delay
ORP
Clocks
D
GLB
ns
S
ES
IG
N
tio
tdin
Global Reset
45 Global Reset to GLB
U
tgr
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
Table 2-0036/2128V
Specifications ispLSI 2128V
ispLSI 2128V Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Comb 4 PT Bypass #23
#21
I/O Delay
GRP
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#20
#22
#24
#28
#37
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
#25, 26, 27
Q
#36
RST
#45
#29, 30,
31, 32
D
Reset
EW
Control RE
PTs
OE
#33, 34, CK
35
#43, 44
Y0,1,2
#42
R
N
GOE 0
tco
Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.4 + 1.2 + 5.6) + (5.4) - (0.4 + 1.2 + 9.5)
=
=
=
12.4 ns =
VE
=
=
=
=
28
1.5 ns
Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.4 + 1.2 + 9.5) + (0.2) - (0.4 + 1.2 + 3.8)
Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.4 + 1.2 + 5.6) + (1.6) + (1.4 + 2.2)
21
th
=
=
=
=
SI
5.9 ns
FO
Derivations of tsu, th and tco from the Product Term Clock
tsu
pL
Note: Calculations are based upon timing specifications for the ispLSI 2128V-80L.
U
SE
is
Table 2-0042/2128V
7
#38,
39
ES
IG
N
I/O Pin
(Input)
I/O Pin
(Output)
S
Ded. In
#40, 41
0491/2032
Specifications ispLSI 2128V
Power Consumption
Figure 3 shows the relationship between power and
operating speed.
Power consumption in the ispLSI 2128V device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
S
Figure 3. Typical Device Power Consumption vs fmax
ES
IG
N
275
ICC (mA)
250
ispLSI 2128V
225
175
0
20
40
60
80
fmax (MHz)
N
Notes: Configuration of eight 16-bit counters
Typical current at 3.3V, 25° C
EW
D
200
R
ICC can be estimated for the ispLSI 2128V using the following equation:
FO
ICC (mA) = 40 + (# of PTs * 0.6) + (# of nets * Max freq * 0.004)
VE
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
21
28
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption
of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is
sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127/2128V
SI
Power-up Considerations
When Lattice 3.3V 2000V devices are used in mixed 5V/
3.3V applications, some consideration needs to be given
to the power-up sequence. When the I/O pins on the
3.3V ispLSI devices are driven directly by 5V devices, a
low impedance path can exist on the 3.3V device between its I/O and Vcc pins when the 3.3V supply is not
present. This low impedance path can cause current to
flow from the 5V device into the 3.3V ispLSI device. The
maximum current occurs when the signals on the I/O pins
are driven high by the 5V devices. If a large enough
current flows through the 3.3V I/O pins, latch-up can
occur and permanent device damage may result.
SE
is
pL
This latch-up condition occurs only during the power-up
sequence when the 5V supply comes up before the 3.3V
supply. The Lattice 3.3V ispLSI devices are guaranteed
to withstand 5V interface signals within the device operating Vcc range of 3.0V to 3.6V.
The recommended power-up options are as follows:
U
Option 1: Ensure that the 3.3V supply is powered-up and
stable before the 5V supply is powered up.
Option 2: Ensure that the 5V device outputs are driven to
a high impedance or logic low state during power-up.
8
Specifications ispLSI 2128V
Pin Description
160-PIN PQFP PIN NUMBERS 176-PIN TQFP PIN NUMBERS
141,
61,
17
GOE 0, GOE 1
100,
21
RESET
19
Y0, Y1, Y2
18,
ispEN
23
TDI/IN 0
24
TCK/IN 3
97
29,
34,
40,
47,
52,
58,
63,
74,
80,
85,
92,
98,
103,
118,
123,
129,
136,
141,
147,
158,
163,
169,
174,
5,
11,
16,
30,
35,
41,
48,
53,
59,
70,
75,
81,
86,
93,
99,
104,
119,
125,
130,
137,
142,
148,
159,
164,
170,
176,
6,
12,
17
31,
37,
42,
49,
54,
60,
71,
76,
82,
88,
94,
100,
105,
120,
126,
132,
138,
144,
149,
160,
165,
171,
1,
7,
13,
114,
155,
67,
19
110,
23
21
103,
20,
98
32,
38,
44,
50,
56,
61,
72,
77,
83,
89,
95,
101,
116,
121,
127,
133,
139,
145,
150,
161,
167,
172,
3,
8,
14,
113,
108
25
VE
28
21
pL
SI
107
66
140
154
U
GND
VCC
NC1
22,
122,
2,
101,
102
62,
42,
139, 159
20,
39,
119, 142
79,
99,
59,
82,
Global Output Enable input pins
Input Dedicated in-system programming
Boundary Scan enable input pin. This pin is
brought low to enable the programming
mode. The TMS, TDI, TDO and TCK
controls become active.
Input This pin performs two functions.
When ispEN is logic low, it functions as a
serial data input pin to load programming
data into the device. When ispEN is high,
it functions as a dedicated input pin.
Input This pin performs two functions.
When ispEN is logic low, it functions as a
clock pin for the ISP/Boundary Scan state
machine.When ispEN is high, it functions as
a dedicated input pin.
Input This pin performs two functions.
When ispEN is logic low, it functions as a
mode control pin for the ISP/Boundary Scan
state machine. When ispEN is high, it
functions as a dedicated input pin.
Output/Input This pin performs two
functions. When ispEN is logic low, it
functions as an output pin to read serial
shift register data. When ispEN is high, it
functions as a dedicated input pin.
26
60
Dedicated input pins to the device
Active Low (0) Reset pin which resets all
the registers in the device.
Dedicated Clock input. This clock input is
connected to one of the clock inputs of
all the GLBs in the device.
SE
TDO/IN 2
is
TMS/IN 1
Input/Output Pins - These are the general
purpose I/O pins used by the logic array.
S
104,
28,
33,
39,
45,
51,
57,
62,
73,
79,
84,
91,
96,
102,
117,
122,
128,
135,
140,
146,
151,
162,
168,
173,
4,
10,
15,
DESCRIPTION
ES
IG
N
IN 4 - IN 7
29,
34,
40,
46,
51,
56,
65,
70,
75,
81,
87,
92,
105,
110,
115,
121,
127,
132,
137,
146,
151,
156,
3,
8,
13,
D
28,
33,
38,
45,
50,
55,
64,
69,
74,
80,
86,
91,
96,
109,
114,
120,
126,
131,
136,
145,
150,
155,
1,
7,
12,
EW
27,
32,
37,
44,
49,
54,
63,
68,
73,
78,
85,
90,
95,
108,
113,
118,
125,
130,
135,
144,
149,
154,
160,
6,
11,
16
N
26,
31,
36,
43,
48,
53,
58,
67,
72,
77,
84,
89,
94,
107,
112,
117,
124,
129,
134,
143,
148,
153,
158,
5,
10,
15,
R
I/O 0 - I/O 4
I/O 5 - I/O 9
I/O 10 - I/O 14
I/O 15 - I/O 19
I/O 20 - I/O 24
I/O 25 - I/O 29
I/O 30 - I/O 34
I/O 35 - I/O 39
I/O 40 - I/O 44
I/O 45 - I/O 49
I/O 50 - I/O 54
I/O 55 - I/O 59
I/O 60 - I/O 64
I/O 65 - I/O 69
I/O 70 - I/O 74
I/O 75 - I/O 79
I/O 80 - I/O 84
I/O 85 - I/O 89
I/O 90 - I/O 94
I/O 95 - I/O 99
I/O 100 - I/O 104
I/O 105 - I/O 109
I/O 110 - I/O 114
I/O 115 - I/O 119
I/O 120 - I/O 124
I/O 125 - I/O 127
25,
30,
35,
41,
47,
52,
57,
66,
71,
76,
83,
88,
93,
106,
111,
116,
123,
128,
133,
138,
147,
152,
157,
4,
9,
14,
FO
NAME
24,
134,
2,
111,
46,
68,
153, 175
22,
43,
131, 156
87,
109,
Ground (GND)
65,
90,
Vcc
9,
64,
112,
157,
18,
69,
115,
166
36, 55,
97, 106,
143, 152,
27,
78,
124,
No Connect.
Table 2-0002A/2128V
1. NC pins are not to be connected to any active signal, VCC or GND.
9
Specifications ispLSI 2128V
Pin Description
27,
31,
35,
39,
46,
50,
54,
58,
69,
73,
77,
81,
4,
8,
12,
16,
28,
32,
36,
40,
47,
51,
55,
59,
70,
74,
78,
82,
5,
9,
13,
17,
29,
33,
37,
41,
48,
52,
56,
60,
71,
75,
79,
83,
6,
10,
14,
18
IN 4 - IN 7
17,
22,
27,
32,
40,
45,
49,
55,
67,
72,
77,
82,
90,
95,
99,
5,
18,
23,
28,
33,
41,
46,
51,
56,
68,
73,
78,
83,
91,
96,
1,
6,
19,
24,
29,
34,
42,
47,
52,
57,
69,
74,
79,
84,
92,
97,
2,
7,
66,
88, 38,
20,
26,
30,
35,
43,
48,
53,
58,
70,
76,
80,
85,
93,
98,
3,
8
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by
the logic array.
S
26,
30,
34,
38,
45,
49,
53,
57,
68,
72,
76,
80,
3,
7,
11,
15,
ES
IG
N
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
100-PIN TQFP
PIN NUMBERS
D
84-PIN PLCC
PIN NUMBERS
NAME
Dedicated input pins to the device
9
64,
22
62,
13
Global Output Enable input pins
RESET
Y0, Y1, Y2
20
19,
67, 62
11
10,
65, 60
Active Low (0) Reset pin which resets all the registers in the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs in the device.
ispEN
24
15
TDI/IN 0
25
16
TCK/IN 3
61
59
TMS/IN 1
43
37
TDO/IN 2
1
87
GND
23, 44,
VCC
2,
NC1
66
N
EW
GOE 0, GOE 1
R
FO
VE
28
84
14, 39,
61,
86
Ground (GND)
65
12, 36, 63,
89
Vcc
4, 21, 25,
44, 50, 54,
71, 75, 81,
100
31,
64,
94,
No Connect.
pL
SI
21, 42,
21
63,
Input — Dedicated in-system programming Boundary Scan enable input
pin. This pin is brought low to enable the programming mode. The TMS,
TDI, TDO and TCK controls become active.
Input — This pin performs two functions. When ispEN is logic low, it
functions as a serial data input pin to load programming data into the
device. When ispEN is high, it functions as a dedicated input pin.
Input — This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the ISP/Boundary Scan state machine.
When ispEN is high, it functions as a dedicated input pin.
Input — This pin performs two functions. When ispEN is logic low, it
functions as a mode control pin for the ISP/Boundary Scan state
machine. When ispEN is high, it functions as a dedicated input pin.
Output/Input — This pin performs two functions. When ispEN is logic
low, it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
U
SE
is
1. NC pins are not to be connected to any active signal, VCC or GND.
10
Table 2-0002B/2128V
Specifications ispLSI 2128V
Pin Configuration
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
I/O 78
VCC
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
NC1
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
NC1
IN 4
Y1
NC1
VCC
GOE 0
GND
Y2
TCK/IN 3
NC1
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
NC1
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
VCC
I/O 49
EW
D
ES
IG
N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
SI
21
28
VE
FO
R
Top View
N
ispLSI 2128V
is
I/O 15
GND
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
NC1
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
NC1
VCC
TMS/IN 1
IN 6
GND
NC1
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
NC1
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
GND
I/O 48
pL
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
I/O 113
VCC
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
1NC
I/O 120
I/O 121
I/O 122
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
1
NC
IN 7
Y0
RESET
VCC
GOE 1
GND
ispEN
TDI/IN 0
1NC
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1NC
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
VCC
I/O 14
S
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
I/O 112
GND
I/O 111
I/O 110
I/O 109
I/O 108
I/O 107
I/O 106
I/O 105
I/O 104
NC1
I/O 103
I/O 102
I/O 101
I/O 100
I/O 99
I/O 98
I/O 97
I/O 96
NC1
VCC
IN 5
TDO/IN 2
GND
NC1
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
I/O 89
I/O 88
NC1
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
GND
I/O 79
ispLSI 2128V 176-Pin TQFP Pinout Diagram
176-TQFP/2128V
U
SE
1. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 2128V
Pin Configuration
ES
IG
N
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
S
I/O 112
GND
I/O 111
I/O 110
I/O 109
I/O 108
I/O 107
I/O 106
I/O 105
I/O 104
I/O 103
I/O 102
I/O 101
I/O 100
I/O 99
I/O 98
I/O 97
I/O 96
VCC
IN 5
TDO/IN 2
GND
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
GND
I/O 79
ispLSI 2128V 160-Pin PQFP Pinout Diagram
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
N
EW
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
FO
R
ispLSI 2128V
SI
21
28
VE
Top View
I/O 15
GND
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
VCC
TMS/IN 1
IN 6
GND
I/O 32
I/O 34
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
GND
I/O 48
SE
is
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
pL
I/O 113
VCC
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
I/O 120
I/O 121
I/O 122
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
IN 7
Y0
RESET
VCC
GOE 1
GND
ispEN
TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
VCC
I/O 14
160-PQFP/2128LV
U
1. NC pins are not to be connected to any active signal, VCC or GND.
12
I/O 78
VCC
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
IN 4
Y1
NC1
VCC
GOE 0
GND
Y2
TCK/IN 3
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
VCC
I/O 49
Specifications ispLSI 2128V
Pin Configuration
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
28
VE
FO
R
Top View
N
ispLSI 2128V
EW
D
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC1
I/O 38
I/O 37
I/O 36
NC1
I/O 35
I/O 34
I/O 33
I/O 32
IN 4
Y1
NC1
VCC
GOE 0
GND
Y2
TCK/IN 3
I/O 31
I/O 30
I/O 29
I/O 28
NC1
I/O 27
I/O 26
I/O 25
pL
SI
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
1
NC
I/O 12
I/O 13
I/O 14
I/O 15
VCC
TMS/IN 1
IN 6
GND
I/O 16
I/O 17
I/O 18
I/O 19
1
NC
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
1
NC
21
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O 57
I/O 58
I/O 59
1
NC
I/O 60
I/O 61
I/O 62
I/O 63
IN 7
Y0
RESET
VCC
GOE 1
GND
ispEN
TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
1
NC
I/O 4
I/O 5
I/O 6
1
NC
ES
IG
N
S
NC1
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
NC1
I/O 51
I/O 50
I/O 49
I/O 48
VCC
IN 5
TDO/IN 2
GND
I/O 47
I/O 46
I/O 45
I/O 44
NC1
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
ispLSI 2128V 100-Pin TQFP Pinout Diagram
is
100-TQFP/2128V
U
SE
1. NC pins are not to be connected to any active signals, VCC or GND.
13
Specifications ispLSI 2128V
Pin Configuration
13
I/O 59
14
I/O 60
15
I/O 61
16
I/O 62
17
I/O 63
18
Y0
19
RESET
20
VCC
21
GOE 1
22
ispLSI 2128V
Top View
26
I/O 1
27
I/O 2
28
I/O 3
29
I/O 4
30
I/O 5
31
I/O 6
32
EW
N
R
I/O 0
FO
25
VE
TDI/IN 0
28
24
21
23
S
74
I/O 38
73
I/O 37
72
I/O 36
71
I/O 35
70
I/O 34
69
I/O 33
68
I/O 32
67
Y1
66
NC1
65
VCC
64
GOE 0
63
GND
62
Y2
61
TCK/IN 3
60
I/O 31
59
I/O 30
58
I/O 29
57
I/O 28
56
I/O 27
55
I/O 26
54
I/O 25
SI
GND
I/O 39
ES
IG
N
12
I/O 58
D
I/O 57
ispEN
I/O 40
1 84 83 82 81 80 79 78 77 76 75
I/O 41
2
I/O 42
TDO/IN 2
3
I/O 43
VCC
4
I/O 44
I/O 48
5
I/O 45
I/O 49
6
I/O 46
I/O 50
7
I/O 47
I/O 51
8
GND
I/O 52
11 10 9
I/O 53
I/O 54
I/O 55
I/O 56
ispLSI 2128V 84-Pin PLCC Pinout Diagram
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
GND
I/O 16
TMS/IN1
VCC
I/O 15
I/O 14
I/O 13
I/O 12
I/O 11
I/O 9
I/O 8
I/O 10
is
I/O 7
pL
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
SE
1. NC pins are not to be connected to any active signals, VCC or GND.
U
0123/2128V
14
Specifications ispLSI 2128V
Part Number Description
ispLSI
2128V – XX
X
XXXX X
Device Family
Grade
Blank = Commercial
I = Industrial
Package
T176 = 176-Pin TQFP
Q160 = 160-Pin PQFP
T100 = 100-Pin TQFP
J84 = 84-Pin PLCC
S
Device Number
ES
IG
N
Speed
80 = 80 MHz fmax
60 = 60 MHz fmax
ispLSI 2128V Ordering Information
tpd (ns)
I/Os
ORDERING NUMBER
PACKAGE
80
10
128
ispLSI 2128V-80LT176
176-Pin TQFP
80
10
128
ispLSI 2128V-80LQ160
160-Pin PQFP
80
10
64
ispLSI 2128V-80LT100
100-Pin TQFP
80
10
64
ispLSI 2128V-80LJ84
84-Pin PLCC
60
15
128
ispLSI 2128V-60LT176
176-Pin TQFP
60
15
128
ispLSI 2128V-60LQ160
160-Pin PQFP
60
15
64
ispLSI 2128V-60LT100
100-Pin TQFP
60
15
64
ispLSI 2128V-60LJ84
84-Pin PLCC
FO
VE
INDUSTRIAL
tpd (ns)
I/Os
ORDERING NUMBER
PACKAGE
60
15
128
ispLSI 2128V-60LT176I
176-Pin TQFP
15
64
ispLSI 2128V-60LT100I
100-Pin TQFP
pL
ispLSI
Table 2-0041A/2128V
fmax (MHz)
SI
FAMILY
28
*Contact factory for availability.
R
fmax (MHz)
21
ispLSI
N
COMMERCIAL
FAMILY
0212/2128V
EW
D
Power
L = Low
Table 2-0041B/2128V
U
SE
is
60
15