ETC ISPLSI2096V

®
ispLSI 2096V
3.3V High Density Programmable Logic
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• 3.3V LOW VOLTAGE 2096 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
— Fuse Map Compatible with 5V ispLSI 2096
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 80 MHz Maximum Operating Frequency
— tpd = 10 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C7
C6
C5
C4
Output Routing Pool (ORP)
C3
C2
C1
C0
A0
B7
D Q
A1
A2
GLB
Logic
Array
B6
D Q
Global Routing Pool
(GRP)
D Q
B5
D Q
A3
B4
A4
A5
A6
A7
Output Routing Pool (ORP)
B0
B1
B2
Output Routing Pool (ORP)
Features
B3
Output Routing Pool (ORP)
0919/2096V
Description
The ispLSI 2096V is a High Density Programmable Logic
Device containing 96 Registers, six Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2096V features in-system
programmability through the Boundary Scan Test Access Port (TAP). The ispLSI 2096V offers non-volatile
reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2096V device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2096v_08
1
February 2000
Specifications ispLSI 2096V
Functional Block Diagram
Megablock
Generic Logic
Blocks (GLBs)
TDI/IN 0
TMS/IN 1
C7
C3
C0
C1
C2
IN 5
IN 4
I/O 67
I/O 66
I/O 65
I/O 64
I/O 71
I/O 70
I/O 69
I/O 68
I/O 75
I/O 74
I/O 73
I/O 72
I/O 79
I/O 78
I/O 77
I/O 76
I/O 83
I/O 82
I/O 81
I/O 80
I/O 87
I/O 86
I/O 85
I/O 84
C4
C5
C6
I/O 63
I/O 62
I/O 61
I/O 60
Global
Routing
Pool
(GRP)
A1
A2
B6
B5
A3
Input Bus
B7
A6
A5
A7
Output Routing Pool (ORP)
RESET
B2
B1
B0
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
B4
A4
I/O 59
I/O 58
I/O 57
I/O 56
B3
Output Routing Pool (ORP)
CLK 0
CLK 1
CLK 2
I/O 12
I/O 13
I/O 14
I/O 15
Output Routing Pool (ORP)
I/O 8
I/O 9
I/O 10
I/O 11
Input Bus
Output Routing Pool (ORP)
A0
Input Bus
I/O 4
I/O 5
I/O 6
I/O 7
Input Bus
Output Routing Pool (ORP)
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 91
I/O 90
I/O 89
I/O 88
I/O 95
I/O 94
I/O 93
I/O 92
GOE 1
GOE 0
Figure 1. ispLSI 2096V Functional Block Diagram
Input Bus
Input Bus
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 5-volt signal levels to
support mixed-voltage systems.
0917/2096V
Y0
Y1
Y2
I/O 44
I/O 45
I/O 46
I/O 47
I/O 40
I/O 41
I/O 42
I/O 43
I/O 36
I/O 37
I/O 38
I/O 39
I/O 32
I/O 33
I/O 34
I/O 35
TDO/IN 2
TCK/IN 3
I/O 28
I/O 29
I/O 30
I/O 31
I/O 24
I/O 25
I/O 26
I/O 27
I/O 20
I/O 21
I/O 22
I/O 23
I/O 16
I/O 17
I/O 18
I/O 19
ispEN
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a programmable fuse. When this fuse is erased (JEDEC “1”),
the output is configured as a totem-pole output. When
this fuse is programmed (JEDEC “0”), the output is
configured as an open-drain. The default configuration
when the device is in bulk erased state is totem-pole
configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096V device contains three Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2096V device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2096V are individually programmable, either as a standard totem-pole output or an
2
Specifications ispLSI 2096V
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +5.6V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
VCC
Supply Voltage
VIL
VIH
Input Low Voltage
MIN.
MAX.
UNITS
Commercial
TA = 0°C to + 70°C
3.0
3.6
V
Industrial
TA = -40°C to + 85°C
3.0
3.6
V
0.8
V
VSS – 0.5
Input High Voltage
2.0
5.25
V
Table 2-0005/2096V
Capacitance (TA=25°C, f=1.0 MHz)
TYPICAL
UNITS
Dedicated Input Capacitance
10
pf
VCC = 3.3V, VIN = 2.0V
I/O Capacitance
10
pf
VCC = 3.3V, VI/O = 2.0V
Clock and Global Output Enable Capacitance
13
pf
VCC = 3.3V, VY = 2.0V
SYMBOL
C1
C2
C3
PARAMETER
TEST CONDITIONS
Table 2-0006/2096V
Data Retention Specifications
PARAMETER
MINIMUM
MAXIMUM
UNITS
20
–
Years
10000
–
Cycles
Data Retention
ispLSI Erase/Reprogram Cycles
Table 2-0008/2096V
3
Specifications ispLSI 2096V
Switching Test Conditions
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
≤ 3ns 10% to 90%
Input Rise and Fall Time
Input Timing Reference Levels
+ 3.3V
1.5V
Output Timing Reference Levels
1.5V
Output Load
R1
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
Device
Output
Table 2-0003/2096V
Test
Point
R2
CL*
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
R2
CL
316Ω
348Ω
35pF
Active High
∞
348Ω
35pF
Active Low
A
B
C
*CL includes Test Fixture and Probe Capacitance.
0213A/2128V
316Ω
348Ω
35pF
Active High to Z
at VOH -0.5V
∞
348Ω
5pF
Active Low to Z
at VOL +0.5V
316Ω
348Ω
5pF
Table 2-0004/2128V
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
VOL
VOH
IIL
PARAMETER
CONDITION
3
MIN.
TYP.
MAX. UNITS
Output Low Voltage
IOL= 8 mA
—
—
0.4
V
Output High Voltage
IOH = -4 mA
2.4
—
—
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
—
—
-10
µA
(VCC — 0.2)V ≤ V
CC
IN ≤ V
—
—
10
A
VCC ≤ VIN ≤ 5.25V
—
—
50
mA
µA
IIH
Input or I/O High Leakage Current
IIL-isp
IIL-PU
IOS1
ispEN Input Low Leakage Current
0V ≤ VIN ≤ VIL
—
—
-150
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
—
—
-150
µA
Output Short Circuit Current
VCC = 3.3V, VOUT = 0.5V
—
—
-100
mA
ICC2, 4
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
—
140
—
mA
fCLOCK = 1 MHz
Table 2-0007A/2096V
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at VCC = 3.3V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC .
4
Specifications ispLSI 2096V
External Timing Parameters
Over Recommended Operating Conditions
4
PARAMETER
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
1.
2.
3.
4.
TEST
2
#
COND.
DESCRIPTION
-80
1
-60
MIN. MAX. MIN. MAX.
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
A
2
Data Propagation Delay
A
3
Clock Frequency with Internal Feedback
–
4
–
–
–
10.0
–
15.0
UNITS
ns
–
15.0
–
20.0
ns
80.0
–
61.7
–
MHz
Clock Frequency with External Feedback ( tsu2 + tco1)
64.5
–
51.3
–
MHz
5
Clock Frequency, Max. Toggle
100
–
71.4
–
MHz
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
7.0
–
9.0
–
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
6.5
–
8.5
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
ns
–
9
GLB Reg. Setup Time before Clock
9.0
–
11.0
–
ns
–
10 GLB Reg. Clock to Output Delay
–
7.5
–
9.5
ns
–
11 GLB Reg. Hold Time after Clock
0.0
–
0.0
–
ns
A
12 Ext. Reset Pin to Output Delay
–
13 Ext. Reset Pulse Duration
3
1
–
14.0
–
16.0
ns
7.0
–
8.0
–
ns
B
14 Input to Output Enable
–
15.0
–
18.0
ns
C
15 Input to Output Disable
–
15.0
–
18.0
ns
B
16 Global OE Output Enable
–
10.0
–
12.0
ns
C
17 Global OE Output Disable
–
10.0
–
12.0
ns
–
18 External Synchronous Clock Pulse Duration, High
5.0
–
7.0
–
ns
–
19 External Synchronous Clock Pulse Duration, Low
5.0
–
7.0
–
ns
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
5
Table 2-0030/2096V
Specifications ispLSI 2096V
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
2
#
DESCRIPTION
-60
-80
MIN. MAX. MIN. MAX.
UNITS
Inputs
tio
tdin
20 Input Buffer Delay
–
0.4
–
0.6
ns
21 Dedicated Input Delay
–
1.3
–
1.4
ns
22 GRP Delay
–
1.2
–
2.1
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
–
5.8
–
9.6
ns
24 4 Product Term Bypass Path Delay (Registered)
–
7.5
–
10.3
ns
25 1 Product Term/XOR Path Delay
–
9.2
–
12.3
ns
26 20 Product Term/XOR Path Delay
–
9.5
–
12.3
ns
–
11.3
–
14.4
ns
–
0.3
–
1.3
ns
29 GLB Register Setup Time befor Clock
0.2
–
0.2
–
ns
30 GLB Register Hold Time after Clock
5.4
–
8.0
–
ns
31 GLB Register Clock to Output Delay
–
1.6
–
1.6
ns
32 GLB Register Reset to Output Delay
–
2.5
–
2.8
ns
33 GLB Product Term Reset to Register Delay
–
5.6
–
9.3
ns
34 GLB Product Term Output Enable to I/O Cell Delay
–
8.5
–
10.4
ns
3.8
5.6
6.5
9.3
ns
36 ORP Delay
–
1.4
–
1.5
ns
37 ORP Bypass Delay
–
0.4
–
0.5
ns
38 Output Buffer Delay
–
2.2
–
2.2
ns
39 Output Slew Limited Delay Adder
–
12.2
–
12.2
ns
40 I/O Cell OE to Output Enabled
–
4.9
–
4.9
ns
41 I/O Cell OE to Output Disabled
–
4.9
–
4.9
ns
42 Global Output Enable
–
5.1
–
7.1
ns
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
2.3
2.3
4.2
4.2
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.3
2.3
4.2
4.2
ns
–
7.9
–
9.5
ns
GRP
tgrp
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
27 XOR Adjacent Path Delay
3
28 GLB Register Bypass Delay
35 GLB Product Term Clock Delay
ORP
torp
torpbp
Outputs
tob
tsl
toen
todis
tgoe
Clocks
tgy0
tgy1/2
Global Reset
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
Table 2-0036/2096V
Specifications ispLSI 2096V
ispLSI 2096V Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
Comb 4 PT Bypass #23
#21
I/O Pin
(Input)
I/O Delay
GRP
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#20
#22
#24
#28
#37
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
#25, 26, 27
Q
#38,
39
#36
RST
#45
Reset
#29, 30,
31, 32
Control RE
PTs
OE
#33, 34, CK
35
#40, 41
#43, 44
Y0,1,2
#42
GOE 0
0491/2032
Derivations of tsu, th and tco from the Product Term Clock
tsu
5.9 ns
th
1.5 ns
tco
=
=
=
=
Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.4 + 1.2 + 9.5) + (0.2) - (0.4 + 1.2 + 3.8)
=
=
=
=
Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.4 + 1.2 + 5.6) + (5.4) - (0.4 + 1.2 + 9.5)
=
=
=
12.4 ns =
Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.4 + 1.2 + 5.6) + (1.6) + (1.4 + 2.2)
Note: Calculations are based upon timing specifications for the ispLSI 2096V-80L.
Table 2-0042/2096V
7
I/O Pin
(Output)
Specifications ispLSI 2096V
Power Consumption
Figure 3 shows the relationship between power and
operating speed.
Power consumption in the ispLSI 2096V device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax
ICC (mA)
200
ispLSI 2096V
180
160
140
120
0
20
40
60
80
100
fmax (MHz)
Notes: Configuration of six 16-bit counters
Typical current at 3.3V, 25° C
ICC can be estimated for the ispLSI 2096V using the following equation:
ICC (mA) = 20.2 + (# of PTs * 0.611) + (# of nets * Max freq * 0.0063)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two
GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to
operating conditions and the program in the device, the actual ICC should be verified.
0127/2096V
Power-up Considerations
When Lattice 3.3V 2000V devices are used in mixed 5V/
3.3V applications, some consideration needs to be given
to the power-up sequence. When the I/O pins on the
3.3V ispLSI devices are driven directly by 5V devices, a
low impedance path can exist on the 3.3V device between its I/O and Vcc pins when the 3.3V supply is not
present. This low impedance path can cause current to
flow from the 5V device into the 3.3V ispLSI device. The
maximum current occurs when the signals on the I/O pins
are driven high by the 5V devices. If a large enough
current flows through the 3.3V I/O pins, latch-up can
occur and permanent device damage may result.
This latch-up condition occurs only during the power-up
sequence when the 5V supply comes up before the 3.3V
supply. The Lattice 3.3V ispLSI devices are guaranteed
to withstand 5V interface signals within the device operating Vcc range of 3.0V to 3.6V.
The recommended power-up options are as follows:
Option 1: Ensure that the 3.3V supply is powered-up and
stable before the 5V supply is powered up.
Option 2: Ensure that the 5V device outputs are driven to
a high impedance or logic low state during power-up.
8
Specifications ispLSI 2096V
Pin Description
NAME
PQFP & TQFP PIN NUMBERS
23,
29,
37,
43,
53,
59,
67,
73,
87,
93,
101,
107,
117,
123,
3,
9,
24,
30,
38,
44,
54,
60,
68,
74,
88,
94,
102,
108,
118,
124,
4,
10,
25,
32,
39,
45,
55,
61,
69,
75,
89,
96,
103,
109,
119,
125,
5,
11,
DESCRIPTION
26
33
40
46
56
62
70
76
90
97
104
110
120
126
6
12
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
21,
27,
35,
41,
51,
57,
64,
71,
85,
91,
99,
105,
115,
121,
128,
7,
22,
28,
36,
42,
52,
58,
65,
72,
86,
92,
100,
106,
116,
122,
1,
8,
GOE 0, GOE 1
80,
17
Global Output Enables input pins.
IN 4, IN 5
84,
113
Dedicated input pins to the device.
ispEN
19
Input — Dedicated in-system programming Boundary Scan enable input
pin. This pin is brought low to enable the programming mode. The TMS,
TDI, TDO and TCK controls become active.
TDI/IN 0
20
TMS/IN 1
48
TDO/IN 2
112
TCK/IN 3
77
Input — This pin performs two functions. When ispEN is logic low, it
functions as a serial data input pin to load programming data into the
device. When ispEN is high, it functions as a dedicated input pin.
Input — This pin performs two functions. When ispEN is logic low, it
functions as a mode control pin for the ISP/Boundary Scan state
machine. When ispEN is high, it functions as a dedicated input pin.
Output/Input — This pin performs two functions. When ispEN is logic
low, it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
Input — This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the ISP/Boundary Scan state machine.
When ispEN is high, it functions as a dedicated input pin.
RESET
15
Y0, Y1, Y2
14
83,
78
GND
18,
111,
34,
127
50,
63,
79,
98,
Ground (GND)
VCC
2,
95,
16,
114
31,
47,
66,
81,
VCC
NC1
13,
49,
82
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
No Connect.
1. NC pins are not to be connected to any active signal, VCC or GND.
9
Table 2-0002-2096V
Specifications ispLSI 2096V
Pin Configuration
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
I/O 84
GND
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
VCC
IN 5
TDO/IN 2
GND
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
I/O 59
ispLSI 2096V 128-Pin PQFP and TQFP Pinout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ispLSI 2096V
Top View
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O 58
VCC
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 4
Y1
NC1
VCC
GOE 0
GND
Y2
TCK/IN 3
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
VCC
I/O 37
I/O 11
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
VCC
TMS/IN 1
1NC
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GND
I/O 36
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
I/O 85
VCC
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
1NC
Y0
RESET
VCC
GOE 1
GND
ispEN
TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
VCC
I/O 10
1. NC pins are not to be connected to any active signals, VCC or GND.
10
0124-2096V
Specifications ispLSI 2096V
Part Number Description
ispLSI
2096V – XX
X XXX X
Device Family
Grade
Blank = Commercial
I = Industrial
Package
T128 = 128-Pin TQFP
Q128 = 128-Pin PQFP
Device Number
Speed
80 = 80 MHz fmax
60 = 60 MHz fmax
Power
L = Low
0212/2096V
ispLSI 2096V Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
80
10
ispLSI 2096V-80LT128
128-Pin TQFP
80
10
ispLSI 2096V-80LQ128
128-Pin PQFP
60
15
ispLSI 2096V-60LT128
128-Pin TQFP
60
15
ispLSI 2096V-60LQ128
128-Pin PQFP
ORDERING NUMBER
PACKAGE
Table 2-0041A/2096V
INDUSTRIAL
FAMILY
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
ispLSI
60
15
ispLSI 2096V-60LT128I
128-Pin TQFP
Table 2-0041B/2096V
11