ispMACH™ 4A CPLD Family High Performance E2CMOS® In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature — SpeedLockingTM performance for guaranteed fixed timing — Central, input and output switch matrices for 100% routability and 100% pin-out retention High speed — 5.0ns tPD Commercial and 7.5ns tPD Industrial — 182MHz fCNT 32 to 512 macrocells; 32 to 768 registers 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages Flexible architecture for a wide range of design styles — D/T registers and latches — Synchronous or asynchronous mode — Dedicated input registers — Programmable polarity — Reset/ preset swapping Advanced capabilities for easy system integration — 3.3-V & 5-V JEDEC-compliant operations — JTAG (IEEE 1149.1) compliant for boundary scan testing — 3.3-V & 5-V JTAG in-system programming — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades) — Safe for mixed supply voltage system designs — Programmable pull-up or Bus-FriendlyTM inputs and I/Os — Hot-socketing — Programmable security bit — Individual output slew rate control Advanced E2CMOS process provides high-performance, cost-effective solutions Supported by ispDesignEXPERTTM software for rapid logic development — Supports HDL design methodologies with results optimized for ispMACH 4A — Flexibility to adapt to user requirements — Software partnerships that ensure customer success Lattice and third-party hardware programming support — LatticePROTM software for in-system programmability support on PCs and automated test equipment — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General Publication# ISPM4A Amendment/0 Rev: D Issue Date: August 2000 Table 1. ispMACH 4A Device Features 3.3 V Devices Feature Macrocells User I/O options M4A3-322 M4A3-642 M4A3-962 M4A3-1282 M4A3-1922 32 64 96 128 32 32/641 48 64 M4A3-256 M4A3-3842 M4A3-5121 192 256 384 512 96 1282/1601/1921 160/192 160/192/256 6.5 7.5 tPD (ns) 5.0 5.5 5.5 5.5 6.0 5.53 fCNT (MHz) 182 167 167 167 160 167 154 125 tCOS (ns) 4.0 4.0 4.0 4.0 4.5 4.0 4.5 5.5 tSS (ns) 3.0 3.5 3.5 3.5 3.5 3.5 3.5 5.0 Static Power (mA) 20 25/521 40 55 85 1102/1501 149/155 179 JTAG Compliant Yes Yes Yes Yes Yes Yes Yes Yes PCI Compliant Yes Yes Yes Yes Yes Yes Yes Yes M4A5-322 M4A5-642 M4A5-962 M4A5-1282 M4A5-1921 M4A5-2562 Macrocells 32 64 96 128 192 256 User I/O options 32 32 48 64 96 128 tPD (ns) 5.0 5.5 5.5 5.5 6.0 6.5 fCNT (MHz) 182 167 167 167 160 154 tCOS (ns) 4.0 4.0 4.0 4.0 4.5 5.0 tSS (ns) 3.0 3.5 3.5 3.5 3.5 3.5 Static Power (mA) 20 25 40 55 74 110 JTAG Compliant Yes Yes Yes Yes Yes Yes PCI Compliant Yes Yes Yes Yes Yes Yes 5 V Devices Feature Notes: 1. Advance information. Please contact a Lattice sales representative for details on availability. 2. Preliminary information. 3. M4A3-256/128 available now in 5.5ns. Contact factory for availability of 7.5ns M4A3-256/160 and M4A3-256/192 2 ispMACH 4A Family GENERAL DESCRIPTION The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation. ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity. All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out retention after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A products can deliver guaranteed fixed timing as fast as 5.0 ns tPD and 182 MHz fCNT through the SpeedLocking feature when using up to 20 product terms per output (Table 2). Table 2. ispMACH 4A Speed Grades Speed Grade Device -5 M4A3-323 M4A5-323 -55 -6 -65 C -7 -10 -12 C, I C, I I M4A3-64/323 M4A5-64/323 C C, I C, I I M4A3-64/642 C C, I C, I I C C, I C, I I C C, I C, I I C, I C, I I M4A3-963 M4A5-963 M4A3-1283 M4A5-1283 M4A3-1923 M4A5-1922 C M4A3-256/1283 C M4A5-256/1283 C C, I C, I I C C C, I I C C, I I C, I C, I I C, I C, I I M4A3-256/1922 M4A3-256/1602 M4A3-3842 C M4A3-5122 Notes: 1. C = Commercial, -14 C I = Industrial 2. Advance information. Please contact a Lattice sales representative for details on availability. 3. Preliminary information. ispMACH 4A Family 3 The ispMACH 4A family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), finepitch BGA (fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table 3). It also offers I/O safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-V devices do not overdrive 3.3-V inputs. Additional features include BusFriendly inputs and I/Os, a programmable power-down mode for extra power savings and individual output slew rate control for the highest speed transition or for the lowest noise transition. Table 3. ispMACH 4A Package and I/O Options (Number of I/Os and dedicated inputs in Table) 3.3 V Devices M4A3-322 M4A3-64 44-pin PLCC 32+2 32+22 44-pin TQFP 32+2 32+22 48-pin TQFP 32+2 32+22 Package 64+61 100-pin TQFP M4A3-962 M4A3-128 48+8 64+62 100-pin PQFP 64+62 100-ball caBGA 64+61 M4A3-192 144-pin TQFP 96+162 144-ball fpBGA 96+161 M4A3-256 M4A3-3841 M4A3-5121 208-pin PQFP 128+142, 1601 160 160 256-ball fpBGA 128+142, 1921 192 192 128+142 192 256-ball BGA 388-ball fpBGA 256 5 V Devices M4A5-322 M4A5-642 44-pin PLCC 32+2 32+2 44-pin TQFP 32+2 32+2 48-pin TQFP 32+2 32+2 Package 100-pin TQFP 100-pin PQFP M4A5-962 M4A5-1282 48+8 64+6 M4A5-1921 M4A5-2562 64+6 144-pin TQFP 96+16 208-pin PQFP 128+14 256-ball BGA 128+14 Note: 1. Advance information. Please contact a Lattice sales representative for details on availability. 2. Preliminary information. 4 ispMACH 4A Family FUNCTIONAL DESCRIPTION The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized PAL® blocks interconnected by a central switch matrix. The central switch matrix allows communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL blocks and central switch matrix allow the logic designer to create large designs in a single device instead of having to use multiple devices. The key to being able to make effective use of these devices lies in the interconnect schemes. In the ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the output switch matrix. In addition, more input routing options are provided by the input switch matrix. These resources provide the flexibility needed to fit designs efficiently. PAL Block 4 Dedicated Input Pins Central Switch Matrix Note 3 33/ 34/ 36 Logic Array Logic 16 Output/ Allocator Buried with XOR Macrocells 16 Input Switch Matrix 16 8 Note 1 I/O Cells Clock/Input Pins Output Switch Matrix Note 2 Clock Generator 16 I/O Pins I/O Pins PAL Block PAL Block I/O Pins 17466G-001 Figure 1. ispMACH 4A Block Diagram and PAL Block Structure Notes: 1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page). 2. Block clocks do not go to I/O cells in M4A(3,5)-32/32. 3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do not connect to the central switch matrix. ispMACH 4A Family 5 Table 4. Architectural Summary of ispMACH 4A devices ispMACH 4A Devices M4A3-64/32, M4A5-64/32 M4A3-96/48, M4A5-96/48 M4A3-128/64, M4A5-128/64 M4A3-192/96, M4A5-192/96 M4A3-256/128, M4A5-256/128 M4A3-384 M4A3-512 M4A3-32/32 M4A5-32/32 M4A3-64/64 M4A3-256/160 M4A3-256/192 Macrocell-I/O Cell Ratio 2:1 1:1 Input Switch Matrix Yes Yes1 Input Registers Yes No Central Switch Matrix Yes Yes Output Switch Matrix Yes Yes The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells internally in a PAL block (Table 4). The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through the central switch matrix. This mechanism ensures that PAL blocks in ispMACH 4A devices communicate with each other with consistent, predictable delays. The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL devices on a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single programmable device; the software partitions the design into PAL blocks through the central switch matrix so that the designer does not have to be concerned with the internal architecture of the device. Each PAL block consists of: ◆ ◆ ◆ ◆ ◆ ◆ ◆ Product-term array Logic allocator Macrocells Output switch matrix I/O cells Input switch matrix Clock generator Notes: 1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix. 6 ispMACH 4A Family Product-Term Array The product-term array consists of a number of product terms that form the basis of the logic being implemented. The inputs to the AND gates come from the central switch matrix (Table 5), and are provided in both true and complement forms for efficient logic implementation. Table 5. PAL Block Inputs Device Number of Inputs to PAL Block M4A3-32/32 and M4A5-32/32 M4A3-64/32 and M4A5-64/32 M4A3-64/64 M4A3-96/48 and M4A5-96/48 M4A3-128/64 and M4A5-128/64 33 33 33 33 33 M4A3-192/96 and M4A5-192/96 M4A3-256/128 and M4A5-256/128 34 34 M4A3-256/160 and M4A3-256/192 M4A3-384 M4A3-512 36 36 36 Logic Allocator Within the logic allocator, product terms are allocated to macrocells in “product term clusters.” The availability and distribution of product term clusters are automatically considered by the software as it fits functions within a PAL block. The size of a product term cluster has been optimized to provide high utilization of product terms, making complex functions using many product terms possible. Yet when few product terms are used, there will be a minimal number of unused—or wasted—product terms left over. The product term clusters available to each macrocell within a PAL block are shown in Tables 6 and 7. Each product term cluster is associated with a macrocell. The size of a cluster depends on the configuration of the associated macrocell. When the macrocell is used in synchronous mode (Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in asynchronous mode (Figure 2b), the cluster has 2 product terms. Note that if the product term cluster is routed to a different macrocell, the allocator configuration is not determined by the mode of the macrocell actually being driven. The configuration is always set by the mode of the macrocell that the cluster will drive if not routed away, regardless of the actual routing. In addition, there is an extra product term that can either join the basic cluster to give an extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included with the basic cluster, this provides for up to 20 product terms on a synchronous function that uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18 product terms. When the extra product term is used to extend the cluster, the value of the second XOR input can be programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic allocator are shown in Figures 3 and 4. ispMACH 4A Family 7 Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32) Output Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7, C8 C6, C7, C8, C9 Output Macrocell M8 M9 M10 M11 M12 M13 M14 M15 Available Clusters C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15 Table 7. Logic Allocator for M4A(3,5)-32/32 Output Macrocell M8 M9 M10 M11 M12 M13 M14 M15 Logic Allocator n n To n+1 0 Default From n+1 From n+2 0 Default Extra Product Term Available Clusters C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15 To Macrocell n Basic Product Term Cluster From n-1 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7 C6, C7 To n-1 To n-2 Output Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Prog. Polarity 17466G-005 n Logic Allocator n 0 Default To n+1 Extra Product Term From n+1 From n+2 0 Default To Macrocell n Basic Product Term Cluster From n-1 To n-1 To n-2 a. Synchronous Mode Prog. Polarity b. Asynchronous Mode Figure 2. Logic Allocator: Configuration of Cluster “n” Set by Mode of Macrocell “n” 8 ispMACH 4A Family 17466G-006 a. Basic cluster with XOR b. Extended cluster, active high c. Extended cluster, active low 0 d. Basic cluster routed away; single-product-term, active high e. Extended cluster routed away 17466G-007 Figure 3. Logic Allocator Configurations: Synchronous Mode a. Basic cluster with XOR b. Extended cluster, active high c. Extended cluster, active low 0 d. Basic cluster routed away; single-product-term, active high e. Extended cluster routed away 17466G-008 Figure 4. Logic Allocator Configurations: Asynchronous Mode Note that the configuration of the logic allocator has absolutely no impact on the speed of the signal. All configurations have the same delay. This means that designers do not have to decide between optimizing resources or speed; both can be optimized. If not used in the cluster, the extra product term can act in conjunction with the basic cluster to provide XOR logic for such functions as data comparison, or it can work with the D-,T-type flipflop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to another macrocell, the extra product term is still available for logic. In this case, the first XOR input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without giving up the use of the macrocell. Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the ends of the block have fewer product terms available. ispMACH 4A Family 9 Macrocell The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the macrocell. Power-Up Reset PAL-Block Initialization Product Terms SWAP Common PAL-block resource Individual macrocell resources AP D/T/L From Logic Allocator From PAL-Clock Generator AR Q To Output and Input Switch Matrices Block CLK0 Block CLK1 Block CLK2 Block CLK3 17466G-009 a. Synchronous mode Power-Up Reset Individual Initialization Product Term AP AR Q D/T/L From Logic Allocator From PAL-Block Clock Generator To Output and Input Switch Matrices Block CLK0 Block CLK1 Individual Clock Product Term b. Asynchronous mode 17466G-010 Figure 5. Macrocell In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will generally be used, since it provides more product terms in the allocator. 10 ispMACH 4A Family The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs are HIGH. AP AR D Q AP AR D Q b. D-type with programmable D polarity a. D-type with XOR L AP AR L Q AP AR Q G G c. Latch with XOR d. Latch with programmable D polarity AP AR T Q f. Combinatorial with XOR e. T-type with programmable T polarity g. Combinatorial with programmable polarity 17466G-011 Figure 6. Primary Macrocell Configurations ispMACH 4A Family 11 Table 8. Register/Latch Operation Input(s) CLK/LE 1 Q+ D-type Register D=X D=0 D=1 0,1, ↓ (↑) ↑ (↓) ↑ (↓) Q 0 1 T-type Register T=X T=0 T=1 0, 1, ↓ (↑) ↑ (↓) ↑ (↓) Q Q Q D-type Latch D=X D=0 D=1 1(0) 0(1) 0(1) Q 0 1 Configuration Note: 1. Polarity of CLK/LE can be programmed Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product terms are divided between J and K (or S and R). When configured as J-K, S-R, or T-type, the extra product term must be used on the XOR gate input for flip-flop emulation. In any register type, the polarity of the inputs can be programmed. The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode, with the additional choice of either polarity of an individual product term clock in the asynchronous mode. The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous reset and preset are provided, each driven by a product term common to the entire PAL block. Power-Up Reset Power-Up Preset PAL-Block Initialization Product Terms PAL-Block Initialization Product Terms AP D/T/L AR Q AP D/L b. Power-up preset a. Power-up reset 17466G-012 Figure 7. Synchronous Mode Initialization Configurations 12 AR Q ispMACH 4A Family 17466G-013 A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization. It can be selected to control reset or preset. Power-Up Preset Power-Up Reset Individual Preset Product Term Individual Reset Product Term AP D/L/T AP D/L/T AR Q a. Reset AR Q b. Preset 17466G-014 17466G-015 Figure 8. Asynchronous Mode Initialization Configurations Note that the reset/preset swapping selection feature effects power-up reset as well. The initialization functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data to the output switch matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired. The input switch matrix can send the signal back to the central switch matrix as feedback. Table 9. Asynchronous Reset/Preset Operation AR AP CLK/LE1 Q+ 0 0 X See Table 8 0 1 X 1 1 0 X 0 1 1 X 0 Note: 1. Transparent latch is unaffected by AR, AP ispMACH 4A Family 13 Output Switch Matrix The output switch matrix allows macrocells to be connected to any of several I/O cells within a PAL block. This provides high flexibility in determining pinout and allows design changes to occur without effecting pinout. In ispMACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as many macrocells as I/O cells. The ispMACH 4A output switch matrix allows for half of the macrocells to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can choose from eight macrocells; each macrocell has a choice of four I/O cells. The ispMACH 4A devices with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/O cells (Figure 9). M0 I/O cell MUX macrocells I/O0 M0 I/O0 I/O1 M1 M1 I/O1 M1 M2 M2 I/O2 M2 I/O2 M3 M3 I/O3 M3 I/O3 M4 I/O4 M4 I/O4 I/O5 M4 Each I/O cell can choose one of 8 macrocells in all ispMACH 4A devices. M0 I/O0 M5 I/O1 M5 I/O5 M5 M6 I/O2 M6 I/O6 M6 I/O6 M7 I/O3 M7 I/O7 M7 I/O7 M8 I/O4 M8 I/O8 M8 I/O8 M9 I/O5 M9 I/O9 M9 I/O9 M10 I/O6 M10 I/O10 M10 I/O10 M11 I/O7 M11 I/O11 M11 I/O11 M12 M12 I/O12 M12 I/O12 M13 M13 I/O13 M13 I/O13 M14 M14 I/O14 M14 I/O14 M15 M15 I/O15 M15 I/O15 Each macrocell can drive one of 4 I/O cells in ispMACH 4A devices with 2:1 macrocell-I/O cell ratio. Each macrocell can drive one of 8 I/O cells in ispMACH 4A devices with 1:1 macrocell-I/O cell ratio except M4A(3, 5)-32/32 devices. Each macrocell can drive one of 8 I/O cells in M4A(3, 5)-32/32 devices. Figure 9. ispMACH 4A Output Switch Matrix Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio 14 Macrocell Routable to I/O Cells M0, M1 I/O0, I/O5, I/O6, I/O7 M2, M3 I/O0, I/O1, I/O6, I/O7 M4, M5 I/O0, I/O1, I/O2, I/O7 M6, M7 I/O0, I/O1, I/O2, I/O3 M8, M9 I/O1, I/O2, I/O3, I/O4 ispMACH 4A Family Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio Macrocell Routable to I/O Cells M10, M11 I/O2, I/O3, I/O4, I/O5 M12, M13 I/O3, I/O4, I/O5, I/O6 M14, M15 I/O4, I/O5, I/O6, I/O7 I/O Cell Available Macrocells I/O0 M0, M1, M2, M3, M4, M5, M6, M7 I/O1 M2, M3, M4, M5, M6, M7, M8, M9 I/O2 M4, M5, M6, M7, M8, M9, M10, M11 I/O3 M6, M7, M8, M9, M10, M11, M12, M13 I/O4 M8, M9, M10, M11, M12, M13, M14, M15 I/O5 M0, M1, M10, M11, M12, M13, M14, M15 I/O6 M0, M1, M2, M3, M12, M13, M14, M15 I/O7 M0, M1, M2, M3, M4, M5, M14, M15 Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192 Macrocell Routable to I/O Cells M0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M4 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M5 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M6 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M8 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M9 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M10 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M11 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M12 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M13 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M14 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M15 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O0 M0 M1 M2 M3 M4 M5 M6 M7 I/O1 M0 M1 M2 M3 M4 M5 M6 M7 I/O2 M0 M1 M2 M3 M4 M5 M6 M7 I/O3 M0 M1 M2 M3 M4 M5 M6 M7 I/O4 M0 M1 M2 M3 M4 M5 M6 M7 I/O5 M0 M1 M2 M3 M4 M5 M6 M7 I/O6 M0 M1 M2 M3 M4 M5 M6 M7 I/O Cell Available Macrocells ispMACH 4A Family 15 Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192 Macrocell Routable to I/O Cells I/O7 M0 M1 M2 M3 M4 M5 M6 M7 I/O8 M8 M9 M10 M11 M12 M13 M14 M15 I/O9 M8 M9 M10 M11 M12 M13 M14 M15 I/O10 M8 M9 M10 M11 M12 M13 M14 M15 I/O11 M8 M9 M10 M11 M12 M13 M14 M15 I/O12 M8 M9 M10 M11 M12 M13 M14 M15 I/O13 M8 M9 M10 M11 M12 M13 M14 M15 I/O14 M8 M9 M10 M11 M12 M13 M14 M15 I/O15 M8 M9 M10 M11 M12 M13 M14 M15 Table 12. Output Switch Matrix Combinations for M4A(3,5)-32/32 Macrocell Routable to I/O Cells M0, M1, M2, M3, M4, M5, M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 M8, M9, M10, M11, M12, M13, M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 I/O Cell Available Macrocells I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 M0, M1, M2, M3, M4, M5, M6, M7 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 M8, M9, M10, M11, M12, M13, M14, M15 Table 13. Output Switch Matrix Combinations for M4A3-64/64 16 Macrocell Routable to I/O Cells MO, M1 I/O0, I/O1, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 M2, M3 I/O0, I/O1, I/O2, I/O3, I/O12, I/O13, I/O14, I/O15 M4, M5 I/O0, I/O1, I/O2,I/O3, I/O4,I/O5, I/O14, I/O15 M6, M7 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 M8, M9 I/O2, I/O3, I/O4, I/O5, I/O6, I/O7, I/O8, I/O9 M10, M11 I/O4, I/O5, I/O6, I/O7, I/O8, I/O9, I/O10, I/O11 M12, M13 I/O6, I/O7, I/O8, I/O9, I/O10, I/O11, I/O12, I/O13 M14, M15 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 I/O Cell Available Macrocells I/O0, I/O1 M0, M1, M2, M3, M4, M5, M6, M7 I/O2, I/O3 M2, M3, M4, M5, M6, M7, M8, M9 I/O4, I/O5 M4, M5, M6, M7, M8, M9, M10, M11 I/O6, I/O7 M6, M7, M8, M9, M10, M11, M12, M13 I/O8, I/O9 M8, M9, M10, M11, M12, M13, M14, M15 I/O10, I/O11 M0, M1, M10, M11, M12, M13, M14, M15 I/O12, I/O13 M0, M1, M2, M3, M12, M13, M14, M15 I/O14, I/O15 M0, M1, M2, M3, M4, M5, M14, M15 ispMACH 4A Family I/O Cell The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual output enable product term is provided for each I/O cell. The feedback signal drives the input switch matrix. Individual Output Enable Product Term From Output Switch Matrix To Input Switch Matrix Individual Output Enable Product Term From Output Switch Matrix Q D/L To Input Switch Matrix Block CLK0 Block CLK1 Block CLK2 Block CLK3 Power-up reset 17466G-017 Figure 10. I/O Cell for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio 17466G-018 Figure 11. I/O Cell for ispMACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and registered versions of the input are sent to the input switch matrix. This allows for such functions as “time-domain-multiplexed” data comparison, where the first data value is stored, and then the second data value is put on the I/O pin and compared with the previous stored value. Note that the flip-flop used in the ispMACH 4A I/O cell is independent of the flip-flops in the macrocells. It powers up to a logic low. Zero-Hold-Time Input Register The ispMACH 4A devices have a zero-hold-time (ZHT) fuse which controls the time delay associated with loading data into all I/O cell registers and latches. When programmed, the ZHT fuse increases the data path setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased, the setup time to the input storage element is minimized. This feature facilitates doing worst-case designs for which data is loaded from sources which have low (or zero) minimum output propagation delays from clock edges. ispMACH 4A Family 17 Input Switch Matrix The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch matrix. Without the input switch matrix, each input and feedback signal has only one way to enter the central switch matrix. The input switch matrix provides additional ways for these signals to enter the central switch matrix. 17466G-002 Figure 12. ispMACH 4A with 2:1 Macrocell-I/O Cell Ratio - Input Switch Matrix 18 From I/O Pin From Macrocell To Central Switch Matrix Registered/Latched Direct From Macrocell 2 From Macrocell 1 To Central Switch Matrix From Input Cell 17466G-003 Figure 13. ispMACH 4A with 1:1 Macrocell-I/O Cell Ratio - Input Switch Matrix ispMACH 4A Family PAL Block Clock Generation Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive a clock generator in each PAL block (Figure 14). The clock generator provides four clock signals that can be used anywhere in the PAL block. These four PAL block clock signals can consist of a large number of combinations of the true and complement edges of the global clock signals. Table 14 lists the possible combinations. GCLK0 Block CLK0 (GCLK0 or GCLK1) GCLK1 Block CLK1 (GCLK1 or GCLK0) GCLK2 Block CLK2 (GCLK2 or GCLK3) GCLK3 Block CLK3 (GCLK3 or GCLK2) 17466G-004 Figure 14. PAL Block Clock Generator 1 1. M4A(3,5)-32/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is tied to GCLK1. Table 14. PAL Block Clock Combinations1 Block CLK0 GCLK0 GCLK1 GCLK0 GCLK1 X X X X Block CLK1 GCLK1 GCLK1 GCLK0 GCLK0 X X X X Block CLK2 Block CLK3 X X X X GCLK2 (GCLK0) GCLK3 (GCLK1) GCLK2 (GCLK0) GCLK3 (GCLK1) X X X X GCLK3 (GCLK1) GCLK3 (GCLK1) GCLK2 (GCLK0) GCLK2 (GCLK0) Note: 1. Values in parentheses are for the M4A(3,5)-32/32 and M4A(3,5)-64/32. This feature provides high flexibility for partitioning state machines and dual-phase clocks. It also allows latches to be driven with either polarity of latch enable, and in a master-slave configuration. ispMACH 4A Family 19 ispMACH 4A TIMING MODEL The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a ispMACH 4A device, and at the same time, be easy to understand. This model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback. The parameter, tBUF, is defined as the time it takes to go from feedback through the output buffer to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is followed by an “i”. By adding tBUF to this internal parameter, the external parameter is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized ispMACH 4A timing model is shown in Figure 15. Refer to the application note entitled MACH 4 Timing and High Speed Design for a more detailed discussion about the timing parameters. (External Feedback) (Internal Feedback) COMB/DFF/TFF/ LATCH/SR*/JK* tPL tSS(T) tSA(T) tH(S/A) tS(S/A)L tH(S/A)L tSRR INPUT REG/ INPUT LATCH tSIRS tHIRS tSIL tHIL tSIRZ tHIRZ tSILZ tHILZ tPDILi tICOSi tIGOSi tPDILZi tSLW *emulated Central Switch Matrix IN tPDi Q tPDLi tCO(S/A)i tGO(S/A)i tSRi S/R Q OUT tBUF tEA tER BLK CLK 17466G-025 Figure 15. ispMACH 4A Timing Model SPEEDLOCKING FOR GUARANTEED FIXED TIMING The ispMACH 4A architecture allows allocation of up to 20 product terms to an individual macrocell with the assistance of an XOR gate without incurring additional timing delays. The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required by the design. Other competitive CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine to give designs easy access to the performance required in today’s designs. 20 ispMACH 4A Family IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY All ispMACH 4A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a boardlevel serial scan path for more complete board-level testing. IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All ispMACH 4A devices provide In-System Programming (ISP) capability through their Boundary ScanTest Access Ports. This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface. ispMACH 4A devices can be programmed across the commercial temperature and voltage range. The PC-based LatticePRO software facilitates in-system programming of ispMACH 4A devices. LatticePRO takes the JEDEC file output produced by the design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. LatticePRO software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats understood by common automated test equipment. This equpment can then be used to program ispMACH 4A devices during the testing of a circuit board. PCI COMPLIANT ispMACH 4A devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the PCI Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature. SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS Both the 3.3-V and 5-V VCC ispMACH 4A devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5 V. Both the 5-V and 3.3-V versions have the same high-speed performance and provide easy-touse mixed-voltage design capability. PULL UP OR BUS-FRIENDLY INPUTS AND I/Os All ispMACH 4A devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site. ispMACH 4A Family 21 All ispMACH 4A devices have a programmable bit that configures all inputs and I/Os with either pull-up or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs and I/O pins are weakly pulled up. For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site. POWER MANAGEMENT Each individual PAL block in ispMACH 4A devices features a programmable low-power mode, which results in power savings of up to 50%. The signal speed paths in the low-power PAL block will be slower than those in the non-low-power PAL block. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in the low-power mode. PROGRAMMABLE SLEW RATE Each ispMACH 4A device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slowslew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power. POWER-UP RESET/SET All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed. SECURITY BIT A programmable security bit is provided on the ispMACH 4A devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device. HOT SOCKETING ispMACH 4A devices are well-suited for those applications that require hot socketing capability. Hot socketing a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the powered-down MACH devices be minimal on active signals. 22 ispMACH 4A Family CLK0 CLK1 CLK2 CLK3 CLOCK GENERATOR A 4 M4A(3, 5)-64/32 M4A3-64/64 M4A(3, 5)-96/48 M4A(3, 5)-128/64 A B M4(3, 5)-192/96 M4(3, 5)-256/128 16 17 17 17 M4A3-384 M4A3-512 18 18 0 M0 C0 MACROCELL M0 M1 C1 M1 MACROCELL M2 MACROCELL M3 C3 OUTPUT SWITCH MATRIX LOGIC ALLOCATOR CENTRAL SWITCH MATRIX M7 M7 MACROCELL M8 MACROCELL M8 M9 MACROCELL M10 MACROCELL M11 MACROCELL M12 MACROCELL C15 89 O4 I/O CELL O5 I/O CELL O6 I/O CELL O7 I/O CELL I/O3 I/O4 I/O5 M12 M13 C14 I/O CELL I/O2 M10 M11 C13 O3 I/O1 M6 MACROCELL M6 M9 C12 I/O CELL MACROCELL M5 C6 C11 O2 I/O0 M4 M5 C10 I/O CELL MACROCELL M4 C5 C9 O1 MACROCELL M3 C4 C8 I/O CELL M2 C2 C7 O0 M13 MACROCELL M14 MACROCELL I/O6 M14 M15 I/O7 MACROCELL M15 B 16 24 INPUT SWITCH MATRIX 16 Figure 16. PAL Block for ispMACH 4A with 2:1 Macrocell - I/O Cell Ratio ispMACH 4A Family 23 CLK0 CLK1 CLK2 CLK3 CLOCK GENERATOR A M4A3-64/64 M4A3-256/160 M4A3-256/192 16 17 18 18 A B 4 0 M0 M0 MACROCELL M1 MACROCELL M2 MACROCELL M3 MACROCELL M4 MACROCELL C5 M5 MACROCELL C6 M6 MACROCELL M7 MACROCELL M8 MACROCELL M9 MACROCELL M10 MACROCELL C11 M11 MACROCELL C12 M12 MACROCELL C13 M13 MACROCELL C14 M14 MACROCELL C15 M15 MACROCELL C0 O0 I/O CELL O1 I/O CELL O2 I/O CELL O3 I/O CELL O4 I/O CELL O5 I/O CELL O6 I/O CELL O7 I/O CELL O8 I/O CELL O9 I/O CELL O10 I/O CELL O11 I/O CELL O12 I/O CELL O13 I/O CELL O14 I/O CELL O15 I/O CELL M1 C1 M2 C2 M3 C3 M4 C4 C8 M7 M8 M9 C9 C10 OUTPUT SWITCH MATRIX C7 M6 LOGIC ALLOCATOR CENTRAL SWITCH MATRIX M5 M10 M11 M12 M13 M14 M15 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 97 B 16 32 INPUT SWITCH MATRIX 16 17466H-41 Figure 17. PAL Block for ispMACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32) 24 ispMACH 4A Family CLK0/I0 CLK0/I1 CLOCK GENERATOR 16 2 0 M0 M0 MACROCELL M1 MACROCELL M2 MACROCELL M3 MACROCELL M4 MACROCELL C5 M5 MACROCELL C6 M6 MACROCELL M7 MACROCELL M8 MACROCELL M9 MACROCELL M10 MACROCELL C11 M11 MACROCELL C12 M12 MACROCELL C13 M13 MACROCELL C14 M14 MACROCELL C15 M15 MACROCELL C0 O0 I/O CELL O1 I/O CELL O2 I/O CELL O3 I/O CELL O4 I/O CELL O5 I/O CELL O6 I/O CELL O7 I/O CELL O8 I/O CELL O9 I/O CELL O10 I/O CELL O11 I/O CELL O12 I/O CELL O13 I/O CELL M1 C1 M3 C3 M4 C4 C7 C8 M6 LOGIC ALLOCATOR CENTRAL SWITCH MATRIX M5 OUTPUT SWITCH MATRIX M2 C2 M7 M8 M9 C10 M10 M11 M12 M13 OUTPUT SWITCH MATRIX C9 M14 O14 I/O CELL O15 I/O CELL M15 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 97 17 16 32 INPUT SWITCH MATRIX 16 Figure 18. PAL Block for M4A (3,5)-32/32 ispMACH 4A Family 17466H-042 25 BLOCK DIAGRAM – M4A(3,5)-32/32 Block A I/O8–I/O15 I/O0–I/O7 8 8 I/O Cells Clock Generator I/O Cells 8 8 8 Output Switch Matrix 8 4 8 8 Output Switch Matrix 8 4 8 8 Macrocells OE 2 8 Input Switch Matrix OE Macrocells Input Switch Matrix 8 66 X 98 AND Logic Array and Logic Allocator 16 16 33 Central Switch Matrix 2 2 33 16 Input Switch Matrix 16 OE 8 2 Input Switch Matrix 66 X 98 AND Logic Array and Logic Allocator OE CLK0/I0, CLK1/I1 8 8 Macrocells Macrocells 8 4 8 8 Output Switch Matrix 8 8 Clock Generator 8 I/O Cells 4 8 8 8 Output Switch Matrix 8 I/O Cells 8 8 I/O16–I/O23 I/O24–I/O31 Block B 17466H-019 26 ispMACH 4A Family BLOCK DIAGRAM – M4A(3,5)-64/32 Block A Block D I/O0–I/O7 I/O24–I/O31 8 8 I/O Cells 8 8 Output Switch Matrix 16 4 16 16 8 4 Output Switch Matrix 8 16 4 16 Macrocells OE Input Switch Matrix OE 16 66 X 90 AND Logic Array and Logic Allocator 2 24 33 33 24 Central Switch Matrix 2 2 Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 2 33 24 66 X 90 AND Logic Array and Logic Allocator 2 OE OE 16 Macrocells 4 Output Switch Matrix 8 16 Clock Generator 16 8 16 Macrocells 16 4 24 Input Switch Matrix 33 Clock Generator CLK0/I0, CLK1/I1 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator 2 16 Input Switch Matrix 4 Clock Generator Clock Generator I/O Cells 16 4 16 8 4 I/O Cells 8 Output Switch Matrix 16 8 I/O Cells 8 I/O8–I/O15 I/O16–I/O23 Block B Block C 17466H-020 ispMACH 4A Family 27 BLOCK DIAGRAM – M4A3-64/64 Block D 16 16 I/O Cells I/O Cells 16 16 Output Switch Matrix 16 4 16 Clock Generator Clock Generator Block A 16 16 Output Switch Matrix 16 4 16 Macrocells OE OE CLK0/I0, CLK1/I1 CLK2/I3, CLK3/I4 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator 4 16 16 16 66 X 90 AND Logic Array and Logic Allocator 4 33 33 Central Switch Matrix 4 2 4 33 33 66 X 90 AND Logic Array and Logic Allocator 4 66 X 90 AND Logic Array and Logic Allocator 4 OE OE 16 16 Macrocells 16 16 Output Switch Matrix 16 16 Clock Generator Clock Generator Macrocells 4 16 4 16 16 16 Output Switch Matrix 16 16 I/O Cells I/O Cells 16 16 Block C Block B 17466H-020A 28 ispMACH 4A Family 4 Clock Generator CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5 ispMACH 4A Family 4 OE OE 4 Block D I/O24–I/O31 8 I/O Cells 8 Output Switch Matrix 16 4 8 Block E I/O32–I/O39 8 I/O Cells 8 Output Switch Matrix 16 Macrocells 24 16 16 Input Switch Matrix 8 OE 4 16 66 X 90 AND Logic Array and Logic Allocator 33 4 4 4 8 OE 16 Input Switch Matrix 16 OE Macrocells 4 24 4 4 8 Block F I/O40–I/O47 8 I/O Cells 8 Output Switch Matrix 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator 33 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 8 I/O Cells 8 16 16 24 24 16 16 Input Switch Matrix 4 24 16 16 Central Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 4 OE 16 66 X 90 AND Logic Array and Logic Allocator Input Switch Matrix 24 4 4 8 8 Input Switch Matrix 33 16 16 4 I/O Cells 8 I/O0–I/O7 Block A Input Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix Clock Generator 4 8 8 I/O Cells 8 Block B I/O8–I/O15 Clock Generator 4 4 4 Block C I/O16–I/O23 4 BLOCK DIAGRAM – M4A(3,5)-96/48 I2, I3, I6, I7 Clock Generator Clock Generator Clock Generator 17466G-021 29 4 OE ispMACH 4A Family OE 4 Block F 8 I/O Cells 8 Output Switch Matrix I/O40–I/O47 4 8 Block E Clock Generator I/O32–I/O39 8 I/O Cells 8 16 16 4 4 8 Block G I/O48–I/O55 8 I/O Cells 8 Output Switch Matrix 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator 33 24 24 16 16 4 4 4 4 4 8 8 OE Output Switch Matrix 16 Input Switch Matrix 16 Macrocells 4 OE 8 OE 4 16 66 X 90 AND Logic Array and Logic Allocator 24 16 Input Switch Matrix 16 Input Switch Matrix 16 OE Macrocells 4 33 Central Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 16 4 Block A Block H I/O56–I/O63 8 I/O Cells 8 Output Switch Matrix 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator 33 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 8 I/O Cells 8 I/O0–I/O7 16 16 24 24 16 16 Input Switch Matrix 4 24 8 Output Switch Matrix OE 16 66 X 90 AND Logic Array and Logic Allocator Input Switch Matrix 24 4 4 8 OE 33 16 Input Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 16 4 I/O Cells 8 Input Switch Matrix 24 4 4 8 8 Output Switch Matrix Block B I/O8–I/O15 Input Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator 16 16 Clock Generator 4 Clock Generator Macrocells 16 16 4 I/O Cells 8 Clock Generator 4 8 Output Switch Matrix 8 I/O Cells 8 Block C I/O16–I/O23 Clock Generator 4 4 4 Block D I/O24–I/031 2 BLOCK DIAGRAM – M4A(3,5)-128/64 I2, I5 Clock Generator Clock Generator Clock Generator CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4 17466H-022 30 BLOCK DIAGRAM – M4A(3,5)-192/96 68 X 90 AND Logic Array and Logic Allocator 24 4 4 16 4 16 8 4 34 16 Macrocells 16 16 68 X 90 AND Logic Array and Logic Allocator 4 24 34 Output Switch Matrix 16 16 16 68 X 90 AND Logic Array and Logic Allocator 4 4 8 4 OE Macrocells 68 X 90 AND Logic Array and Logic Allocator 24 34 8 Output Switch Matrix Macrocells 16 Input Switch Matrix 16 Input Switch Matrix 16 Macrocells 8 16 OE 16 16 Clock Generator 4 8 I/O Cells 8 4 OE 8 16 4 Clock Generator 16 8 Output Switch Matrix OE 4 Clock Generator 8 Output Switch Matrix 8 I/O Cells I/O Cells Clock Generator I/O Cells 4 4 8 Block K I/O80–I/O87 Input Switch Matrix 8 Block L I/O88–I/O95 CLK0–CLK3 Input Switch Matrix Block A I/O0–I/O7 Block B I/O8–I/O15 24 34 I/O72–I/O79 Block J I/O64–I/O71 Block I Block C I/O16–I/O23 Block D I/O24–I/O31 8 8 8 8 Output Switch Matrix 8 4 8 4 Output Switch Matrix 8 I/O Cells I/O Cells 8 8 I/O32–I/O39 Block E I/O40–I/O47 Block F 4 8 4 8 8 16 I/O48–I/O55 Block G 4 16 Macrocells 16 16 4 8 4 Input Switch Matrix Input Switch Matrix 24 Input Switch Matrix Clock Generator OE OE 4 I/O Cells I0–I15 34 68 X 90 AND Logic Array and Logic Allocator OE Input Switch Matrix Clock Generator OE Output Switch Matrix 16 24 34 16 16 4 8 4 16 16 68 X 90 AND Logic Array and Logic Allocator 16 Macrocells Macrocells 16 16 4 16 Macrocells 24 68 X 90 AND Logic Array and Logic Allocator Output Switch Matrix 16 24 34 4 8 4 16 Clock Generator 16 16 16 68 X 90 AND Logic Array and Logic Allocator 34 8 4 16 34 68 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 16 34 24 4 8 Output Switch Matrix 4 4 4 I/O Cells 8 4 Macrocells Clock Generator 34 68 X 90 AND Logic Array and Logic Allocator 16 68 X 90 AND Logic Array and Logic Allocator 24 34 24 16 4 Input Switch Matrix 24 16 Input Switch Matrix 68 X 90 AND Logic Array and Logic Allocator Macrocells OE Input Switch Matrix 16 Central Switch Matrix OE Macrocells 4 16 16 Clock Generator 16 8 16 Clock Generator 4 Clock Generator 8 16 4 OE 16 8 Output Switch Matrix OE 4 Clock Generator 8 Output Switch Matrix I/O Cells I/O Cells Input Switch Matrix I/O Cells Output Switch Matrix 16 8 I/O Cells 8 I/O56–I/O63 Block H 17466G-067 ispMACH 4A Family 31 BLOCK DIAGRAM – M4A(3,5)-256/128 4 8 8 8 Output Switch Matrix 8 4 8 4 Clock Generator Clock Generator OE OE 68 X 90 AND Logic Array and Logic Allocator 4 4 8 I/O Cells 8 8 I/O56–I/O63 Block H 8 4 8 4 8 I/O Cells 8 14 I0–I13 Input Switch Matrix Input Switch Matrix Input Switch Matrix Input Switch Matrix Clock Generator OE Output Switch Matrix I/O64–I/O71 Block I ispMACH 4A Family 16 24 34 34 24 68 X 90 AND Logic Array and Logic Allocator 4 16 Macrocells 16 16 4 8 4 16 16 68 X 90 AND Logic Array and Logic Allocator 4 16 16 16 Macrocells 16 4 Output Switch Matrix 16 16 24 Macrocells 4 8 4 24 68 X 90 AND Logic Array and Logic Allocator Macrocells Output Switch Matrix OE 68 X 90 AND Logic Array and Logic Allocator 34 8 4 16 34 16 16 16 16 34 I/O Cells I/O48–I/O55 Block G 32 Input Switch Matrix 16 8 Output Switch Matrix 4 4 4 I/O Cells 8 4 34 16 Macrocells 16 16 Input Switch Matrix 4 Clock Generator Input Switch Matrix 24 I/O104–I/O111 Block N I/O96–I/O103 Block M I/O88–I/O95 Block L I/O80–I/O87 Block K 8 OE 34 8 I/O Cells 8 Macrocells 68 X 90 AND Logic Array and Logic Allocator 16 8 Macrocells 24 34 16 16 4 16 4 68 X 90 AND Logic Array and Logic Allocator 8 16 OE Input Switch Matrix 68 X 90 AND Logic Array and Logic Allocator 4 16 OE Macrocells 24 8 Output Switch Matrix 16 4 Output Switch Matrix 8 OE 4 8 I/O Cells Clock Generator 8 Clock Generator 4 16 24 8 I/O Cells 8 16 OE I/O Cells 16 Clock Generator OE 8 16 4 I/O Cells 8 16 Output Switch Matrix 16 16 4 I/O Cells Block C I/O16–I/O23 Block D I/O24–I/O31 Block E I/O32–I/O39 Block F I/O40–I/O47 Output Switch Matrix 8 16 Macrocells OE I/O Cells 4 16 16 4 24 68 X 90 AND Logic Array and Logic Allocator Input Switch Matrix 8 Output Switch Matrix 34 Clock Generator 4 8 4 24 34 16 Macrocells Macrocells 16 16 4 16 16 68 X 90 AND Logic Array and Logic Allocator 4 Clock Generator 8 4 16 Macrocells 24 68 X 90 AND Logic Array and Logic Allocator Output Switch Matrix 16 16 Clock Generator 4 34 Clock Generator Output Switch Matrix Input Switch Matrix 16 16 16 34 68 X 90 AND Logic Array and Logic Allocator 8 4 24 34 16 Macrocells 4 Central Switch Matrix Input Switch Matrix 16 4 68 X 90 AND Logic Array and Logic Allocator 4 8 4 16 34 24 68 X 90 AND Logic Array and Logic Allocator 16 OE 34 24 16 4 Macrocells 68 X 90 AND Logic Array and Logic Allocator 24 34 Input Switch Matrix 24 4 8 Output Switch Matrix Macrocells Clock Generator OE 68 X 90 AND Logic Array and Logic Allocator 4 16 Clock Generator Input Switch Matrix 16 16 16 Macrocells 8 16 OE 16 16 Clock Generator 4 8 I/O Cells 8 4 OE 8 16 4 OE 16 8 Output Switch Matrix Clock Generator 4 Clock Generator 8 Output Switch Matrix 8 I/O Cells I/O Cells Input Switch Matrix I/O Cells 4 4 8 Block O I/O112–I/O119 Input Switch Matrix 8 Block P I/O120–I/O127 CLK0–CLK3 Input Switch Matrix Block A I/O0–I/O7 Block B I/O8–I/O15 Output Switch Matrix 16 8 I/O Cells 8 I/O72–I/O79 Block J 17466G-024 BLOCK DIAGRAM – M4A3-256/160, M4A3-256/192 16 16 Output Switch Matrix 16 I/O Cells 16 Block G 16 4 16 4 Clock Generator Clock Generator 16 4 16 4 Input Switch Matrix Input Switch Matrix Clock Generator OE OE Output Switch Matrix 16 I/O Cells I/O Cells 16 16 Block H 36 Block I 32 72 X 98 AND Logic Array and Logic Allocator 16 16 Macrocells 16 16 32 36 4 4 16 4 16 16 72 X 98 AND Logic Array and Logic Allocator 4 32 16 16 Macrocells OE OE 4 Output Switch Matrix 16 16 32 Macrocells 4 16 4 16 72 X 98 AND Logic Array and Logic Allocator 4 16 4 OE OE OE 16 16 72 X 98 AND Logic Array and Logic Allocator Macrocells Output Switch Matrix Output Switch Matrix 36 4 N M L K I/O Cells 16 36 16 16 16 4 4 Clock Generator 16 Block Block Block Block 16 4 36 72 X 98 AND Logic Array and Logic Allocator 16 Macrocells 16 I/O Cells 16 36 Clock Generator 16 4 4 16 16 Macrocells 72 X 98 AND Logic Array and Logic Allocator 32 Input Switch Matrix Input Switch Matrix 16 4 Output Switch Matrix 16 OE 36 72 X 98 AND Logic Array and Logic Allocator 4 16 16 16 Macrocells 32 36 32 16 4 Input Switch Matrix 72 X 98 AND Logic Array and Logic Allocator 16 16 16 Clock Generator Input Switch Matrix 16 4 16 OE Macrocells 32 16 16 16 I/O Cells Output Switch Matrix OE 16 16 4 16 Clock Generator 16 16 I/O Cells 4 Input Switch Matrix OE OE Input Switch Matrix 16 I/O Cells 16 I/O Cells I/O Cells 16 16 4 Output Switch Matrix 4 Input Switch Matrix 4 16 16 Macrocells 16 Input Switch Matrix 16 Output Switch Matrix 32 72 X 98 AND Logic Array and Logic Allocator 16 16 4 36 Clock Generator 4 32 36 4 16 16 72 X 98 AND Logic Array and Logic Allocator 4 32 Macrocells Block C Block D Block E Block F Output Switch Matrix 4 OE 4 16 16 32 72 X 98 AND Logic Array and Logic Allocator Macrocells 16 I/O Cells Clock Generator 36 16 16 Clock Generator 36 Output Switch Matrix Macrocells Clock Generator 4 36 72 X 98 AND Logic Array and Logic Allocator 16 4 16 Clock Generator 16 36 16 4 16 72 X 98 AND Logic Array and Logic Allocator 4 4 Clock Generator 4 16 16 Central Switch Matrix 16 72 X 98 AND Logic Array and Logic Allocator Clock Generator Output Switch Matrix 16 16 4 Output Switch Matrix Macrocells 16 Macrocells 16 16 4 Input Switch Matrix Input Switch Matrix 16 16 4 Macrocells 32 16 I/O Cells 16 4 OE OE 36 72 X 98 AND Logic Array and Logic Allocator 16 16 32 36 32 16 4 16 4 Clock Generator Input Switch Matrix 72 X 98 AND Logic Array and Logic Allocator 32 16 16 Macrocells 16 16 I/O Cells Output Switch Matrix OE 16 16 4 16 Clock Generator 16 4 I/O Cells 4 Block O Input Switch Matrix I/O Cells 16 4 16 Block P Input Switch Matrix 16 Output Switch Matrix CLK0–CLK3 Block A Input Switch Matrix Block B 16 16 Output Switch Matrix 16 16 I/O Cells 16 Block J 17466G-050 ispMACH 4A Family 33 BLOCK DIAGRAM – M4A3-384/160, M4A3-384/192 CLK0–CLK3 Block B Block A Block HX Block GX 4 4 Output Switch Matrix 8 4 8 I/O Cells 8 Block G Block J Block H Block I 4 16 Macrocells 16 16 8 Input Switch Matrix 24 Input Switch Matrix Clock Generator 36 OE Output Switch Matrix 16 16 4 8 4 Output Switch Matrix 16 8 I/O Cells I/O Cells 8 Block D Block E OE OE OE 8 24 72 X 90 AND Logic Array and Logic Allocator 4 16 16 72 X 90 AND Logic Array and Logic Allocator 36 16 4 I/O Cells Block C Block F Input Switch Matrix Clock Generator Clock Generator OE Input Switch Matrix Input Switch Matrix 16 16 16 16 4 16 Macrocells Output Switch Matrix Macrocells Clock Generator 4 8 Macrocells 4 16 24 72 X 90 AND Logic Array and Logic Allocator 4 Clock Generator 8 4 Central Switch Matrix 4 36 16 16 16 Output Switch Matrix 36 8 24 36 72 X 90 AND Logic Array and Logic Allocator 8 4 16 72 X 90 AND Logic Array and Logic Allocator 4 4 16 16 36 OE Input Switch Matrix Input Switch Matrix 16 4 Output Switch Matrix Macrocells 72 X 90 AND Logic Array and Logic Allocator 24 Macrocells 8 OE OE 36 8 I/O Cells 8 4 Macrocells 24 4 8 4 16 4 72 X 90 AND Logic Array and Logic Allocator 4 Output Switch Matrix 16 36 24 16 16 16 72 X 90 AND Logic Array and Logic Allocator 24 16 8 Macrocells 16 8 I/O Cells Clock Generator 4 16 16 Clock Generator 4 8 Clock Generator 16 4 I/O Cells 8 Output Switch Matrix 4 8 I/O Cells Input Switch Matrix 8 Detail A 8 8 Block FX Block CX Block EX Block DX Repeat Detail A Block AX Block P 8 Block K 8 4 4 Output Switch Matrix 8 I/O Cells 8 4 8 4 8 Block L 36 8 Block M 24 72 X 90 AND Logic Array and Logic Allocator 4 16 Macrocells 16 16 4 8 4 Input Switch Matrix OE 8 I/O Cells 24 36 OE Output Switch Matrix 16 16 16 16 72 X 90 AND Logic Array and Logic Allocator 4 16 16 4 Macrocells 16 Macrocells Macrocells Clock Generator Clock Generator OE 4 Output Switch Matrix 16 24 72 X 90 AND Logic Array and Logic Allocator OE 4 4 24 36 16 16 Clock Generator OE 36 72 X 90 AND Logic Array and Logic Allocator 8 16 Clock Generator 8 I/O Cells 4 72 X 90 AND Logic Array and Logic Allocator 4 Clock Generator Output Switch Matrix Input Switch Matrix 16 4 16 8 4 16 36 16 Macrocells 16 16 Input Switch Matrix Input Switch Matrix 16 16 Output Switch Matrix 16 36 24 4 4 OE 36 8 Macrocells 72 X 90 AND Logic Array and Logic Allocator I/O Cells 8 4 Macrocells 24 36 72 X 90 AND Logic Array and Logic Allocator 4 16 4 8 16 OE 72 X 90 AND Logic Array and Logic Allocator 4 Output Switch Matrix OE Input Switch Matrix 16 24 16 16 Macrocells 24 8 Clock Generator 4 16 16 Clock Generator 8 Clock Generator 16 4 Output Switch Matrix I/O Cells I/O Cells 8 Block BX Block O 8 Input Switch Matrix I/O Cells 8 Input Switch Matrix 8 Input Switch Matrix 8 Output Switch Matrix 16 8 I/O Cells 8 Block N 17466G-067 34 ispMACH 4A Family BLOCK DIAGRAM - M4A3-512/160, M4A3-512/192, M4A3-512/256 CLK0–CLK3 Block B Block A Block PX Block OX 4 4 8 16 16 4 Output Switch Matrix 8 4 8 I/O Cells 8 Block G Block J Block H Block I Block K Block N Block L Block M OE 16 Macrocells 16 16 8 Input Switch Matrix 24 Input Switch Matrix Clock Generator 36 16 16 4 8 4 Output Switch Matrix 16 8 I/O Cells I/O Cells 8 Block D Block E OE OE Output Switch Matrix 4 I/O Cells Block C Block F Input Switch Matrix Clock Generator Clock Generator OE 8 24 72 X 90 AND Logic Array and Logic Allocator 4 16 16 72 X 90 AND Logic Array and Logic Allocator 36 16 4 16 16 4 16 Macrocells Output Switch Matrix Macrocells Clock Generator 8 Macrocells 4 16 24 72 X 90 AND Logic Array and Logic Allocator 4 Clock Generator 4 4 OE Input Switch Matrix Input Switch Matrix 72 X 90 AND Logic Array and Logic Allocator 8 24 36 Central Switch Matrix 16 Output Switch Matrix 36 8 4 16 72 X 90 AND Logic Array and Logic Allocator 4 4 16 16 36 16 16 4 36 OE Input Switch Matrix Input Switch Matrix 16 Output Switch Matrix Macrocells 72 X 90 AND Logic Array and Logic Allocator 24 Macrocells 8 OE OE 36 8 I/O Cells 8 4 Macrocells 24 4 8 4 16 4 72 X 90 AND Logic Array and Logic Allocator 4 Output Switch Matrix 16 36 24 16 16 16 72 X 90 AND Logic Array and Logic Allocator 24 16 8 Macrocells 16 8 I/O Cells Clock Generator 4 16 16 Clock Generator 4 8 Clock Generator 16 4 I/O Cells 8 Output Switch Matrix 4 8 I/O Cells Input Switch Matrix 8 Detail A 8 8 Block MX Block LX Block NX Block KX Block IX Block HX Block JX Block GX Repeat Detail A Repeat Detail A Block EX Block DX Output Switch Matrix 8 I/O Cells 8 Block O 4 Output Switch Matrix 8 I/O Cells 4 36 8 Block AX ispMACH 4A Family 16 Macrocells 16 16 4 8 4 Input Switch Matrix 24 72 X 90 AND Logic Array and Logic Allocator OE 8 I/O Cells 8 Block P OE OE Output Switch Matrix 4 16 24 36 4 16 16 72 X 90 AND Logic Array and Logic Allocator 16 16 4 8 Clock Generator Clock Generator Clock Generator OE 4 8 16 16 4 16 Macrocells Macrocells 16 16 4 Output Switch Matrix Macrocells 24 72 X 90 AND Logic Array and Logic Allocator OE Input Switch Matrix 16 4 8 36 4 4 16 Clock Generator Macrocells 16 16 36 16 8 24 36 72 X 90 AND Logic Array and Logic Allocator 8 4 16 72 X 90 AND Logic Array and Logic Allocator 4 Clock Generator 16 4 4 16 16 36 24 Input Switch Matrix Input Switch Matrix 16 Output Switch Matrix 4 OE 36 8 Macrocells 72 X 90 AND Logic Array and Logic Allocator I/O Cells 8 4 Macrocells 24 36 72 X 90 AND Logic Array and Logic Allocator 4 16 4 8 16 OE 72 X 90 AND Logic Array and Logic Allocator 4 Output Switch Matrix OE Input Switch Matrix 16 24 16 16 Macrocells 24 8 Clock Generator 4 16 16 Clock Generator 8 Clock Generator 16 4 Output Switch Matrix I/O Cells I/O Cells 8 8 Input Switch Matrix I/O Cells Block FX Block CX 8 Input Switch Matrix 8 Input Switch Matrix 8 Output Switch Matrix 16 8 I/O Cells 8 Block BX 17466G-068 35 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES M4A5 Commercial (C) Devices Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . . . 0°C to +70°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . .-55°C to +100°C Device Junction Temperature . . . . . . . . . . . . . . . +130°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage. . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . 2000 V Latchup Current (TA = -40°C to +85°C) . . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +4.75 V to +5.25 V Industrial (I) Devices Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . . -40°C to +85°C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.50 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. 5-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description VOH Output HIGH Voltage VOL Test Conditions IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL Min Typ Max Unit 2.4 V IOH = –2.5 mA, VCC = Max, VIN = VIH or VIL 3.6 V Output LOW Voltage IOL = 24 mA, VCC = Min, VIN = VIH or VIL (Note 1) 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 3) –10 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 3) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max , VIN = VIH or VIL (Note 3) –10 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 4) –160 mA 2.0 –30 V Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 36 ispMACH 4A Family ABSOLUTE MAXIMUM RATINGS OPERATING RANGES M4A3 Commercial (C) Devices Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . . . 0°C to +70°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . .-55°C to +100°C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V Device Junction Temperature . . . . . . . . . . . . . . . +130°C Industrial (I) Devices Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +4.5 V Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . . -40°C to +85°C DC Input Voltage. . . . . . . . . . . . . . . . . . . . -0.5 V to 6.0 V Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . 2000 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V Latchup Current (TA = -40°C to +85°C) . . . . . . . 200 mA Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. 3.3-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min VIN = VIH or VIL VOL Output LOW Voltage VCC = Min VIN = VIH or VIL (Note 1) Min Typ Max Unit IOH = –100 µA VCC – 0.2 V IOH = –3.2 mA 2.4 V IOL = 100 µA 0.2 V IOL = 24 mA 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs 2.0 5.5 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs –0.3 0.8 V IIH Input HIGH Leakage Current VIN = 3.6 V, VCC = Max (Note 2) 5 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –5 µA IOZH Off-State Output Leakage Current HIGH VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) 5 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –5 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –160 mA –15 Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Notes: 1. See “MACH Switching Test Circuit” document on the Literature Download page of the Lattice web site. 2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. ispMACH 4A Family 37 ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 -5 -55 -6 -65 -7 -10 -12 -14 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit Combinatorial Delay: tPDi Internal combinatorial propagation delay 3.5 4.0 4.3 4.5 5.0 7.0 9.0 11.0 ns tPD Combinatorial propagation delay 5.0 5.5 6.0 6.5 7.5 10.0 12.0 14.0 ns Registered Delays: tSS Synchronous clock setup time, D-type register 3.0 3.5 3.5 3.5 5.0 5.5 7.0 10.0 ns tSST Synchronous clock setup time, T-type register 4.0 4.0 4.0 4.0 6.0 6.5 8.0 11.0 ns tSA Asynchronous clock setup time, D-type register 2.5 2.5 2.5 3.0 3.5 4.0 5.0 8.0 ns tSAT Asynchronous clock setup time, T-type register 3.0 3.0 3.0 3.5 4.5 5.0 6.0 9.0 ns tHS Synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns tHA Asynchronous clock hold time 2.5 2.5 2.5 3.0 3.5 4.0 5.0 8.0 ns tCOSi Synchronous clock to internal output 2.5 2.5 2.8 3.0 3.0 3.0 3.5 3.5 ns tCOS Synchronous clock to output 4.0 4.0 4.5 5.0 5.5 6.0 6.5 6.5 ns tCOAi Asynchronous clock to internal output 5.0 5.0 5.0 5.0 6.0 8.0 10.0 12.0 ns tCOA Asynchronous clock to output 6.5 6.5 6.8 7.0 8.5 11.0 13.0 15.0 ns Latched Delays: tSSL Synchronous latch setup time tSAL Asynchronous latch setup time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns tHSL Synchronous latch hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns tHAL Asynchronous latch hold time 3.0 3.0 3.5 3.5 4.0 4.0 5.0 8.0 ns tPDLi Transparent latch to internal output 5.5 5.5 5.8 6.0 7.5 9.0 11.0 12.0 ns tPDL Propagation delay through transparent latch to output 7.0 7.0 7.5 8.0 10.0 12.0 14.0 15.0 ns tGOSi Synchronous gate to internal output 3.0 3.0 3.0 3.0 3.5 4.5 7.0 8.0 ns Synchronous gate to output 4.5 4.5 4.8 5.0 6.0 7.5 10.0 11.0 ns tGOS 4.0 4.0 4.0 4.5 6.0 7.0 8.0 10.0 ns tGOAi Asynchronous gate to internal output 6.0 6.0 6.0 6.0 8.5 10.0 13.0 15.0 ns Asynchronous gate to output 7.5 7.5 7.8 8.0 11.0 13.0 16.0 18.0 ns tGOA Input Register Delays: Input register setup time 1.5 tHIRS Input register hold time 2.5 tSIRS tICOSi Input register clock to internal feedback 1.5 2.0 2.5 3.0 2.0 3.0 3.0 2.0 3.0 3.0 2.0 3.0 3.0 2.0 3.0 3.5 2.0 3.0 4.5 ns 4.0 6.0 ns 6.0 ns Input Latch Delays: tSIL Input latch setup time 1.5 tHIL Input latch hold time 2.5 tIGOSi Input latch gate to internal feedback tPDILi 38 Transparent input latch to internal feedback 1.5 1.5 2.5 2.0 2.5 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 ns 4.0 ns 3.5 3.5 3.8 4.0 4.0 4.0 4.0 5.0 ns 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns ispMACH 4A Family ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) -5 -55 -6 -65 -7 -10 -12 -14 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit Input Register Delays with ZHT Option: Input register setup time - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns tHIRZ Input register hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns Input latch setup time - ZHT 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns tHILZ Input latch hold time - ZHT 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns tSIRZ Input Latch Delays with ZHT Option: tSILZ tPDIL Transparent input latch to internal feedback - ZHT Zi 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 ns Output Delays: tBUF Output buffer delay 1.5 1.5 1.8 2.0 2.5 3.0 3.0 3.0 ns tSLW Slow slew rate delay adder 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns tEA Output enable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns tER Output disable time 7.5 7.5 8.5 8.5 9.5 10.0 12.0 15.0 ns 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns Power Delay: tPL Power-down mode delay adder Reset and Preset Delays: tSRi Asynchronous reset or preset to internal register output 7.5 7.7 8.0 8.0 9.5 11.0 13.0 16.0 ns tSR Asynchronous reset or preset to register output 9.0 9.2 10.0 10.0 12.0 14.0 16.0 19.0 ns tSRR Asynchronous reset and preset register recovery time 7.0 7.0 7.5 7.5 8.0 8.0 10.0 15.0 ns tSRW Asynchronous reset or preset width 7.0 7.0 8.0 8.0 10.0 10.0 12.0 15.0 ns Clock/LE Width: tWLS Global clock width low 2.0 2.0 2.5 2.5 3.0 4.0 5.0 6.0 ns tWHS Global clock width high 2.0 2.0 2.5 2.5 3.0 4.0 5.0 6.0 ns tWLA Product term clock width low 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns tWHA Product term clock width high 3.0 3.0 3.5 3.5 4.0 5.0 8.0 9.0 ns tGWS Global gate width low (for low transparent) or high (for high transparent) 4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns tGWA Product term gate width low (for low transparent) or high (for high transparent) 4.0 4.0 4.5 4.5 5.0 5.0 6.0 9.0 ns tWIRL Input register clock width low 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns tWIRH Input register clock width high 3.0 3.0 3.5 3.5 4.0 5.0 6.0 6.0 ns 4.0 4.0 4.5 4.5 5.0 5.0 6.0 6.0 ns tWIL Input latch gate width ispMACH 4A Family 39 ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) -5 -55 -6 -65 -7 -10 -12 -14 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit Frequency: External feedback, D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS) fMAXS fMAXA fMAXI 143 133 125 118 95.2 87.0 74.1 60.6 MHz External feedback, T-type, Min of 1/(tWLS 125 + tWHS) or 1/(tSST + tCOS) 125 118 111 87.0 80.0 69.0 57.1 MHz Internal feedback (fCNT), D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOSi) 182 167 160 154 125 118 95.0 74.1 MHz Internal feedback (fCNT), T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOSi) 154 154 148 143 111 105 87.0 69.0 MHz No feedback2, Min of 1/(tWLS + tWHS), 1/(tSS + tHS) or 1/(tSST + tHS) 250 250 200 200 154 125 100 83.3 MHz External feedback, D-type, Min of 1/ (tWLA + tWHA) or 1/(tSA + tCOA) 111 111 108 100 83.3 66.7 55.6 43.5 MHz External feedback, T-type, Min of 1/(tWLA 105 + tWHA) or 1/(tSAT + tCOA) 105 102 95.2 76.9 62.5 52.6 41.7 MHz Internal feedback (fCNTA), D-type, Min of 133 1/(tWLA + tWHA) or 1/(tSA + tCOAi) 133 125 125 105 83.3 66.7 50.0 MHz Internal feedback (fCNTA), T-type, Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOAi) 125 125 125 118 95.2 76.9 62.5 47.6 MHz No feedback2, Min of 1/(tWLA + tWHA), 1/(tSA + tHA) or 1/(tSAT + tHA) 167 167 143 143 125 100 62.5 55.6 MHz Maximum input register frequency, Min 167 of 1/(tWIRH + tWIRL) or 1/(tSIRS + tHIRS) 167 143 143 125 100 83.3 83.3 MHz Notes: 1. See “Switching Test Circuit” document on the Literature Download page of the Lattice web site. 2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. CAPACITANCE 1 Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input capacitance VIN=2.0 V 3.3 V or 5 V, 25°C, 1 MHz 6 pF CI/O Output capacitance VOUT=2.0V 3.3 V or 5 V, 25°C, 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where this parameter may be affected. 40 ispMACH 4A Family ICC vs. FREQUENCY These curves represent the typical power consumption for a particular device at system frequency. The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power. VCC = 5 V or 3.3 V, TA = 25º C 400 M4A-512/160 350 M4A-384/160 M4A-256/160 300 M4A-256/128 ICC (mA) 250 200 M4A-192/96 150 M4A-96/48 M4A-128/64 M4A-64/64 100 M4A-64/32 50 M4A-32/32 200 180 160 140 120 100 80 60 40 20 0 0 Frequency (MHz) Figure 19. ispMACH 4A ICC Curves at High Speed Mode M4A-512/160 VCC = 5 V or 3.3 V, TA = 25º C 250 M4A-384/160 M4A-256/160 150 M4A-256/128 M4A-192/96 M4A-96/48 M4A-128/64 M4A-64/64 M4A-64/32 100 50 M4A-32/32 200 180 160 140 120 100 80 60 40 20 0 0 ICC (mA) 200 Frequency (MHz) Figure 20. ispMACH 4A ICC Curves at Low Power Mode ispMACH 4A Family 41 44-PIN PLCC CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View A5 A6 A7 B7 B6 B5 B4 I/O2 A5 I/O1 A6 I/O0 A7 I/O31 D7 I/O30 D6 I/O29 D5 I/O28 D4 5 4 3 2 VCC A4 6 GND A3 I/O3 A4 M4A(3,5)-64/32 I/O4 A3 44-Pin PLCC M4A(3,5)-64/32 1 44 43 42 41 40 A2 A2 I/O5 7 39 I/O27 D3 B3 A1 A1 I/O6 8 38 I/O26 D2 B2 A0 A0 I/O7 9 37 I/O25 D1 B1 36 I/O24 D0 B0 M4A(3,5)-32/32 C 7 TDI 10 CLK0/I0 11 35 TDO GND 12 34 GND 33 CLK1/I1 TCK 13 A8 B0 I/O8 14 A9 B1 I/O9 I/O Cell PAL Block 15 A10 B2 I/O10 16 A11 B3 I/O11 17 M4A(3,5)-32/32 32 TMS 31 I/O23 C0 B8 30 I/O22 C1 B9 29 I/O21 C2 B10 C6 I/O17 C5 I/O18 C4 I/O19 C3 I/O20 B14 B13 B12 B11 GND B7 I/O15 A15 C7 I/O16 B6 I/O14 A14 B15 B5 I/O13 VCC B4 I/O12 A13 M4A(3,5)-64/32 A12 18 19 20 21 22 23 24 25 26 27 28 M4A(3,5)-64/32 17466G-026 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 42 ispMACH 4A Family 44-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View A3 A4 A5 A6 A7 B7 B6 B5 B4 D7 D6 D5 D4 M4A(3,5)-64/32 44 43 42 41 40 39 38 37 36 35 34 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 M4A(3,5)-64/32 A3 A4 A5 A6 A7 44-Pin TQFP I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 B0 I/O9 B1 B2 I/O10 B3 I/O11 A2 A1 A0 A2 A1 A0 M4A(3,5)-32/32 C 7 I/O Cell PAL Block 33 32 31 30 29 28 27 26 25 24 23 I/O27 D3 I/O26 D2 I/O25 D1 I/O24 D0 TDO GND CLK1/I1 TMS I/O23 C0 I/O22 C1 I/O21 C2 B3 B2 B1 B0 M4A(3,5)-32/32 B8 B9 B10 B4 B5 B6 B7 C7 C6 C5 C4 C3 A12 A13 A14 A15 B15 B14 B13 B12 B11 M4A(3,5)-64/32 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 12 13 14 15 16 17 18 19 20 21 22 A8 A9 A10 A11 1 2 3 4 5 6 7 8 9 10 11 M4A(3,5)-64/32 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out ispMACH 4A Family 43 48-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View A3 A4 A5 A6 A7 B7 B6 B5 B4 D7 D6 D5 D4 M4A(3,5)-64/32 48 47 46 45 44 43 42 41 40 39 38 37 I/O4 I/O3 I/O2 I/O1 I/O0 GND NC VCC I/O31 I/O30 I/O29 I/O28 M4A(3,5)-64/32 A3 A4 A5 A6 A7 48-Pin TQFP I/O5 I/O6 I/O7 TDI CLK0/I0 NC GND TCK B0 I/O8 B1 I/O9 B2 I/O10 B3 I/O11 A2 A1 A0 A2 A1 A0 M4A(3,5)-32/32 C 7 I/O Cell PAL Block 36 35 34 33 32 31 30 29 28 27 26 25 I/O27 D3 I/O26 D2 I/O25 D1 I/O24 D0 TDO GND NC CLK1/I1 TMS I/O23 C0 I/O22 C1 I/O21 C2 B3 B2 B1 B0 M4A(3,5)-32/32 B8 B9 B10 C7 C6 C5 C4 C3 M4A(3,5)-64/32 B15 B14 B13 B12 B11 A12 A13 A14 A15 B4 B5 B6 B7 M4A(3,5)-64/32 I/O12 I/O13 I/O14 I/O15 VCC NC GND I/O16 I/O17 I/O18 I/O19 I/O20 13 14 15 16 17 18 19 20 21 22 23 24 A8 A9 A10 A11 1 2 3 4 5 6 7 8 9 10 11 12 17466G-028 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O = Input/Output VCC = Supply Voltage NC = No Connect TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out 44 ispMACH 4A Family 100-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-96/48) Top View F7 F6 F5 F4 F3 F2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GND NC NC I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I7 VCC GND NC NC I6 NC I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 NC NC GND A2 A3 A4 A5 A6 A7 100-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 C 7 I/O Cell PAL Block 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC TDO NC NC NC I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I5/CLK3 GND VCC I4/CLK2 I/O35 I/O34 I/O33 I/O32 I/O31 I/O30 NC NC NC NC F1 F0 E0 E1 E2 E3 E4 E5 E6 E7 D0 D1 D7 D6 D5 D4 D3 D2 C2 C3 C4 C5 C6 C7 GND NC NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC I2 NC NC GND VCC I3 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 NC NC GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC TDI NC NC A1 I/O6 A0 I/O7 B0 I/O8 B1 I/O9 B2 I/O10 B3 I/O11 I0/CLK0 VCC GND I1/CLK1 B4 I/O12 B5 I/O13 B6 I/O14 B7 I/O15 C0 I/O16 C1 I/O17 NC NC TMS TCK NC 17466G-029 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage NC = No Connect TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out ispMACH 4A Family 45 100-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-128/64) Top View C H0 H1 H2 H3 H4 H5 H6 H7 (82) (81) (80) (79) (78) (77) (76) (75) 92 91 90 89 88 87 86 85 84 83 82 81 7 I/O Cell PAL Block 80 79 78 77 (73) 76 (72) 75 (71) 74 (70) 73 (69) 72 (68) 71 (67) 70 (66) 69 (65) 68 67 66 65 64 (62) 63 (61) 62 (60) 61 (59) 60 (58) 59 (57) 58 (56) 57 (55) 56 (54) 55 (41) 54 53 52 51 31 (33) 32 (34) 33 (35) 34 (36) 35 (37) 36 (38) 37 (39) 38 (40) 39 40 41 42 43 (45) 44 (46) 45 (47) 46 (48) 47 (49) 48 (50) 49 (51) 50 (52) 1 2 3 4 (83) 5 (12) 6 (13) 7 (14) 8 (15) 9 (16) 10 (17) 11 (18) 12 (19) 13 (20) 14 15 16 17 18 (23) 19 (24) 20 (25) 21 (26) 22 (27) 23 (28) 24 (29) 25 (30) 26 (31) 27 28 29 30 GND GND TD0 TRST G7 I/O55 G6 I/O54 G5 I/O53 I/O52 G4 I/O51 G3 I/O50 G2 I/O49 G1 I/O48 G0 I4/CLK3 GND GND VCC VCC I3/CLK2 I/O47 F0 F1 I/O46 F2 I/O45 F3 I/O44 F4 I/O43 F5 I/O42 F6 I/O41 F7 I/O40 I2 ENABLE GND GND E0 E1 E2 E3 E4 E5 E6 E7 D7 D6 D5 D4 D3 D2 D1 D0 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND TDI I5 B7 I/O8 B6 I/O9 B5 I/O10 B4 I/O11 B3 I/O12 B2 I/O13 B1 I/O14 B0 I/O15 IO/CLK0 VCC VCC GND GND I1/CLK1 C0 I/O16 C1 I/O17 C2 I/O18 C3 I/O19 C4 I/O20 C5 I/O21 C6 I/O22 C7 I/O23 TMS TCK GND GND (10) 100 (9) 99 (8) 98 (7) 97 (6) 96 (5) 95 (4) 94 (3) 93 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 A7 A6 A5 A4 A3 A2 A1 A0 100-Pin PQFP PIN DESIGNATIONS I/CLK = Input or Clock GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out TRST = Test Reset ENABLE = Program 46 ispMACH 4A Family 17466G-031 100-PIN TQFP CONNECTION DIAGRAM (M4A3-64/64 AND M4A(3,5)-128/64) Top View A7 A6 A5 A4 A3 A2 A1 A0 H0 H1 H2 H3 H4 H5 H6 H7 D0 D2 D4 D6 D8 D10 D12 D14 M4A3-128/64 M4A5-128/64 M4A3-64/64 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GND GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I5 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND A14 A12 A10 A8 A6 A4 A2 A0 100-Pin TQFP B7 B6 B5 B4 B3 B2 B1 B0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 C 7 I/O Cell PAL Block 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND TDO TRST I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 ENABLE GND D1 D3 D5 D7 D9 D11 D13 D15 G7 G6 G5 G4 G3 G2 G1 G0 C15 C13 C11 C9 C7 C5 C3 C1 F0 F1 F2 F3 F4 F5 F6 F7 B14 B12 B10 B8 B6 B4 B2 B0 C0 C2 C4 C6 C8 C10 C12 C14 D7 D6 D5 D4 D3 D2 D1 D0 E0 E1 E2 E3 E4 E5 E6 E7 GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 C0 C1 C2 C3 C4 C5 C6 C7 GND TDI I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 VCC GND I1/CLK1 I/O16 B15 I/O17 B13 I/O18 B11 I/O19 B9 I/O20 B7 I/O21 B5 I/O22 B3 I/O23 B1 TMS TCK GND A1 A3 A5 A7 A9 A11 A13 A15 17466G-032a PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out TRST = Test Reset ENABLE = Program ispMACH 4A Family 47 100-BALL caBGA CONNECTION DIAGRAM (M4A3-128/64) Bottom View 100-Ball caBGA 10 9 8 7 6 5 4 3 2 1 A GND I/O63 H7 I/O60 H4 I/O57 H1 GND GND I/O1 A1 I/O4 A4 I/O7 A7 GND A B TRST GND I/O61 H5 I5 VCC I/O0 A0 I/O6 A6 GND TDI I/O15 B7 B C I/O53 G5 TDO I/O62 H6 I/O58 H2 I/O56 H0 I/O2 A2 GND I/O14 B6 I/O13 B5 I/O12 B4 C D I/O50 G2 I/O55 G7 GND I/O59 H3 I/O3 A3 I/O5 A5 I/O11 B3 I/O10 B2 CLK0/I0 I/O9 B1 D E CLK3/I3 I/O49 G1 I/O51 G3 I/O54 G6 VCC I/O16 C0 I/O20 C4 I/O8 B0 VCC GND E F GND VCC I/O40 F0 I/O52 G4 I/O48 G0 VCC I/O22 C6 I/O19 C3 I/O17 C1 G I/O41 F1 CLK2/I2 I/O42 F2 I/O43 F3 I/O37 E5 I/O35 E3 I/O27 D3 GND I/O23 C7 I/O18 C2 G H I/O44 F4 I/O45 F5 I/O46 F6 GND I/O34 E2 I/O24 D0 I/O26 D2 I/O30 D6 TCK I/O21 C5 H J I/O47 F7 ENABLE GND I/O38 E6 I/O32 E0 VCC I2 I/O29 D5 GND TMS J K GND I/O39 E7 I/O36 E4 I/O33 E1 GND GND I/O25 D1 I/O28 D4 I/O31 D7 GND K 10 9 8 7 6 5 4 3 2 1 CLK1/I1 F PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell PAL Block 17466G-100cabga 48 ispMACH 4A Family 144-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-192/96) Top View L0 L1 L2 L3 L4 L5 L6 L7 A7 A6 A5 A4 A3 A2 A1 A0 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 I1 I0 CLK0 GND VCC CLK3 I15 I14 I13 I/O79 I/O78 I/O77 I/O76 I/O75 I/O74 I/O73 I/O72 GND B7 B6 B5 B4 B3 B2 B1 B0 144-Pin TQFP D7 D6 D5 D4 D3 D2 D1 D0 C7 C6 C5 C4 C3 C2 C1 C0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 C 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 7 I/O Cell PAL Block GND TDO NC I/O71 I/O70 I/O69 I/O68 I/O67 I/O66 I/O65 I/O64 I12 VCC GND I11 I10 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND VCC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 NC GND K0 K1 K2 K3 K4 K5 K6 K7 J0 J1 J2 J3 J4 J5 J6 J7 I0 I1 I2 I3 I4 I5 I6 I7 H0 H1 H2 H3 H4 H5 H6 H7 G0 G1 G2 G3 G4 G5 G6 G7 F7 F6 F5 F4 F3 F2 F1 F0 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I5 I6 I7 CLK1 GND VCC CLK2 I8 I9 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 VCC GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 E7 E6 E5 E4 E3 E2 E1 E0 GND TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I2 I3 VCC GND I4 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND VCC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND 17466G-033 PIN DESIGNATIONS CLK = Clock GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out ispMACH 4A Family 49 144-BALL fpBGA CONNECTION DIAGRAM (M4A3-192/96) Bottom View 144-Ball fpBGA 12 11 10 9 8 7 6 5 4 3 2 1 A GND I/O95 L7 I/O91 L3 I13 GBCLK3 I0 I/O2 A2 I/O6 A6 I/O8 B0 I/O13 B5 I/O15 B7 GND A B GND I/O94 L6 I/O90 L2 I/O88 L0 VCC I1 I/O3 A3 I/O7 A7 I/O10 B2 I/O14 B6 I/O31 D7 TDI B C GND TDO I/O93 L5 I14 GND I/O0 A0 I/O4 A4 GND I/O12 B4 I/O30 D6 I/O27 D3 I/O28 D4 C D I/O84 K4 I/O82 K2 I/O80 K0 I/O92 L4 GBCLK0 I/O1 A1 VCC I/O11 B3 I/O29 D5 I2 I/O25 D1 I/O24 D0 D E I12 I/O87 K7 I/O85 K5 I/O81 K1 I/O89 L1 I/O5 A5 I/O9 B1 I/O26 D2 I/O23 C7 I4 GND VCC E F I10 I11 GND I/086 K6 I/O83 K3 I15 I3 GND I/O19 C3 I/O20 C4 I/O21 C5 I/O22 C6 F G I/O75 J3 I/O74 J2 I/O73 J1 I/O72 J0 VCC GND I7 I/O35 E3 I/O38 E6 I/O16 C0 I/O17 C1 I/O18 C2 G H I/O79 J7 I/O78 J6 I/O77 J5 I/O76 J4 I/O66 I2 I/O57 H1 I/O53 G5 I/O41 F1 I/O33 E1 I/O37 E5 I/O39 E7 VCC H J I/O64 I0 I/O65 I1 VCC I/O69 I5 I/O59 H3 VCC I/O49 G1 GBCLK2 I/O44 F4 I/O32 E0 I/O34 E2 I/O36 E4 J K I/O68 I4 I/O67 I3 I/O70 I6 I/O60 H4 GND I/O52 G4 I/O48 G0 VCC I6 I/O45 F5 TCK TMS K L GND I/O71 I7 I/O62 H6 I/O58 H2 I/O55 G7 I/O51 G3 I9 GND I/O40 F0 I/O42 F2 I/O46 F6 GND L M GND I/O63 H7 I/O61 H5 I/O56 H0 I/O54 G6 I/O50 G2 I8 GBCLK1 I5 I/O43 F3 I/O47 F7 GND M 12 11 10 9 8 7 6 5 4 3 2 1 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell PAL Block m4a3.192.96_144bga 50 ispMACH 4A Family 208-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-256/128 AND M4A3-256/160) Top View O8 O9 O10 O11 O12 O13 O14 O15 P12 P14 O0 O1 O2 O3 O4 O5 O6 O7 A6 A4 P4 P6 B7 B6 B5 B4 B3 B2 B1 B0 A14 A12 M4A3-256/160 O0 O1 O2 O3 O4 O5 O6 O7 P0 P1 P2 P3 P4 P5 P6 P7 A7 A6 A5 A4 A3 A2 A1 A0 M4A(3, 5)256/128 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 GND I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I1 I0 CLK0 VCC GND GND VCC VCC GND GND VCC CLK3 I13 I12 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 VCC GND I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND B7 B6 B5 B4 B3 B2 B1 B0 GND I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 CLK0 VCC GND I/O1 I/O0 I/O159 I/O158 GND VCC CLK3 I/O157 I/O156 I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 VCC GND I/O147 I/O146 I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 GND B15 B14 B13 B12 B11 B10 B9 B8 208-Pin PQFP PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 GND TDO TRST I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 VCC GND I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 I/O96 I11 GND VCC VCC GND GND VCC VCC GND I10 I9 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 ENABLE GND N7 N6 N5 N4 N3 N2 N1 N0 M7 M6 M5 M4 M3 M2 M1 M0 L0 L1 L2 L3 L4 L5 L6 L7 K0 K1 K2 K3 K4 K5 K6 K7 GND TDO NC I/O139 I/O138 I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 VCC GND I/O131 I/O130 I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 GND I/O122 I/O121 I/O120 I/O119 I/O118 VCC GND I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 GND VCC I/O107 I/O106 I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 NC GND N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 M10 M6 M2 M0 L4 L6 L12 L14 K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 J0 J1 J2 J3 J4 J5 J6 J7 I0 I1 I2 I3 I4 I5 I6 I7 H7 H6 H5 H4 H3 H2 H1 H0 J8 J9 J10 J11 J12 J13 J14 J15 I12 I14 J0 J1 J2 J3 J4 J5 J6 J7 H6 H4 I4 I6 G7 G6 G5 G4 G3 G2 G1 G0 H14 H12 F0 F1 F2 F3 F4 F5 F6 F7 156 155 RECOMMEND TO TIE TO VCC 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 I/O Cell 124 123 PAL Block 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 RECOMMEND TO TIE TO GND 106 105 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 F8 F9 F10 F11 F12 F13 F14 F15 E0 E1 E2 E3 E4 E5 E6 E7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 GND I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND VCC I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I5 I6 CLK1 VCC GND GND VCC VCC GND GND VCC CLK2 I7 I8 I/O64 I/O66 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 VCC GND I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 GND E10 F0 F1 F2 F3 F4 F5 F6 F7 D7 D6 D5 D4 D3 D2 D1 D0 GND TDI I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 I3 GND VCC VCC GND GND VCC VCC GND I4 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND VCC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 TMS TCK GND G7 G6 G5 G4 G3 G2 G1 G0 D6 D4 E0 E2 E6 C7 C6 C5 C4 C3 C2 C1 C0 GND I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 I/O66 I/O67 GND VCC I/O68 I/O69 I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 CLK1 VCC GND I/O78 I/O79 I/O80 I/O81 GND VCC CLK2 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 I/O90 I/O91 VCC GND I/O92 I/O93 I/O94 I/O95 I/O96 I/O97 I/O98 I/O99 GND C7 C6 C5 C4 C3 C2 C1 C0 D14 D12 GND TDI I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 VCC GND I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 GND VCC I/O38 I/O39 I/O40 I/O41 I/O42 GND I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 GND VCC I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 TMS TCK GND G15 G14 G13 G12 G11 G10 G9 G8 C15 C14 C13 C12 C11 C10 C9 C8 17466G-044 ispMACH 4A Family 51 208-PIN PQFP CONNECTION DIAGRAM (M4A3-384/160 AND M4A3-512/160) Top View XO0 XO1 XO2 XO3 XO4 XO5 XO6 XO7 XP6 XP7 XN0 XN1 XN2 XN3 XN4 XN5 XN6 XN7 A4 A1 XP1 XP4 C7 C6 C5 C4 C3 C2 C1 C0 A7 A6 M4A3-512/160 XG0 XG1 XG2 XG3 XG4 XG5 XG6 XG7 XH6 XH7 XE0 XE1 XE2 XE3 XE4 XE5 XE6 XE7 A4 A1 XH1 XH4 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 M4A3-384/160 F7 F6 F5 F4 F3 F2 F1 F0 G7 G6 G5 G4 G3 G2 G1 G0 E7 E5 E2 E0 L0 L2 L3 L5 J0 J1 J2 J3 J4 J5 J6 J7 C7 C6 C5 C4 C3 C2 C1 C0 F7 F6 F5 F4 F3 F2 F1 F0 E7 E5 E2 E0 H0 H2 H3 H5 G0 G1 G2 G3 G4 G5 G6 G7 J0 J1 J2 J3 J4 J5 J6 J7 GND TDI I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 VCC GND I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 GND VCC I/O36 I/O37 I/O38 I/O39 I/O40 GND I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 GND VCC I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 TMS TCK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 RECOMMEND TO TIE TO VCC 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 I/O Cell 124 123 PAL Block 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 RECOMMEND TO TIE TO GND 106 105 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 GND TDO NC I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 VCC GND I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 GND I/O120 I/O119 I/O118 I/O117 I/O116 VCC GND I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 GND VCC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 NC GND XF7 XF6 XF5 XF4 XF3 XF2 XF1 XF0 XC7 XC6 XC5 XC4 XC3 XC2 XC1 XC0 XD5 XD3 XD2 XD0 XA0 XA2 XA5 XA7 XB0 XB1 XB2 XB3 XB4 XB5 XB6 XB7 O0 O1 O2 O3 O4 O5 O6 O7 GND TDO NC I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 VCC GND I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 GND I/O120 I/O119 I/O118 I/O117 I/O116 VCC GND I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 GND VCC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 NC GND XK7 XK6 XK5 XK4 XK3 XK2 XK1 XK0 XJ7 XJ6 XJ5 XJ4 XJ3 XJ2 XJ1 XJ0 XL5 XL3 XL2 XL0 XE0 XE2 XE5 XE7 XG0 XG1 XG2 XG3 XG4 XG5 XG6 XG7 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 N0 N1 N2 N3 N4 N5 N6 N7 M6 M7 P0 P1 P2 P3 P4 P5 P6 P7 L4 L1 M1 M4 I7 I6 I5 I4 I3 I2 I1 I0 L7 L6 XB0 XB1 XB2 XB3 XB4 XB5 XB6 XB7 XA6 XA7 XC0 XC1 XC2 XC3 XC4 XC5 XC6 XC7 P4 P1 XA1 XA4 N7 N6 N5 N4 N3 N2 N1 N0 P7 P6 O7 O6 O5 O4 O3 O2 O1 O0 GND I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 GND VCC I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 CLK1 VCC GND I/O76 I/O77 I/O78 I/O79 GND VCC CLK2 I/O80 I/O81 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 VCC GND I/O90 I/O91 I/O92 I/O93 I/O94 I/O95 I/O96 I/O97 GND K7 K6 K5 K4 K3 K2 K1 K0 GND I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 GND VCC I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 CLK1 VCC GND I/O76 I/O77 I/O78 I/O79 GND VCC CLK2 I/O80 I/O81 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 VCC GND I/O90 I/O91 I/O92 I/O93 I/O94 I/O95 I/O96 I/O97 GND 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 K0 K1 K2 K3 K4 K5 K6 K7 GND TDI I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 VCC GND I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 GND VCC I/O36 I/O37 I/O38 I/O39 I/O40 GND I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 GND VCC I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 TMS TCK GND 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 GND I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 GND VCC I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLK0 VCC GND I/O159 I/O158 I/O157 I/O156 GND VCC CLK3 I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 VCC GND I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 I/O139 I/O138 GND B7 B6 B5 B4 B3 B2 B1 B0 GND I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 GND VCC I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLK0 VCC GND I/O159 I/O158 I/O157 I/O156 GND VCC CLK3 I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 VCC GND I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 I/O139 I/O138 GND B7 B6 B5 B4 B3 B2 B1 B0 208-Pin PQFP 17466Ga-044 52 ispMACH 4A Family 256-BALL BGA CONNECTION DIAGRAM (M4A(3,5)-256/128) Bottom View 256-Ball BGA 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A GND N/C GND I/O108 N4 I/O105 N1 GND I/O100 M4 I/O96 M0 GND GND GND GND I/O95 L0 I/O91 L4 GND I/O87 K0 N/C GND GND GND A B GND I/O113 O6 N/C I/O109 N5 I/O106 N2 I/O103 M7 I/O102 M6 I/O98 M2 N/C I11 N/C N/C I/O93 L2 I/O89 L6 I/O88 L7 I/O85 K2 I/O83 K4 I/O82 K5 N/C GND B C I/O116 O3 N/C VCC TRST I/O111 N7 I/O107 N3 I/O104 N0 I/O101 M5 I/O97 M1 N/C I10 I/O94 L1 I/O90 L5 I/O86 K1 I/O84 K3 I/O80 K7 ENABLE VCC I/O78 J6 I/O74 J2 C D I/O120 P7 I/O117 O2 I/O112 O7 VCC VCC I/O110 N6 VCC N/C I/O99 M3 N/C I9 I/O92 L3 N/C VCC I/O81 K6 VCC VCC I/O79 J7 I/O75 J3 I/O71 I7 D E I/O123 P4 I/O119 O0 I/O114 O5 TDI TDO I/O77 J5 I/O72 J0 I/O68 I4 E F GND I/O122 P5 I/O118 O1 I/O115 O4 I/O76 J4 I/O73 J1 I/O69 I5 GND F G I12 I/O125 P2 I/O121 P6 VCC VCC I/O70 I6 I/O65 I1 I8 G H GND I/O127 P0 I/O126 P1 I/O124 P3 I/O67 I3 I/O66 I2 I/O64 I0 GND H J N/C N/C N/C I13 I7 N/C N/C N/C J K GND CLK3 N/C N/C N/C N/C CLK2 N/C K L N/C CLK0 N/C N/C N/C N/C CLK1 GND L M N/C N/C N/C I0 I6 N/C I/O63 H0 I/O62 H1 M I/O60 H3 I/O61 H2 I/O59 H4 GND N PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell PAL Block N GND I/O0 A0 I/O2 A2 I/O3 A3 P I1 I/O1 A1 I/O6 A6 VCC VCC I/O57 H6 I/O58 H5 I5 P R GND I/O5 A5 I/O9 B1 N/C I/O51 G4 I/O54 G1 I/O56 H7 GND R T I/O4 A4 I/O8 B0 I/O12 B4 TCK TMS I/O50 G5 I/O55 G0 N/C T U I/O7 A7 I/O11 B3 I/O15 B7 VCC VCC I/O18 C5 VCC I/O24 D7 I/O29 D2 I2 N/C I/O35 E3 N/C VCC N/C VCC VCC I/O48 G7 I/O53 G2 N/C U V I/O10 B2 I/O13 B5 VCC I/O16 C7 I/O17 C6 I/O21 C2 I/O23 C0 I/O27 D4 I/O31 D0 I3 N/C I/O33 E1 I/O37 E5 I/O41 F1 I/O43 F3 I/O46 F6 I/O47 F7 VCC I/O52 G3 N/C V W GND I/O14 B6 N/C N/C I/O19 C4 I/O22 C1 I/O25 D6 I/O28 D3 N/C N/C I4 N/C I/O34 E2 I/O38 E6 I/O39 E7 I/O42 F2 I/O45 F5 N/C I/O49 G6 GND W Y GND GND GND N/C I/O20 C3 GND I/O26 D5 I/O30 D1 GND GND GND GND I/O32 E0 I/O36 E4 GND I/O40 F0 I/O44 F4 GND N/C GND Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17466G-045 ispMACH 4A Family 53 256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/192) Bottom View 256-Ball fpBGA 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A I/O167 N15 I/O181 O13 I/O180 O12 I/O177 O9 I/O174 O6 I/O172 O4 I/O191 P14 I/O186 P4 I/O1 A2 I/O3 A6 GCLK0 I/O9 B1 I/O13 B5 I/O15 B7 I/O18 B10 I/O20 B12 A B I/O165 N13 I/O166 N14 I/O182 O14 I/O179 O11 I/O175 O7 I/O173 O5 I/O168 O0 I/O187 P6 I/O0 A0 I/O5 A10 I/O7 A14 I/O10 B2 I/O16 B8 I/O19 B11 I/O21 B13 NC B C I/O163 N11 I/O164 N12 NC I/O183 O15 I/O178 O10 I/O170 O2 I/O171 O3 I/O189 P10 I/O184 P0 I/O6 A12 I/O12 B4 I/O14 B6 I/O23 B15 I/O22 B14 TDI I/O39 C15 C D I/O158 N6 I/O159 N7 TDO GND GND VCC GND VCC GND GND VCC GND VCC I/O17 B9 I/O38 C14 I/O37 C13 D E I/O156 N4 NC I/O162 N10 VCC I/O160 N8 I/O161 N9 I/O190 GCLK3 I/O188 P12 P8 I/O2 A4 I/O8 B0 NC GND I/O36 C12 I/O35 C11 I/O31 C7 E F I/O152 N0 I/O157 N5 I/O155 N3 GND I/O154 N2 I/O153 N1 I/O176 O8 I/O169 O1 I/O185 P2 I/O4 A8 I/O11 B3 I/O34 C10 VCC I/O32 C8 I/O30 C6 I/O29 C5 F G I/O147 M6 I/O150 M12 I/O149 M10 VCC I/O148 M8 I/O151 M14 VCC GND GND VCC I/O33 C9 I/O28 C4 GND I/O26 C2 I/O25 C1 I/O47 D14 G H I/O144 M0 I/O146 M4 I/145 OM2 GND I/O136 L0 I/O137 L2 GND VCC VCC GND I/O27 C3 I/O24 C0 VCC I/O44 D8 I/O43 D6 I/O42 D4 H J I/O138 L4 I/O139 L6 I/O140 L8 GND I/O142 L12 I/O141 L10 GND VCC VCC GND I/O46 D12 I/O45 D10 GND I/O49 E2 I/O48 E0 I/O50 E4 J K I/O143 L14 I/O120 K0 I/O121 K1 VCC I/O123 K3 I/O122 K2 VCC GND GND VCC I/O41 D2 I/O40 D0 VCC I/O55 E14 I/O54 E12 I/O56 F0 K L I/O124 K4 I/O125 K5 I/O127 K7 GND I/O130 K10 I/O126 K6 I/O98 I4 I/O91 H6 I/O75 G3 I/O77 G5 I/O52 E8 I/O51 E6 GND I/O59 F3 I/O60 F4 I/O57 F1 L M I/O128 K8 I/O129 K9 I/O131 K11 GND I/O107 J3 I/O105 J1 I/O100 I8 I/O90 H4 I/O74 G2 I/O80 G8 I/O83 G11 I/O53 E10 VCC I/O68 F12 I/O63 F7 I/O58 F2 M N I/O132 K12 I/O133 K13 I/O135 K15 VCC GND VCC GND VCC GND GND VCC GND GND TCK I/O64 F8 I/O61 F5 N P I/O134 K14 I/O117 J13 I/O118 J14 I/O119 J15 I/O108 J4 I/O106 J2 I/O101 I10 I/O89 H2 I/O93 H10 I/O94 H12 I/O79 G7 I/O84 G12 I/O87 G15 TMS I/O65 F9 I/O62 F6 P R I/O116 J12 I/O115 J11 I/O112 J8 I/O111 J7 I/O104 J0 I/O102 I12 I/O99 I6 I/O96 I0 I/O92 H8 I/O72 G0 I/O76 G4 I/O81 G9 I/O85 G13 I/O71 F15 I/O67 F11 I/O66 F10 R T I/O114 J10 I/O113 J9 I/O110 J6 I/O109 J5 I/O103 GCLK2 I14 I/O97 I2 I/O88 H0 GCLK1 I/O95 H14 I/O73 G1 I/O78 G6 I/O82 G10 I/O86 G14 I/O70 F14 I/O69 F13 T 16 15 14 13 10 9 8 7 6 5 4 3 2 1 12 11 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE 54 = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 ispMACH 4A Family I/O Cell PAL Block 17466G-047 256-BALL BGA CONNECTION DIAGRAM - (M4A3-384/192) Bottom View 256-Ball BGA 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A GND I/O11 XF7 GND I/O44 XF6 I/O58 XC6 GND I/O70 XC2 I/O76 XD6 GND GND GND GND I/O108 XA5 I/O116 XB0 GND I/O128 XB7 I/O134 O3 GND GND GND A B GND I/O12 XG7 I/O28 XF5 I/O45 XF3 I/O59 XC7 I/O64 XC5 I/O71 XC3 I/O77 XD7 I/O84 XD5 I/O90 XD2 I/O96 XA0 I/O102 XA3 I/O109 XA6 I/O117 XB1 I/O122 XB4 I/O129 XB6 I/O135 O4 I/O148 O6 I/O164 O7 GND B C I/O0 XG6 I/O13 XG5 VCC I/O46 XF4 I/O60 XF2 I/O65 XF1 I/O72 XC4 I/O78 XC0 I/O85 XD4 I/O91 XD1 I/O97 XA1 I/O103 XA4 I/O110 XB2 I/O118 XB5 I/O123 O0 I/O130 O1 I/O136 O5 VCC I/O165 N7 I/O181 N6 C D I/O1 XE7 I/O14 XG3 I/O29 XG4 VCC VCC I/O66 XF0 VCC I/O79 XC1 I/O86 XD3 I/O92 XD0 I/O98 XA2 I/O104 XA7 I/O111 XB3 VCC I/O124 O2 VCC VCC I/O149 N4 I/O166 N5 I/O182 P7 D E I/O2 XE0 I/O15 XG0 I/O30 XG1 TDI TDO I/O150 N2 I/O167 N3 I/O183 P6 E F GND I/O16 XE1 I/O31 XE6 I/O47 XG2 I/O137 N1 I/O151 N0 I/O168 P5 GND F G I/O3 XH6 I/O17 XE4 I/O32 XE5 VCC VCC I/O152 P4 I/O169 P3 I/O184 M7 G H GND I/O18 XH5 I/O33 XE2 I/O48 XE3 I/O138 P2 I/O153 P1 I/O170 P0 GND H I/O139 M6 I/O154 M5 I/O171 M4 I/O185 M3 J I/O140 M0 I/O155 M1 CLK2 I/O186 M2 K I/O141 L3 I/O156 L4 CLK1 GND L I/O142 L6 I/O157 L5 I/O172 L0 I/O187 L1 M I/O143 I5 I/O158 I0 I/O173 L7 GND N J I/O4 XH0 I/O19 XH1 I/O34 XH4 I/O49 XH7 K GND CLK3 I/O35 XH2 I/O50 XH3 L I/O5 A2 CLK0 I/O36 A0 I/O51 A1 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out C 7 M I/O6 A4 I/O20 A3 I/O37 A5 I/O52 A6 N GND I/O21 A7 I/O38 D0 I/O53 D1 P I/O7 D2 I/O22 D3 I/O39 D4 VCC VCC I/O159 I4 I/O174 I1 I/O188 L2 P R GND I/O23 D5 I/O40 D6 I/O54 D7 I/O144 K5 I/O160 K0 I/O175 I3 GND R T I/O8 B3 I/O24 B0 I/O41 B7 TCK TMS I/O161 K4 I/O176 K1 I/O189 I2 T U I/O9 B4 I/O25 B1 I/O42 B6 VCC VCC I/O67 C0 VCC I/O80 F0 I/O87 E5 I/O93 E2 I/O99 H2 I/O105 H5 I/O112 G0 VCC I/O125 J1 VCC VCC I/O162 K7 I/O177 K2 I/O190 I6 U V I/O10 B5 I/O26 B2 VCC I/O55 C5 I/O61 C2 I/O68 C1 I/O73 F4 I/O81 F1 I/O88 E4 I/O94 E1 I/O100 H1 I/O106 H4 I/O113 G1 I/O119 G4 I/O126 J0 I/O131 J2 I/O145 J5 VCC I/O178 K3 I/O191 I7 V W GND I/O27 C7 I/O43 C6 I/O56 C3 I/O62 F7 I/O69 F5 I/O74 F3 I/O82 E7 I/O89 E3 I/O95 E0 I/O101 H0 I/O107 H3 I/O114 H7 I/O120 G3 I/O127 G5 I/O132 G7 I/O146 J4 I/O163 J6 I/O179 J7 GND W Y GND GND GND I/O57 C4 I/O63 F6 GND I/O75 F2 I/O83 E6 GND GND GND GND I/O115 H6 I/O121 G2 GND I/O133 G6 I/O147 J3 GND I/O180 K6 GND Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 I/O Cell PAL Block 17466G-046 ispMACH 4A Family 55 256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/128) Bottom View 256-Ball fpBGA 16 15 14 13 12 11 A TRST I/O117 O5 I/O116 O4 I/O113 O1 I/O126 P6 I/O124 P4 10 9 8 7 6 5 4 3 2 1 NC CLK0 I/O1 A1 I/O5 A5 I/O7 A7 I/O10 B2 I/O12 B4 I12 NC NC A B I/O110 N6 I/O111 N7 I/O118 O6 I/O115 O3 I/O127 P7 I/O125 P5 I/O120 P0 NC NC NC I1 I/O2 A2 I/O8 B0 I/O11 B3 I/O13 B5 NC B C I/O108 N4 I/O109 N5 NC I/O119 O7 I/O114 O2 I/O122 P2 I/O123 P3 NC NC I0 I/O4 A4 I/O6 A6 I/O5 B7 I/O14 B6 TDI I/O23 C7 C D NC I/O104 N0 TDO GND GND VCC GND VCC GND GND VCC GND VCC I/O9 B1 I/O22 C6 I/O21 C5 D E I/O102 M6 NC I/O107 N3 VCC I/O105 N1 I/O106 N2 I13 CLK3 NC NC I/O0 A0 NC GND I/O20 C4 I/O19 C3 I/O31 D7 E F I/O98 M2 I/O103 M7 I/O101 M5 GND I/O100 M4 I/O99 M3 I/O112 O0 I/O121 P1 NC NC I/O3 A3 I/O18 C2 VCC I/O16 C0 I/O30 D6 I/O29 D5 F G NC I/O96 M0 I11 VCC NC I/O97 M1 VCC GND GND VCC I/O17 C1 I/O28 D4 GND I/O26 D2 I/O25 D1 I2 G H I/O88 L0 I10 I9 GND I/O89 L1 I/O90 L2 GND VCC VCC GND I/O27 D3 I/O24 D0 VCC NC NC NC H J I/O91 L3 I/O92 L4 I/O93 L5 GND I/O95 L7 I/O94 L6 GND VCC VCC GND I3 NC GND NC NC NC J K NC NC NC VCC NC NC VCC GND GND VCC NC NC VCC I4 NC I/O32 E0 K L NC NC I/O80 K0 GND I/O83 K3 NC NC NC I/O59 H3 I/O61 H5 NC NC GND I/O35 E3 I/O36 E4 I/O33 E1 L M I/O81 K1 I/O82 K2 I/O84 K4 GND I/O67 I3 I/O65 I1 NC NC I/O58 H2 I/O48 G0 I/O51 G3 NC VCC I/O44 F4 I/O39 E7 I/O34 E2 M N I/O85 K5 I/O86 K6 TENB VCC GND VCC GND VCC GND GND VCC GND GND TCK I/O40 F0 I/O37 E5 N P I/O87 K7 I/O77 J5 I/O78 J6 I/O79 J7 I/O68 I4 I/O66 I2 NC NC NC I6 I/O63 H7 I/O52 G4 I/O55 G7 TMS I/O41 F1 I/O38 E6 P R I/O76 J4 I/O75 J3 I/O72 J0 I/O71 I7 I/O64 I0 I7 NC NC NC I/O56 H0 I/O60 H4 I/O49 G1 I/O53 G5 I/O47 F7 I/O43 F3 I/O42 F2 R T I/O74 J2 I/O73 J1 I/O70 I6 I/O69 I5 I8 CLK2 NC NC CLK1 I5 I/O57 H1 I/O62 H6 I/O50 G2 I/O54 G6 I/O46 F6 I/O45 F5 T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE 56 = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 ispMACH 4A Family I/O Cell PAL Block m4a3.256.128_256bga 256-BALL fpBGA CONNECTION DIAGRAM (M4A3-384/192) Bottom View 256-Ball fpBGA 8 7 6 5 4 3 2 1 A I/O175 I/O181 I/O180 I/O177 I/O166 I/O164 I/O191 I/O186 FX7 GX5 GX4 GX1 EX6 EX4 HX7 HX2 16 I/O1 A1 I/O3 A3 CLK0 I/O25 D1 I/O29 D5 I/O31 D7 I/O10 B2 I/O12 B4 A B I/O173 I/O174 I/O182 I/O179 I/O167 I/O165 I/O160 I/O187 FX5 FX6 GX6 GX3 EX7 EX5 EX0 HX3 I/O0 A0 I/O5 A5 I/O7 A7 I/O26 D2 I/O8 B0 I/O11 B3 I/O13 B5 N/C B C I/O171 I/O172 FX3 FX4 N/C I/O6 A6 I/O28 D4 I/O30 D6 I/O15 B7 I/O14 B6 TDI I/O23 C7 C D I/O150 I/O151 CX6 CX7 TDO GND GND VCC GND VCC GND GND VCC GND VCC I/O9 B1 I/O22 C6 I/O21 C5 D E I/O148 CX4 I/O170 FX2 VCC I/O168 FX0 169 FX1 I/O190 HX6 CLK3 I/O188 HX4 I/O2 A2 I/O24 D0 N/C GND I/O20 C4 I/O19 C3 I/O47 F7 E F I/O144 I/O149 I/O147 CX0 CX5 CX3 GND I/O146 I/O145 I/O176 I/O161 I/O185 CX2 CX1 GX0 EX1 HX1 I/O4 A4 I/O27 D3 I/O18 C2 VCC I/O16 C0 I/O46 F6 I/O45 F5 F G I/O155 I/O158 I/O157 DX3 DX6 DX5 VCC I/O156 I/O159 DX4 DX7 VCC GND GND VCC I/O17 C1 I/O44 F4 GND I/O42 F2 I/O41 F1 I/O39 E7 G H I/O152 I/O154 I/O153 DX0 DX2 DX1 GND I/O128 I/O129 AX0 AX1 GND VCC VCC GND I/O43 F3 I/O40 F0 VCC I/O36 E4 I/O35 E3 I/O34 E2 H J I/O130 I/O131 I/O132 AX2 AX3 AX4 GND I/O134 I/O133 AX6 AX5 GND VCC VCC GND I/O38 E6 I/O37 E5 GND I/O57 H1 I/O56 H0 I/O58 H2 J K I/O135 I/O136 I/O137 AX7 BX0 BX1 VCC I/O139 I/O138 BX3 BX2 VCC GND GND VCC I/O33 E1 I/O32 E0 VCC I/O63 H7 I/O62 H6 I/O48 G0 K L I/O140 I/O141 I/O143 BX4 BX5 BX7 GND I/O114 I/O142 O2 BX6 I/O98 M2 I/O91 L3 I/O67 I3 I/O69 I5 I/O60 H4 I/O59 H3 GND I/O51 G3 I/O52 G4 I/O49 G1 L M I/O112 I/O113 I/O115 O0 O1 O3 GND I/O123 I/O121 I/O100 P3 P1 M4 I/O90 L2 I/O66 I2 I/O80 K0 I/O83 K3 I/O61 H5 VCC I/O76 J4 I/O55 G7 I/O50 G2 M N I/O116 I/O117 I/O119 O4 O5 O7 VCC VCC GND GND VCC GND GND TCK I/O72 J0 I/O53 G5 N P I/O118 I/O109 I/O110 I/O111 I/O124 I/O122 I/O101 O6 N5 N6 N7 P4 P2 M5 I/O89 L1 I/O93 L5 I/O94 L6 I/O71 I7 I/O84 K4 I/O87 K7 TMS I/O73 J1 I/O54 G6 P R I/O108 I/O107 I/O104 I/O127 I/O120 I/O102 N4 N3 N0 P7 P0 M6 I/O99 M3 I/O96 M0 I/O92 L4 I/O64 I0 I/O68 I4 I/O81 K1 I/O85 K5 I/O79 J7 I/O75 J3 I/O74 J2 R T I/O106 I/O105 I/O126 I/O125 I/O103 N2 N1 P6 P5 M7 CLK2 I/O97 M1 I/O88 L0 CLK1 I/O95 L7 I/O65 I1 I/O70 I6 I/O82 K2 I/O86 K6 I/O78 J6 I/O77 J5 T 11 10 9 8 7 6 5 4 3 2 1 16 15 N/C 15 14 14 13 12 11 10 9 I/O183 I/O178 I/O162 I/O163 I/O189 I/O184 GX7 GX2 EX2 EX3 HX5 HX0 13 GND 12 VCC GND PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell PAL Block m4a3.384.192_256bga ispMACH 4A Family 57 256-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/192) Bottom View 256-Ball fpBGA 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A I/O159 I/O181 I/O180 I/O177 I/O174 I/O172 I/O191 I/O186 KX7 OX5 OX4 OX1 NX6 NX4 PX7 PX2 I/O1 A1 I/O3 A3 CLK0 I/O17 C1 I/O21 C5 I/O21 C7 I/O10 B2 I/O12 B4 A B I/O157 I/O158 I/O182 I/O179 I/O175 I/O173 I/O168 I/O187 KX5 KX6 OX6 OX3 NX7 NX5 NX0 PX3 I/O0 A0 I/O5 A5 I/O7 A7 I/O18 C2 I/O8 B0 I/O11 B3 I/O13 B5 N/C B C I/O155 I/O156 KX3 KX4 N/C I/O6 A6 I/O20 C4 I/O22 C6 I/O15 B7 I/O14 B6 TDI I/O39 F7 C D I/O150 I/O151 JX6 JX7 TDO GND GND VCC GND VCC I/O9 B1 I/O38 F6 I/O37 F5 D E I/O148 JX4 I/O154 KX2 VCC I/O152 I/O153 I/O190 KX0 KX1 PX6 CLK3 I/O188 PX4 I/O2 A2 I/O16 C0 N/C GND I/O36 F4 I/O35 F3 I/O47 G7 E F I/O144 I/O149 I/O147 JX0 JX5 JX3 GND I/O146 I/O145 I/O176 I/O169 I/O185 JX2 JX1 OX0 NX1 PX1 I/O4 A4 I/O19 C3 I/O34 F2 VCC I/O32 F0 I/O46 G6 I/O45 G5 F G I/O163 I/O166 I/O165 LX3 LX6 LX5 VCC I/O164 I/O167 LX4 LX7 VCC GND GND VCC I/O33 F1 I/O44 G4 GND I/O42 G2 I/O41 G1 I/O31 E7 G H I/O160 I/O162 I/O161 LX0 LX2 LX1 GND I/O120 I/O121 EX0 EX1 GND VCC VCC GND I/O43 G3 I/O40 G0 VCC I/O28 E4 I/O27 E3 I/O26 E2 H J I/O122 I/O123 I/O124 EX2 EX3 EX4 GND I/O126 I/O125 EX6 EX5 GND VCC VCC GND I/O30 E6 I/O29 E5 GND I/O65 L1 I/O64 L0 I/O66 L2 J K I/O127 I/O136 I/O137 EX7 GX0 GX1 VCC I/O139 I/O138 GX3 GX2 VCC GND GND VCC I/O25 E1 I/O24 E0 VCC I/O71 L7 I/O70 L6 I/O48 J0 K L I/O140 I/O141 I/O143 GX4 GX5 GX7 GND I/O130 I/O142 FX2 GX6 I/O98 AX2 I/O91 P3 I/O75 N3 I/O77 N5 I/O68 L4 I/O67 L3 GND I/O51 J3 I/O52 J4 I/O49 J1 L M I/O128 I/O129 I/O131 FX0 FX1 FX3 GND I/O115 I/O113 I/O100 CX3 CX1 AX4 I/O90 P2 I/O74 N2 I/O80 O0 I/O83 O3 I/O69 L5 VCC I/O60 K4 I/O55 J7 I/O50 J2 M N I/O132 I/O133 I/O135 FX4 FX5 FX7 VCC VCC GND GND VCC GND GND TCK I/O56 K0 I/O53 J5 N P I/O134 I/O109 I/O110 I/O111 I/O116 I/O114 I/O101 FX6 BX5 BX6 BX7 CX4 CX2 AX5 I/O89 P1 I/O93 P5 I/O94 P6 I/O79 N7 I/O84 O4 I/O87 O7 TMS I/O57 K1 I/O54 J6 P R I/O108 I/O107 I/O104 I/O119 I/O112 I/O102 BX4 BX3 BX0 CX7 CX0 AX6 I/O99 AX3 I/O96 AX0 I/O92 P4 I/O72 N0 I/O76 N4 I/O81 O1 I/O85 O5 I/O63 K7 I/O59 K3 I/O58 K2 R T I/O106 I/O105 I/O118 I/O117 I/O103 BX2 BX1 CX6 CX5 AX7 CLK2 I/O97 AX1 I/O88 P0 CLK1 I/O95 P7 I/O73 N1 I/O78 N6 I/O82 O2 I/O86 O6 I/O62 K6 I/O61 K5 T 11 10 9 8 7 6 5 4 3 2 1 16 N/C 15 14 I/O183 I/O178 I/O170 I/O171 I/O189 I/O184 OX7 OX2 NX2 NX3 PX5 PX0 13 GND GND 12 VCC GND VCC GND VCC GND PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE 58 = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 ispMACH 4A Family I/O Cell PAL Block m4a3.512.192_256bga 388-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/256) Bottom View 388-Ball fpBGA 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A GND I/O243 I/O240 I/O241 I/O236 I/O231 I/O228 I/O226 I/O255 I/O251 I/O248 OX3 OX0 OX1 NX4 MX7 MX4 MX2 PX7 PX3 PX0 I/O0 A0 I/O5 A5 I/O6 A6 I/O27 D3 I/O30 D6 I/O17 C1 I/O22 C6 I/O8 B0 I/O10 B2 N/C GND A B N/C GND I/O245 I/O242 I/O238 I/O234 I/O232 I/O229 I/O224 I/O253 I/O249 OX5 OX2 NX6 NX2 NX0 MX5 MX0 PX5 PX1 I/O2 A2 CLK0 I/O26 D2 I/O29 D5 I/O31 D7 I/O20 C4 I/O9 B1 I/O12 B4 I/O13 B5 GND TDI B I/O7 A7 I/O25 D1 I/O16 C0 I/O18 C2 I/O23 C7 I/O11 B3 I/O15 B7 GND I/O47 F7 I/O44 F4 C I/O24 D0 VCC I/O19 C3 I/O21 C5 VCC I/O14 B6 GND I/O46 F6 I/O43 F3 I/O41 F1 D C I/O213 TDO KX5 GND I/O247 I/O244 I/O239 I/O235 I/O230 I/O227 CLK3 I/O250 I/O11 OX7 OX4 NX7 NX3 MX6 MX3 PX2 A1 D I/O210 I/O212 I/O215 GND I/O246 VCC I/O237 I/O233 VCC I/O254 VCC KX2 KX4 KX7 OX6 NX5 NX1 PX6 E I/O207 I/O209 I/O211 I/O214 JX7 KX1 KX3 KX6 I/O45 F5 I/O42 F2 I/O40 F0 I/O54 G6 E F I/O203 I/O205 I/O208 VCC JX3 JX5 KX0 VCC I/O55 G7 I/O52 G4 I/O50 G2 F G I/O200 I/O202 I/O204 I/O206 JX0 JX2 JX4 JX6 VCC VCC N/C H I/O221 I/O222 I/O223 I/O201 LX5 LX6 LX7 JX1 VCC N/C GND GND J I/O218 I/O219 I/O220 VCC LX2 LX3 LX4 N/C GND GND K I/O197 I/O198 I/O199 I/O216 IX5 IX6 IX7 LX0 I/O217 GND LX1 L I/O192 I/O194 I/O195 I/O196 IX0 IX2 IX3 IX4 I/O185 I/O187 VCC M I/O184 HX0 HX1 HX3 I/O225 I/O252 MX1 PX4 I/O3 A3 I/O4 A4 I/O28 D4 N/C VCC VCC I/O53 G5 I/O51 G3 I/O49 G1 I/O39 E7 G GND GND GND GND N/C VCC I/O48 G0 I/O38 E6 I/O37 E5 I/O36 E4 H GND GND GND GND GND GND N/C VCC I/O35 E3 I/O34 E2 I/O32 E0 J GND GND GND GND GND GND GND I/O33 E1 I/O63 H7 I/O62 H6 I/O61 H5 I/O60 H4 K I/O193 GND IX1 GND GND GND GND GND GND GND I/O58 H2 VCC I/O59 H3 I/O57 H1 I/O56 H0 L I/O186 GND HX2 GND GND GND GND GND GND GND I/O69 I5 I/O67 I3 I/O65 I1 I/O66 I2 I/O64 I0 M I/O162 GND EX2 GND GND GND GND GND GND GND I/O89 L1 I/O88 L0 I/O71 I7 I/O70 I6 I/O68 I4 N N I/O188 I/O189 I/O191 I/O190 HX4 HX5 HX7 HX6 P I/O160 I/O161 I/O163 VCC EX0 EX1 EX3 N/C GND GND GND GND GND GND GND GND N/C VCC I/O92 L4 I/O91 L3 I/O90 L2 P R I/O164 I/O165 I/O166 I/O177 EX4 EX5 EX6 GX1 VCC N/C GND GND GND GND GND GND N/C VCC I/O74 J2 I/O95 L7 I/O94 L6 I/O93 L5 R T I/O167 I/O176 I/O179 I/O181 EX7 GX0 GX3 GX5 VCC VCC N/C I/O152 I/O131 I/O122 I/O98 DX0 AX3 P2 M2 N/C VCC VCC I/O78 J6 I/O76 J4 I/O73 J1 I/O72 J0 T U I/O178 I/O180 I/O183 VCC GX2 GX4 GX7 VCC I/O80 K0 I/O77 J5 I/O75 J3 U V I/O182 GX6 I/O86 K6 I/O83 K3 I/O81 K1 I/O79 J7 V VCC I/O104 I/O111 VCC I/O119 GND N0 N7 O7 I/O87 K7 I/O84 K4 I/O82 K2 W I/O171 I/O174 GND I/O141 I/O138 I/O136 I/O147 I/O158 I/O156 CLK2 I/O132 I/O121 I/O125 I/O99 I/O101 I/O106 I/O110 I/O115 I/O118 GND FX3 FX6 BX5 BX2 BX0 CX3 DX6 DX4 AX4 P1 P5 M3 M5 N2 N6 O3 O6 TMS I/O85 K5 Y GND I/O142 I/O140 I/O151 I/O149 I/O144 I/O157 I/O154 I/O134 I/O130 I/O128 CLK1 I/O127 I/O100 I/O103 I/O108 I/O109 I/O113 I/O116 GND AA I/O175 FX7 BX6 BX4 CX7 CX5 CX0 DX5 DX2 AX6 AX2 AX0 P7 M4 M7 N4 N5 O1 O4 TCK AA I/O139 I/O137 I/O148 I/O146 I/O159 I/O155 I/O135 I/O133 I/O129 I/O120 I/O124 I/O126 I/O97 I/O102 I/O105 I/O107 I/O112 I/O114 I/O117 GND BX3 BX1 CX4 CX2 DX7 DX3 AX7 AX5 AX1 P0 P4 P6 M1 M6 N1 N3 O0 O2 O5 AB N/C I/O169 I/O172 FX1 FX4 I/O170 I/O173 GND I/O143 VCC I/O150 I/O145 VCC I/O153 I/O123 VCC W I/O168 FX0 FX2 FX5 BX7 CX6 CX1 DX1 P3 Y AB GND N/C 22 21 20 19 18 17 16 15 14 13 12 11 I/O96 M0 10 9 8 7 6 5 4 3 2 1 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 ispMACH 4A Family I/O Cell PAL Block m4a3.512.256_388bga 59 ispMACH 4A PRODUCT ORDERING INFORMATION ispMACH 4A Devices Commercial and Industrial - 3.3V and 5V Lattice programmable logic products are available with several ordering options.The order number (Valid Combination) is formed by a combination of: M4A3- 256 / 128 -7 Y FAMILY TYPE M4A3- = ispMACH 4A Family Low Voltage Advanced Feature (3.3-V VCC) M4A5- = ispMACH 4A Family Advanced Feature (5-V VCC) MACROCELL DENSITY 32=32 Macrocells192 64=64 Macrocells256 96=96 Macrocells384 128=128 Macrocells512 I/Os /32 /48 /64 /96 /128 /160 /192 /256 = = = = = = = = = = = = 48 192 Macrocells 256 Macrocells 384 Macrocells 512 Macrocells PACKAGE TYPE A = Ball Grid Array (BGA) J = Plastic Leaded Chip Carrier (PLCC) V = Thin Quad Flat Pack (TQFP) Y = Plastic Quad Flat Pack (PQFP) FA = Fine-pitch Ball Grid Array (fpBGA) CA = Chip-array Ball Grid Array (caBGA) 3.3V Commercial Combinations -5, -7, -10 JC, VC, VC48 JC, VC, VC48 VC -55, -7, -10 VC YC, VC, CAC -6, -7, -10 VC, FAC -55, -65, -7, -10 YC, AC, FAC YC -7, -10 FAC YC -65, -10, -12 AC, FAC YC -7, -10, -12 FAC FAC SPEED -5 =5.0 ns tPD -55 =5.5 ns tPD -6 =6.0 ns tPD -65 =6.5 ns tPD -7 =7.5 ns tPD -10 =10 ns tPD -12 =12 ns tPD -14 =14 ns tPD M4A3-32/32 M4A3-64/32 M4A3-64/64 M4A3-96/48 M4A3-128/64 M4A3-192/96 M4A3-256/128 M4A3-256/160 M4A3-256/192 M4A3-384/160 M4A3-384/192 M4A3-512/160 M4A3-512/192 M4A3-512/256 1. Contact Factory for 6.5ns availability 60 = 48-pin TQFP for M4A3-32/32 or M4A3-64/32 M4A5-32/32 or M4A5-64/32 OPERATING CONDITIONS C = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP 48 I/Os in 100-pin TQFP 64 I/Os in 100-pin TQFP, 100-pin PQFP, or 100-ball caBGA 96 I/Os in 144-pin TQFP or 144-ball fpBGA 128 I/Os in 208-pin PQFP, 256-ball BGA or 256-ball fpBGA 160 I/Os in 208-pin PQFP 192 I/Os in 256-ball BGA or 256-ball fpBGA 256 I/Os in 388-ball fpBGA M4A3-32/32 M4A3-64/32 M4A3-64/64 M4A3-96/48 M4A3-128/64 M4A3-192/96 M4A3-256/128 M4A3-256/1601 M4A3-256/1921 M4A3-384/160 M4A3-384/192 M4A3-512/160 M4A3-512/192 M4A3-512/256 C ispMACH 4A Family 3.3V Industrial Combinations JI, VI, VI48 JI, VI, VI48 VI -7, -10, -12 VI YI, VI, CAI VI, FAI -7, -10, -12 YI, AI, FAI YI -10, -12 FAI YI AI, FAI YI -10, -12, -14 FAI FAI M4A5-32/32 M4A5-64/32 M4A5-96/48 M4A5-128/64 M4A5-192/96 M4A5-256/128 5V Commercial Combinations -5, -7, -10, JC, VC, VC48 JC, VC, VC48 -55, -7, -10 VC YC, VC -6, -7, -10 VC -65, -7, -10 YC, AC M4A5-32/32 M4A5-64/32 M4A5-96/48 M4A5-128/64 M4A5-192/96 M4A5-256/128 5V Industrial Combinations -7, -10, -12 JI, VI, VI48 JI, VI, VI48 -7, -10, -12 VI YI, VI -7, -10, -12 VI -10, -12 YI, AI Most ispMACH devices are dual-marked with both Commercial and Industrial grades.The Industrial speed grade is slower, i.e., M4A3256/128-7YC-10YI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to confirm availability of specific valid combinations and to check on newly released combinations. Copyright © 2000 Lattice Semiconductor. All rights reserved. ispMACH 4A Family 61 62 ispMACH 4A Family