INFINEON XC87XLM

8-Bit
XC87xCLM
8-Bit Single-Chip Microcontroller
Data Sheet
V1.5 2011-03
Micr o co n t ro l l e rs
Edition 2011-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
8-Bit
XC87xCLM
8-Bit Single-Chip Microcontroller
Data Sheet
V1.5 2011-03
Micr o co n t ro l l e rs
XC87xCLM
XC87x Data Sheet
Revision History: V1.5 2011-03
Previous Versions: V1.4
Page
Subjects (major changes since last revision)
Changes from V1.4 2010-08 to V1.5 2011-03
Page 3
A new variant, SAF-XC874CM-13FVA 5V, has been added in Table 2.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
Data Sheet
V1.5, 2011-03
XC87xCLM
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
2.1
2.2
2.3
2.4
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
3.1
3.2
3.2.1
3.2.1.1
3.2.2
3.2.2.1
3.2.2.2
3.2.3
3.2.3.1
3.2.4
3.2.4.1
3.2.4.2
3.2.4.3
3.2.4.4
3.2.4.5
3.2.4.6
3.2.4.7
3.2.4.8
3.2.4.9
3.2.4.10
3.2.4.11
3.2.4.12
3.2.4.13
3.2.4.14
3.2.4.15
3.3
3.3.1
3.4
3.4.1
3.4.2
3.4.3
3.5
3.6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC87x Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Compare/Capture Unit Registers . . . . . . . . . . . . . . . . . . . . .
Timer 21 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MultiCAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Bank Pagination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . .
Data Sheet
I-1
21
21
22
24
24
26
26
28
32
33
34
34
35
36
37
40
40
43
47
49
50
54
54
55
55
57
58
60
61
61
67
69
70
72
V1.5, 2011-03
XC87xCLM
Table of Contents
3.7
3.7.1
3.7.2
3.8
3.8.1
3.8.2
3.9
3.10
3.11
3.12
3.13
3.13.1
3.13.2
3.14
3.15
3.15.1
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.22.1
3.22.2
3.23
3.23.1
3.24
Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Recommended External Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . 77
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Multiplication/Division Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
UART and UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Baud Rate Generation using Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Normal Divider Mode (8-bit Auto-reload Timer) . . . . . . . . . . . . . . . . . . . . . 91
LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . 94
Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Timer 2 and Timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Timer 2 Capture/Compare Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Controller Area Network (MultiCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ADC Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ADC Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4
4.1
4.1.1
4.1.2
4.1.3
4.2
4.2.1
4.2.2
4.2.3
4.2.3.1
4.2.4
4.3
4.3.1
4.3.2
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
I-2
108
108
108
109
110
111
111
114
115
117
118
122
122
123
V1.5, 2011-03
XC87xCLM
Table of Contents
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
5
5.1
5.2
5.3
Data Sheet
Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Data Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
124
125
126
128
129
131
Package and Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
133
133
134
136
I-3
V1.5, 2011-03
8-Bit Single-Chip Microcontroller
1
XC87xCLM
Summary of Features
The XC87x has the following features:
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 8 Kbytes of Boot ROM
– 256 bytes of RAM
– 3 Kbytes of XRAM
– 64/52 Kbytes of Flash;
(includes memory protection strategy)
• I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by
embedded voltage regulator)
(more features on next page)
Flash
52K/64K x 8
On-Chip Debug Support
Boot ROM
8K x 8
UART
SSC
Port 0
8-bit Digital I/O
Capture/Compare Unit
16-bit
Port 1
8-bit Digital I/O
Compare Unit
16-bit
Port 3
8-bit Digital I/O
Timer 2 Capture/
Compare Unit
16-bit
Port 4
8-bit Digital I/O
Port 5
8-bit Digital I/O
XC800 Core
XRAM
3K x 8
RAM
256 x 8
Timer 0
16-bit
Timer 1
16-bit
Timer 21
16-bit
MDU
CORDIC
MultiCAN
Watchdog
Timer
UART1
ADC
10-bit
8-channel
.
8-bit Analog Input
Figure 1
Data Sheet
XC87x Functional Units
1
V1.5, 2011-03
XC87xCLM
Summary of Features
Features: (continued)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Power-on reset generation
Brownout detection for core logic supply
On-chip OSC and PLL for clock generation
– Loss-of-Clock detection
Power saving modes
– slow-down mode
– idle mode
– power-down mode with wake-up capability via RXD or EXINT01)
– clock gating control to each peripheral
Programmable 16-bit Watchdog Timer (WDT)
Five ports
– Up to 40 pins as digital I/O
– 8 dedicated analog inputs used as A/D converter input
8-channel, 10-bit ADC
Four 16-bit timers
– Timer 0 and Timer 1 (T0 and T1)
– Timer 2 and Timer 21 (T2 and T21)
Multiplication/Division Unit for arithmetic operations (MDU)
CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear
functions
MultiCAN with 2 nodes, 32 message objects
Two Capture/compare units
– Capture/compare unit 6 for PWM signal generation (CCU6)
– Timer 2 Capture/compare unit for vaious digital signal generation (T2CCU)
Two full-duplex serial interfaces (UART and UART1)
Synchronous serial channel (SSC)
On-chip debug support
– 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM)
– 64 bytes of monitor RAM
Packages:
– PG-LQFP-64
– PG-VQFN-48
Temperature range TA:
– SAF (-40 to 85 °C)
– SAX (-40 to 105 °C)
– SAK (-40 to 125 °C)
1) SAK product variant does not support power-down mode.
Data Sheet
2
V1.5, 2011-03
XC87xCLM
Summary of Features
XC87x Variant Devices
The XC87x product family features devices with different configurations, program
memory sizes, package options, power supply voltage, temperature and quality profiles
(Automotive or Industrial), to offer cost-effective solutions for different application
requirements.
The list of XC87x device configurations are summarized in Table 1. 2 types of packages
are available :
•
•
PG-LQFP-64, which is denoted by XC878 and;
PG-VQFN-48, which is denoted by XC874
Table 1
Device Configuration
Device Name
CAN
Module
LIN BSL
Support
MDU
Module
XC87x
No
No
No
XC87xM
No
No
Yes
XC87xCM
Yes
No
Yes
XC87xLM
No
Yes
Yes
XC87xCLM
Yes
Yes
Yes
From these 5 different combinations of configuration, each are further made available in
many sales types, which are grouped according to device type, program memory sizes,
power supply voltage, temperature and quality profiles (Automotive or Industrial), as
shown in Table 2.
Table 2
Device Profile
Sales Type
Device Program
Type
Memory
(Kbytes)
Power TempSupply erature
(°C)
(V)
Quality
Profile
SAF-XC878-13FFI 5V
Flash
52
5.0
-40 to 85
Industrial
SAF-XC878M-13FFI 5V
Flash
52
5.0
-40 to 85
Industrial
SAF-XC878CM-13FFI 5V
Flash
52
5.0
-40 to 85
Industrial
SAF-XC878-16FFI 5V
Flash
64
5.0
-40 to 85
Industrial
SAF-XC878M-16FFI 5V
Flash
64
5.0
-40 to 85
Industrial
SAF-XC878CM-16FFI 5V
Flash
64
5.0
-40 to 85
Industrial
SAF-XC878-13FFI 3V3
Flash
52
3.3
-40 to 85
Industrial
SAF-XC878M-13FFI 3V3
Flash
52
3.3
-40 to 85
Industrial
Data Sheet
3
V1.5, 2011-03
XC87xCLM
Summary of Features
Table 2
Device Profile (cont’d)
Sales Type
Device Program
Type
Memory
(Kbytes)
Power TempSupply erature
(V)
(°C)
Quality
Profile
SAF-XC878CM-13FFI 3V3
Flash
52
3.3
-40 to 85
Industrial
SAF-XC878-16FFI 3V3
Flash
64
3.3
-40 to 85
Industrial
SAF-XC878M-16FFI 3V3
Flash
64
3.3
-40 to 85
Industrial
SAF-XC878CM-16FFI 3V3
Flash
64
3.3
-40 to 85
Industrial
SAF-XC878-13FFA 5V
Flash
52
5.0
-40 to 85
Automotive
SAF-XC878CM-13FFA 5V
Flash
52
5.0
-40 to 85
Automotive
SAF-XC878LM-13FFA 5V
Flash
52
5.0
-40 to 85
Automotive
SAF-XC878CLM-13FFA 5V
Flash
52
5.0
-40 to 85
Automotive
SAF-XC878-16FFA 5V
Flash
64
5.0
-40 to 85
Automotive
SAF-XC878CM-16FFA 5V
Flash
64
5.0
-40 to 85
Automotive
SAF-XC878LM-16FFA 5V
Flash
64
5.0
-40 to 85
Automotive
SAF-XC878CLM-16FFA 5V
Flash
64
5.0
-40 to 85
Automotive
SAX-XC878-13FFA 5V
Flash
52
5.0
-40 to 105
Automotive
SAX-XC878CM-13FFA 5V
Flash
52
5.0
-40 to 105
Automotive
SAX-XC878LM-13FFA 5V
Flash
52
5.0
-40 to 105
Automotive
SAX-XC878CLM-13FFA 5V
Flash
52
5.0
-40 to 105
Automotive
SAX-XC878-16FFA 5V
Flash
64
5.0
-40 to 105
Automotive
SAX-XC878CM-16FFA 5V
Flash
64
5.0
-40 to 105
Automotive
SAX-XC878LM-16FFA 5V
Flash
64
5.0
-40 to 105
Automotive
SAX-XC878CLM-16FFA 5V
Flash
64
5.0
-40 to 105
Automotive
SAK-XC878-13FFA 5V
Flash
52
5.0
-40 to 125
Automotive
SAK-XC878CM-13FFA 5V
Flash
52
5.0
-40 to 125
Automotive
SAK-XC878LM-13FFA 5V
Flash
52
5.0
-40 to 125
Automotive
SAK-XC878CLM-13FFA 5V
Flash
52
5.0
-40 to 125
Automotive
SAK-XC878-16FFA 5V
Flash
64
5.0
-40 to 125
Automotive
SAK-XC878CM-16FFA 5V
Flash
64
5.0
-40 to 125
Automotive
SAK-XC878LM-16FFA 5V
Flash
64
5.0
-40 to 125
Automotive
SAK-XC878CLM-16FFA 5V
Flash
64
5.0
-40 to 125
Automotive
SAF-XC874LM-16FVA 5V
Flash
64
5.0
-40 to 85
Automotive
Data Sheet
4
V1.5, 2011-03
XC87xCLM
Summary of Features
Table 2
Device Profile (cont’d)
Sales Type
Device Program
Type
Memory
(Kbytes)
Power TempSupply erature
(V)
(°C)
Quality
Profile
SAF-XC874CM-16FVA 5V
Flash
64
5.0
-40 to 85
Automotive
SAF-XC874CM-13FVA 5V
Flash
52
5.0
-40 to 85
Automotive
SAK-XC874LM-16FVA 5V
Flash
64
5.0
-40 to 125
Automotive
SAK-XC874CM-16FVA 5V
Flash
64
5.0
-40 to 125
Automotive
SAK-XC874-16FVA 5V
Flash
64
5.0
-40 to 125
Automotive
SAK-XC874LM-13FVA 5V
Flash
52
5.0
-40 to 125
Automotive
SAK-XC874CM-13FVA 5V
Flash
52
5.0
-40 to 125
Automotive
SAK-XC874-13FVA 5V
Flash
52
5.0
-40 to 125
Automotive
As this document refers to all the derivatives, some description may not apply to a
specific product. For simplicity, all versions are referred to by the term XC87x throughout
this document.
Ordering Information
The ordering code for Infineon Technologies microcontrollers provides an exact
reference to the required product. This ordering code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
The package and the type of delivery
For the available ordering codes for the XC87x, please refer to your responsible sales
representative or your local distributor.
Data Sheet
5
V1.5, 2011-03
XC87xCLM
General Device Information
2
General Device Information
Chapter 2 contains the block diagram, pin configurations, definitions and functions of the
XC87x.
2.1
Block Diagram
The block diagram of the XC87x is shown in Figure 2.
XC87x
CORDIC
UART1
MDU
SSC
WDT
CCU6
OCDS
MultiCAN
3-Kbyte XRAM
52/64-Kbyte
Flash
Clock Generator
4 MHz
On-chip OSC
PLL
Timer 2 Capture/
Compare Unit
Port 0
UART
Port 1
XTAL1
XTAL2
T0 & T1
P1.0 - P1.7
Port 3
TMS
MBC
TM
RESET
VDDP
VSSP
VDDC
VSSC
256-byte RAM
+
64-byte monitor
RAM
P3.0 - P3.7
Port 4
XC800 Core
P0.0 - P0.7
P4.0 - P4.7
Port 5
Internal Bus
8-Kbyte
Boot ROM1)
P5.0 - P5.7
ADC
Timer 21
AN0 – AN7
VAREF
VAGND
1) Includes 1-Kbyte monitor ROM
Figure 2
Data Sheet
XC87x Block Diagram
6
V1.5, 2011-03
XC87xCLM
General Device Information
2.2
Logic Symbol
The logic symbols of the XC878 and XC874 are shown in Figure 3.
VDDP
VSSP
VDDP
VSSP
Port 0 8-Bit
VAREF
VAREF
Port 1 8-Bit
VAGND
RESET
MBC
VAGND
MBC
XC878
Port 5 8-Bit
XTAL2
XTAL1
AN1,AN2,
AN4 – AN7
XTAL2
AN0 – AN7
VDDC
Port 3 7-Bit
Port 4 4-Bit
TM
XTAL1
Data Sheet
XC874
TMS
Port 4 8-Bit
TM
Figure 3
Port 1 8-Bit
RESET
Port 3 8-Bit
TMS
Port 0 8-Bit
VSSC
VDDC
VSSC
XC878 and XC874 Logic Symbol
7
V1.5, 2011-03
XC87xCLM
General Device Information
2.3
Pin Configuration
AN7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P4.3
P3.6
P3.7
P3.0
P3.1
P4.4
P4.5
P4.6
P4.7
The pin configuration of the XC878, which is based on the PG-LQFP-64, is shown in
Figure 4, while that of the XC874, which is based on the PG-VQFN-48 package, is
shown in Figure 5.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P3.2
49
32
VAREF
P3.3
50
31
VAGND
P3.4
51
30
AN6
P3.5
52
29
AN5
RESET
53
28
AN4
VSSP
54
27
AN3
V DDP
55
26
VSSP
N.C.
56
25
V DDP
TM
57
24
AN2
MBC
58
23
AN1
P4.0
59
22
AN0
P4.1
60
21
P0.1
P4.2
61
20
P5.7
P0.7
62
19
P5.6
P0.3
63
18
P0.2
P0.4
64
17
P0.0
TMS
P5.5
P5.4
P5.3
P5.0
P5.2
VDDP
9 10 11 12 13 14 15 16
P1.7
8
P1.6
7
P5.1
6
VDDC
XTAL2
4 5
VSSC
3
XTAL1
2
P0.6
Data Sheet
1
P0.5
Figure 4
XC878
XC878 Pin Configuration, PG-LQFP-64 Package (top view)
8
V1.5, 2011-03
XC87xCLM
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P4.3
P3.6
P3.0
P3.1
P3.2
P3.3
General Device Information
36 35 34 33 32 31 30 29 28 27 26 25
P3.4
37
24
AN7
P3.5
38
23
VAREF
RESET
39
22
VAGND
VSSP
40
21
AN6
VDDP
41
20
AN5
NC
42
19
AN4
TM
43
18
V SSP
MBC
44
17
VDDP
P4.0
45
16
AN2
P4.1
46
15
AN1
P4.2
47
14
P0.1
P0.7
48
13
P0. 2
P0.0
TMS
VD DC
9 10 11 12
P1.7
8
P1.6
7
VSSC
6
XTAL1
P0. 5
4 5
XTAL2
3
P0.6
2
P0. 4
Data Sheet
1
P0.3
Figure 5
XC874
XC874 Pin Configuration, PG-VQFN-48 Package (top view)
9
V1.5, 2011-03
XC87xCLM
General Device Information
2.4
Pin Definitions and Functions
The functions and default states of the XC87x external pins are provided in Table 3.
Table 3
Pin Definitions and Functions
Symbol Pin Number
(LQFP-64 /
VQFN-48)
Type Reset Function
State
P0
I/O
Port 0
Port 0 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, UART1, T2CCU,
Timer 21, MultiCAN, SSC and External Bus
Interface.
Note: External Bus Interface is not available in
XC874.
P0.0
17/12
Hi-Z
TCK_0
T12HR_1
P0.1
21/14
Hi-Z
TDI_0
T13HR_1
JTAG Clock Input
CCU6 Timer 12 Hardware Run
Input
CC61_1
Input/Output of
Capture/Compare channel 1
CLKOUT_0 Clock Output
RXDO_1
UART Transmit Data Output
RXD_1
RXDC1_0
COUT61_1
EXF2_1
P0.2
18/13
PU
CTRAP_2
TDO_0
TXD_1
TXDC1_0
Data Sheet
10
JTAG Serial Data Input
CCU6 Timer 13 Hardware Run
Input
UART Receive Data Input
MultiCAN Node 1 Receiver Input
Output of Capture/Compare
channel 1
Timer 2 External Flag Output
CCU6 Trap Input
JTAG Serial Data Output
UART Transmit Data
Output/Clock Output
MultiCAN Node 1 Transmitter
Output
V1.5, 2011-03
XC87xCLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number
(LQFP-64 /
VQFN-48)
P0.3
63/1
Type Reset Function
State
Hi-Z
SCK_1
COUT63_1
RXDO1_0
A17
P0.4
64/2
Hi-Z
MTSR_1
CC62_1
TXD1_0
A18
P0.5
1/3
Hi-Z
MRST_1
EXINT0_0
T2EX1_1
RXD1_0
COUT62_1
A19
SSC Clock Input/Output
Output of Capture/Compare
channel 3
UART1 Transmit Data Output
Address Line 17 Output
SSC Master Transmit Output/
Slave Receive Input
Input/Output of
Capture/Compare channel 2
UART1 Transmit Data
Output/Clock Output
Address Line 18 Output
SSC Master Receive Input/Slave
Transmit Output
External Interrupt Input 0
Timer 21 External Trigger Input
UART1 Receive Data Input
Output of Capture/Compare
channel 2
Address Line 19 Output
Compare Output Channel 4
External Data Write Control
Output
P0.6
2/4
PU
T2CC4_1
WR
P0.7
62/48
PU
CLKOUT_1 Clock Output
T2CC5_1
Compare Output Channel 5
RD
External Data Read Control
Output
Data Sheet
11
V1.5, 2011-03
XC87xCLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number
(LQFP-64 /
VQFN-48)
Type Reset Function
State
P1
I/O
Port 1
Port 1 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, Timer 0, Timer 1,
T2CCU, Timer 21, MultiCAN, SSC and
External Bus Interface.
Note: External Bus Interface is not available in
XC874.
P1.0
34/25
PU
RXD_0
T2EX_0
RXDC0_0
A8
UART Receive Data Input
Timer 2 External Trigger Input
MultiCAN Node 0 Receiver Input
Address Line 8 Output
P1.1
35/26
PU
EXINT3_0
T0_1
TXD_0
A9
External Interrupt Input 3
Timer 0 Input
UART Transmit Data
Output/Clock Output
MultiCAN Node 0 Transmitter
Output
Address Line 9 Output
TXDC0_0
P1.2
36/27
PU
SCK_0
A10
SSC Clock Input/Output
Address Line 10 Output
P1.3
37/28
PU
MTSR_0
SSC Master Transmit
Output/Slave Receive Input
SSC Clock Input/Output
MultiCAN Node 1 Transmitter
Output
Address Line 11 Output
SCK_2
TXDC1_3
A11
P1.4
38/29
PU
MRST_0
EXINT0_1
RXDC1_3
MTSR_2
A12
Data Sheet
12
SSC Master Receive Input/
Slave Transmit Output
External Interrupt Input 0
MultiCAN Node 1 Receiver Input
SSC Master Transmit
Output/Slave Receive Input
Address Line 12 Output
V1.5, 2011-03
XC87xCLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number
(LQFP-64 /
VQFN-48)
P1.5
39/30
Type Reset Function
State
PU
CCPOS0_1
EXINT5_0
T1_1
MRST_2
EXF2_0
RXDO_0
CCU6 Hall Input 0
External Interrupt Input 5
Timer 1 Input
SSC Master Receive Input/
Slave Transmit Output
Timer 2 External Flag Output
UART Transmit Data Output
P1.6
10/9
PU
CCPOS1_1 CCU6 Hall Input 1
T12HR_0
CCU6 Timer 12 Hardware Run
Input
EXINT6_0 External Interrupt Input 6
RXDC0_2
MultiCAN Node 0 Receiver Input
T21_1
Timer 21 Input
P1.7
11/10
PU
CCPOS2_1 CCU6 Hall Input 2
T13HR_0
CCU6 Timer 13 Hardware Run
Input
T2_1
Timer 2 Input
TXDC0_2
MultiCAN Node 0 Transmitter
Output
P1.5 and P1.6 can be used as a software chip
select output for the SSC.
Data Sheet
13
V1.5, 2011-03
XC87xCLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number
(LQFP-64 /
VQFN-48)
Type Reset Function
State
P3
I/O
Port 3
Port 3 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, UART1, T2CCU, Timer 21,
MultiCAN and External Bus Interface.
Note: External Bus Interface is not available in
XC874.
P3.0
43/33
Hi-Z
CCPOS1_2 CCU6 Hall Input 1
CC60_0
Input/Output of
Capture/Compare channel 0
RXDO1_1
UART1 Transmit Data Output
T2CC0_1/
External Interrupt Input 3/T2CCU
EXINT3_2 Capture/Compare Channel 0
P3.1
44/34
Hi-Z
CCPOS0_2 CCU6 Hall Input 0
CC61_2
Input/Output of
Capture/Compare channel 1
COUT60_0 Output of Capture/Compare
channel 0
TXD1_1
UART1 Transmit Data
Output/Clock Output
P3.2
49/35
Hi-Z
CCPOS2_2
RXDC1_1
RXD1_1
CC61_0
T2CC1_1/
EXINT4_2
P3.3
50/36
Hi-Z
COUT61_0
TXDC1_1
T2CC2_1/
EXINT5_2
A13
Data Sheet
14
CCU6 Hall Input 2
MultiCAN Node 1 Receiver Input
UART1 Receive Data Input
Input/Output of
Capture/Compare channel 1
External Interrupt Input 4/T2CCU
Capture/Compare Channel 1
Output of Capture/Compare
channel 1
MultiCAN Node 1 Transmitter
Output
External Interrupt Input 5/T2CCU
Capture/Compare Channel 2
Address Line 13 Output
V1.5, 2011-03
XC87xCLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number
(LQFP-64 /
VQFN-48)
P3.4
51/37
Type Reset Function
State
Hi-Z
CC62_0
RXDC0_1
T2EX1_0
T2CC3_1/
EXINT6_3
A14
P3.5
52/38
Hi-Z
COUT62_0
Input/Output of
Capture/Compare channel 2
MultiCAN Node 0 Receiver Input
Timer 21 External Trigger Input
External Interrupt Input 6/T2CCU
Capture/Compare Channel 3
Address Line 14 Output
A15
Output of Capture/Compare
channel 2
Timer 21 External Flag Output
MultiCAN Node 0 Transmitter
Output
Address Line 15 Output
EXF21_0
TXDC0_1
P3.6
41/32
PU
CTRAP_0
CCU6 Trap Input
P3.7
42/-
Hi-Z
EXINT4_0
COUT63_0
External Interrupt Input 4
Output of Capture/Compare
channel 3
Address Line 16 Output
A16
Data Sheet
15
V1.5, 2011-03
XC87xCLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number
(LQFP-64 /
VQFN-48)
Type Reset Function
State
P4
I/O
Port 4
Port 4 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, Timer 0, Timer 1, T2CCU, Timer 21,
MultiCAN and External Bus Interface.
Note: External Bus Interface is not available in
XC874.
P4.0
59/45
Hi-Z
RXDC0_3
CC60_1
T2CC0_0/
EXINT3_1
D0
P4.1
60/46
Hi-Z
TXDC0_3
MultiCAN Node 0 Receiver Input
Output of Capture/Compare
channel 0
External Interrupt Input 3/T2CCU
Capture/Compare Channel 0
Data Line 0 Input/Output
T2CC1_0/
EXINT4_1
D1
MultiCAN Node 0 Transmitter
Output
Output of Capture/Compare
channel 0
External Interrupt Input 4/T2CCU
Capture/Compare Channel 1
Data Line 1 Input/Output
COUT60_1
P4.2
61/47
PU
EXINT6_1
T21_0
D2
External Interrupt Input 6
Timer 21 Input
Data Line 2 Input/Output
P4.3
40/31
Hi-Z
T2EX_1
EXF21_1
COUT63_2
Timer 2 External Trigger Input
Timer 21 External Flag Output
Output of Capture/Compare
channel 3
Data Line 3 Input/Output
D3
P4.4
45/-
Data Sheet
Hi-Z
CCPOS0_3 CCU6 Hall Input 0
T0_0
Timer 0 Input
CC61_4
Output of Capture/Compare
channel 1
T2CC2_0/
External Interrupt Input 5/T2CCU
EXINT5_1 Capture/Compare Channel 2
D4
Data Line 4 Input/Output
16
V1.5, 2011-03
XC87xCLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number
(LQFP-64 /
VQFN-48)
Type Reset Function
State
P4.5
46/-
Hi-Z
CCPOS1_3 CCU6 Hall Input 1
T1_0
Timer 1 Input
COUT61_2 Output of Capture/Compare
channel 1
T2CC3_0/
External Interrupt Input 6/T2CCU
EXINT6_2 Capture/Compare Channel 3
D5
Data Line 5 Input/Output
P4.6
47/-
Hi-Z
CCPOS2_3 CCU6 Hall Input 2
T2_0
Timer 2 Input
CC62_2
Output of Capture/Compare
channel 2
T2CC4_0
Compare Output Channel 4
D6
Data Line 6 Input/Output
P4.7
48/-
Hi-Z
CTRAP_3
COUT62_2
T2CC5_0
D7
Data Sheet
17
CCU6 Trap Input
Output of Capture/Compare
channel 2
Compare Output Channel 5
Data Line 7 Input/Output
V1.5, 2011-03
XC87xCLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number
(LQFP-64 /
VQFN-48)
Type Reset Function
State
P5
I/O
Port 5
Port 5 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for UART, UART1, T2CCU, JTAG and External
Interface.
P5.0
8/-
PU
EXINT1_1
A0
External Interrupt Input 1
Address Line 0 Output
P5.1
9/-
PU
EXINT2_1
A1
External Interrupt Input 2
Address Line 1 Output
P5.2
12/-
PU
RXD_2
T2CC2_2/
EXINT5_3
A2
UART Receive Data Input
External Interrupt Input 5/T2CCU
Capture/Compare Channel 2
Address Line 2 Output
P5.3
13/-
PU
CCPOS0_0 CCU6 Hall Input 0
EXINT1_0 External Interrupt Input 1
T12HR_2
CCU6 Timer 12 Hardware Run
Input
CC61_3
Input of Capture/Compare
channel 1
TXD_2
UART Transmit Data
Output/Clock Output
T2CC5_2
Compare Output Channel 5
A3
Address Line 3 Output
P5.4
14/-
PU
CCPOS1_0 CCU6 Hall Input 1
EXINT2_0 External Interrupt Input 2
T13HR_2
CCU6 Timer 13 Hardware Run
Input
CC62_3
Input of Capture/Compare
channel 2
RXDO_2
UART Transmit Data Output
T2CC4_2
Compare Output Channel 4
A4
Address Line 4 Output
Data Sheet
18
V1.5, 2011-03
XC87xCLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number
(LQFP-64 /
VQFN-48)
Type Reset Function
State
P5.5
15/-
PU
CCPOS2_0 CCU6 Hall Input 2
CTRAP_1
CCU6 Trap Input
CC60_3
Input of Capture/Compare
channel 0
TDO_1
JTAG Serial Data Output
TXD1_2
UART1 Transmit Data Output/
Clock Output
T2CC0_2/
External Interrupt Input 3/T2CCU
EXINT3_3 Capture/Compare Channel 0
A5
Address Line 5 Output
P5.6
19/-
PU
TCK_1
RXDO1_2
T2CC1_2/
EXINT4_3
A6
JTAG Clock Input
UART1 Transmit Data Output
External Interrupt Input 4/T2CCU
Capture/Compare Channel 1
Address Line 6 Output
P5.7
20/-
PU
TDI_1
RXD1_2
T2CC3_2/
EXINT6_4
A7
JTAG Serial Data Input
UART1 Receive Data Input
External Interrupt Input 6/T2CCU
Capture/Compare Channel 3
Address Line 7 Output
Data Sheet
19
V1.5, 2011-03
XC87xCLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number
(LQFP-64 /
VQFN-48)
Type Reset Function
State
VDDP
7, 25, 55/
17, 41
–
–
I/O Port Supply (3.3 or 5.0 V)
Also used by EVR and analog modules. All
pins must be connected.
VSSP
26, 54/
18, 40
–
–
I/O Ground
All pins must be connected.
VDDC
VSSC
VAREF
VAGND
6/8
–
–
Core Supply Monitor (2.5 V)
5/7
–
–
Core Supply Ground
32/23
–
–
ADC Reference Voltage
31/22
–
–
ADC Reference Ground
AN0
22/-
I
Hi-Z
Analog Input 0
AN1
23/15
I
Hi-Z
Analog Input 1
AN2
24/16
I
Hi-Z
Analog Input 2
AN3
27/-
I
Hi-Z
Analog Input 3
AN4
28/19
I
Hi-Z
Analog Input 4
AN5
29/20
I
Hi-Z
Analog Input 5
AN6
30/21
I
Hi-Z
Analog Input 6
AN7
33/24
I
Hi-Z
Analog Input 7
XTAL1
4/6
I
Hi-Z
External Oscillator Input
(Feedback resistor required, normally NC)
XTAL2
3/5
O
Hi-Z
External Oscillator Output
(Feedback resistor required, normally NC)
TMS
16/11
I
PD
JTAG Test Mode Select
RESET 53/39
I
PU
Reset Input
MBC
58/44
I
PU
Monitor & BootStrap Loader Control
TM
57/43
–
–
Test Mode
(External pull down device required)
NC
56/42
–
–
No Connection
Data Sheet
20
V1.5, 2011-03
XC87xCLM
Functional Description
3
Functional Description
Chapter 3 provides an overview of the XC87x functional description.
3.1
Processor Architecture
The XC87x is based on a high-performance 8-bit Central Processing Unit (CPU) that is
compatible with the standard 8051 processor. While the standard 8051 processor is
designed around a 12-clock machine cycle, the XC87x CPU uses a 2-clock machine
cycle. This allows fast access to ROM or RAM memories without wait state. The
instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions.
The XC87x CPU provides a range of debugging features, including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and Special Function Registers (SFRs).
Figure 6 shows the CPU functional blocks.
Internal Data
Memory
Core SFRs
Register Interface
External Data
Memory
Program Memory
fCCLK
Memory Wait
Reset
Legacy External Interrupts (IEN0, IEN1)
External Interrupts
Non-Maskable Interrupt
Figure 6
Data Sheet
External SFRs
16-bit Registers &
Memory Interface
ALU
Opcode &
Immediate
Registers
Multiplier / Divider
Opcode Decoder
Timer 0 / Timer 1
State Machine &
Power Saving
UART
Interrupt
Controller
CPU Block Diagram
21
V1.5, 2011-03
XC87xCLM
Functional Description
3.2
Memory Organization
The XC87x CPU operates in the following address spaces:
•
•
•
8 Kbytes of Boot ROM program memory
256 bytes of internal RAM data memory
3 Kbytes of XRAM memory
(XRAM can be read/written as program memory or external data memory)
A 128-byte Special Function Register area
64/52 Kbytes of Flash program memory (Flash devices)
•
•
Figure 7 and Figure 8 illustrate the memory address spaces of the XC87x with
64Kbytes and 52Kbytes embedded Flash respectively.
Bank F
F' FFFF H
Reserved
Bank E
Bank D
Bank C
Bank B
Bank A
Reserved
Bank 9
Bank 8
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
External
Reserved
Bank 2
External
XRAM
3 KByte
Reserved
Boot ROM
8 KByte
Reserved
Bank 1
Bank 0
D-Flash
4 KByte
F' 0000H
E' FFFFH
E' 0000H
D' FFFFH
D' 0000H
C' FFFFH
C' 0000H
B' FFFFH
B' 0000H
A' FFFFH
A' 0000H
9' FFFFH
9' 0000H
8' FFFFH
8' 0000H
7' FFFFH
7' 0000H
6' FFFFH
6' 0000H
5' FFFFH
5' 0000H
4' FFFFH
4' 0000H
3' FFFFH
3' 0000H
2' FFFFH
2' FEC0H
2' FE00H
2' FC00H
2' F000H
2' E000H
2' C000H
2' 0000H
1' FFFFH
External
XRAM
3 KByte
External
Reserved
External
F' FFFF H
F' FC00H
F' F000H
F' 0000H
E' FFFFH
E' 0000H
D' FFFFH
D' 0000H
C' FFFFH
C' 0000H
B' FFFFH
B' 0000H
A' FFFFH
A' 0000H
9' FFFFH
9' 0000H
8' FFFFH
8' 0000H
7' FFFFH
7' 0000H
6' FFFFH
6' 0000H
5' FFFFH
5' 0000H
4' FFFFH
4' 0000H
3' FFFFH
3' 0000H
2' FFFFH
2' FEC0H
2' FE00H
2' FC00H
Reserved
External
Reserved
External
1' 0000H
0' FFFFH
2' F000H
2' E000H
Memory Extension
Stack Pointer
(MEXSP)
2' C000H
2' 0000H
1' FFFFH
1' 0000H
0' FFFFH
Direct
Address
Internal RAM
Special Function
Registers
FFH
Extension Stack RAM
80H
0' F000H
Reserved
7FH
P-Flash
60 KByte
Internal RAM
0' 0000H
Code Space
Indirect
Address
0' 0000H
00H
Data Space
Internal Data Space
Memory Map User Mode
Figure 7
Data Sheet
Memory Map of XC87x with 64K Flash Memory in user mode
22
V1.5, 2011-03
XC87xCLM
Functional Description
F’FFFF H
Reserved
External
1'0000H
FFFF H
FEC0H
XRAM
2 KByte
D-Flash
4 KByte
External
1'0000H
FFFF H
FEC0H
Reserved
Reserved
External
F’FFFF H
External
FE00H
FC00H
F000 H
External
XRAM
2 KByte
FE00H
FC00 H
F000 H
E000H
Reserved
Boot ROM
8 KByte
C000H
P-Flash
48 KByte /
Reserved
C000H
Reserved /
External
8000H
8000H
Memory Extension
Stack Pointer
(MEXSP)
P-Flash
32 KByte
Indirect
Address
Direct
Address
Internal RAM
Special Function
Registers
FF H
Reserved
Extension Stack RAM
80H
7FH
Internal RAM
0000H
Code Space
Figure 8
Data Sheet
0000H
00 H
Data Space
Internal Data Space
Memory Map User Mode
Memory Map of XC87x with 52K Flash Memory in user mode
23
V1.5, 2011-03
XC87xCLM
Functional Description
3.2.1
Memory Protection Strategy
The XC87x memory protection strategy includes:
•
•
•
Basic protection: The user is able to block any external access via the boot option to
any memory
Read-out protection: The user is able to protect the contents in the Flash
Flash program and erase protection
These protection strategies are enabled by programming a valid password (16-bit nonone value) via Bootstrap Loader (BSL) mode 6.
3.2.1.1
Flash Memory Protection
As long as a valid password is available, all external access to the device, including the
Flash, will be blocked.
For additional security, the Flash hardware protection can be enabled to implement a
second layer of read-out protection, as well as to enable program and erase protection.
Flash hardware protection is available only for Flash devices and comes in two modes:
•
•
Mode 0: Only the P-Flash is protected; the D-Flash is unprotected
Mode 1: Both the P-Flash and D-Flash are protected
The selection of each protection mode and the restrictions imposed are summarized in
Table 4.
Table 4
Flash Protection Modes
Flash
Protection
Without hardware
protection
With hardware protection
Hardware
Protection
Mode
-
0
Activation
Program a valid password via BSL mode 6
Selection
Bit 13 of password = 0
Bit 13 of password = 1 Bit 13 of password = 1
MSB of password = 0 MSB of password = 1
P-Flash
contents
can be read
by
Read instructions in
any program memory
Read instructions in
the P-Flash
Read instructions in
the P-Flash or DFlash
Not possible
Not possible
External
Not possible
access to PFlash
Data Sheet
1
24
V1.5, 2011-03
XC87xCLM
Functional Description
Table 4
Flash Protection Modes (cont’d)
Flash
Protection
Without hardware
protection
With hardware protection
P-Flash
program
and erase
Possible
Possible only on the
Possible only on the
condition that MSB - 1 condition that MSB - 1
of password is set to 1 of password is set to 1
D-Flash
contents
can be read
by
Read instructions in
any program memory
Read instructions in
any program memory
Read instructions in
the P-Flash or DFlash
External
Not possible
access to DFlash
Not possible
Not possible
D-Flash
program
Possible
Possible
Possible, on the
condition that MSB - 1
of password is set to 1
D-Flash
erase
Possible
Possible, on these
Possible, on the
conditions:
condition that MSB - 1
• MISC_CON.DFLASH of password is set to 1
EN bit is set to 1
prior to each erase
operation; or
• the MSB - 1 of
password is set to 1
BSL mode 6, which is used for enabling Flash protection, can also be used for disabling
Flash protection. Here, the programmed password must be provided by the user. To
disable the flash protection, a password match is required. A password match triggers
an automatic erase of the protected P-Flash and D-Flash contents, including the
programmed password. With a valid password, the Flash hardware protection is then
enabled or disabled upon next reset. For the other protection strategies, no reset is
necessary.
Although no protection scheme can be considered infallible, the XC87x memory
protection strategy provides a very high level of protection for a general purpose
microcontroller.
Note: If ROM read-out protection is enabled, only read instructions in the ROM memory
can target the ROM contents.
Data Sheet
25
V1.5, 2011-03
XC87xCLM
Functional Description
3.2.2
Special Function Register
The Special Function Registers (SFRs) occupy direct internal data memory space in the
range 80H to FFH. All registers, except the program counter, reside in the SFR area. The
SFRs include pointers and registers that provide an interface between the CPU and the
on-chip peripherals. As the 128-SFR range is less than the total number of registers
required, address extension mechanisms are required to increase the number of
addressable SFRs. The address extension mechanisms include:
•
•
Mapping
Paging
3.2.2.1
Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is
extended into two portions: the standard (non-mapped) SFR area and the mapped SFR
area. Each portion supports the same address range 80H to FFH, bringing the number of
addressable SFRs to 256. The extended address range is not directly controlled by the
CPU instruction itself, but is derived from bit RMAP in the system control register
SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR
SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed
by clearing bit RMAP. The SFR area can be selected as shown in Figure 9.
As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not
cleared automatically by hardware. Thus, before standard/mapped registers are
accessed, bit RMAP must be cleared/set, respectively, by software.
Data Sheet
26
V1.5, 2011-03
XC87xCLM
Functional Description
Standard Area (RMAP = 0)
FF H
Module 1 SFRs
SYSCON0.RMAP
Module 2 SFRs
rw
…...
Module n SFRs
80 H
SFR Data
(to/from CPU)
Mapped Area (RMAP = 1)
FF H
Module (n+1) SFRs
Module (n+2) SFRs
…...
Module m SFRs
80 H
Direct
Internal Data
Memory Address
Figure 9
Data Sheet
Address Extension by Mapping
27
V1.5, 2011-03
XC87xCLM
Functional Description
SYSCON0
System Control Register 0
7
6
5
Reset Value: 04H
4
3
2
1
0
0
IMODE
0
1
0
RMAP
r
rw
r
r
r
rw
Field
Bits
Type Description
RMAP
0
rw
Interrupt Node XINTR0 Enable
0
The access to the standard SFR area is
enabled
1
The access to the mapped SFR area is
enabled
1
2
r
Reserved
Returns 1 if read; should be written with 1.
0
[7:5],
3,1
r
Reserved
Returns 0 if read; should be written with 0.
Note: The RMAP bit should be cleared/set by ANL or ORL instructions.The rest bits of
SYSCON0 should not be modified.
3.2.2.2
Address Extension by Paging
Address extension is further performed at the module level by paging. With the address
extension by mapping, the XC87x has a 256-SFR address range. However, this is still
less than the total number of SFRs needed by the on-chip peripherals. To meet this
requirement, some peripherals have a built-in local address extension mechanism for
increasing the number of addressable SFRs. The extended address range is not directly
controlled by the CPU instruction itself, but is derived from bit field PAGE in the module
page register MOD_PAGE. Hence, the bit field PAGE must be programmed before
accessing the SFR of the target module. Each module may contain a different number
of pages and a different number of SFRs per page, depending on the specific
requirement. Besides setting the correct RMAP bit value to select the SFR area, the user
must also ensure that a valid PAGE is selected to target the desired SFR. A page inside
the extended address range can be selected as shown in Figure 10.
Data Sheet
28
V1.5, 2011-03
XC87xCLM
Functional Description
SFR Address
(from CPU)
PAGE 0
MOD_PAGE.PAGE
SFR0
rw
SFR1
…...
SFRx
PAGE 1
SFR0
SFR Data
(to/from CPU)
SFR1
…...
SFRy
…...
PAGE q
SFR0
SFR1
…...
SFRz
Module
Figure 10
Address Extension by Paging
In order to access a register located in a page different from the actual one, the current
page must be exited. This is done by reprogramming the bit field PAGE in the page
register. Only then can the desired access be performed.
If an interrupt routine is initiated between the page register access and the module
register access, and the interrupt needs to access a register located in another page, the
current page setting can be saved, the new one programmed and the old page setting
restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore
action of the current page setting. By indicating which storage bit field should be used in
parallel with the new page value, a single write operation can:
•
Save the contents of PAGE in STx before overwriting with the new value
(this is done in the beginning of the interrupt routine to save the current page setting
and program the new page number); or
Data Sheet
29
V1.5, 2011-03
XC87xCLM
Functional Description
•
Overwrite the contents of PAGE with the contents of STx, ignoring the value written
to the bit positions of PAGE
(this is done at the end of the interrupt routine to restore the previous page setting
before the interrupt occurred)
ST3
ST2
ST1
ST0
STNR
PAGE
value update
from CPU
Figure 11
Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can
perform page changes without reading and storing the previously used page information.
The use of only write operations makes the system simpler and faster. Consequently,
this mechanism significantly improves the performance of short interrupt routines.
The XC87x supports local address extension for:
•
•
•
•
Parallel Ports
Analog-to-Digital Converter (ADC)
Capture/Compare Unit 6 (CCU6)
System Control Registers
Data Sheet
30
V1.5, 2011-03
XC87xCLM
Functional Description
The page register has the following definition:
MOD_PAGE
Page Register for module MOD
7
6
Reset Value: 00H
5
4
3
2
1
OP
STNR
0
PAGE
w
w
r
rw
0
Field
Bits
Type Description
PAGE
[2:0]
rw
Page Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00
01
10
11
Data Sheet
ST0 is selected.
ST1 is selected.
ST2 is selected.
ST3 is selected.
31
V1.5, 2011-03
XC87xCLM
Functional Description
Field
Bits
Type Description
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
3.2.3
Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the
bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit
field PASS closes access to writing of all protected bits. In both cases, the value of the
bit field MODE is not changed even if PASSWD register is written with 98H or A8H. It can
only be changed when bit field PASS is written with 11000B, for example, writing D0H to
PASSWD register disables the bit protection scheme.
Note that access is opened for maximum 32 CCLKs if the “close access” password is not
written. If “open access” password is written again before the end of 32 CCLK cycles,
there will be a recount of 32 CCLK cycles. The protected bits include the N- and KDivider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the powerdown and slow-down enable bits, PD and SD.
Data Sheet
32
V1.5, 2011-03
XC87xCLM
Functional Description
3.2.3.1
Password Register
PASSWD
Password Register
7
6
Reset Value: 07H
5
4
3
2
1
0
PASS
PROTECT
_S
MODE
w
rh
rw
Field
Bits
Type Description
MODE
[1:0]
rw
Bit Protection Scheme Control Bits
00
Scheme disabled - direct access to the
protected bits is allowed.
11
Scheme enabled - the bit field PASS has to be
written with the passwords to open and close
the access to protected bits. (default)
Others:Scheme Enabled.
These two bits cannot be written directly. To change
the value between 11B and 00B, the bit field PASS
must be written with 11000B; only then, will the
MODE[1:0] be registered.
PROTECT_S
2
rh
Bit Protection Signal Status Bit
This bit shows the status of the protection.
0
Software is able to write to all protected bits.
1
Software is unable to write to any protected
bits.
PASS
[7:3]
w
Password Bits
The Bit Protection Scheme only recognizes three
patterns.
11000B Enables writing of the bit field MODE.
10011B Opens access to writing of all protected bits.
10101B Closes access to writing of all protected bits
Data Sheet
33
V1.5, 2011-03
XC87xCLM
Functional Description
3.2.4
XC87x Register Overview
The SFRs of the XC87x are organized into groups according to their functional units. The
contents (bits) of the SFRs are summarized in Chapter 3.2.4.1 to Chapter 3.2.4.15.
Note: The addresses of the bitaddressable SFRs appear in bold typeface.
3.2.4.1
CPU Registers
The CPU SFRs can be accessed in both the standard and mapped memory areas
(RMAP = 0 or 1).
Table 5
CPU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0 or 1
81H
SP
Reset: 07H
Stack Pointer Register
Bit Field
82H
DPL
Reset: 00H
Data Pointer Register Low
Bit Field
DPH
Reset: 00H
Data Pointer Register High
Bit Field
PCON
Reset: 00H
Power Control Register
Bit Field
TCON
Reset: 00H
Timer Control Register
Bit Field
TF1
TR1
TF0
Type
rwh
rw
rwh
TMOD
Reset: 00H
Timer Mode Register
Bit Field
GATE
1
T1S
rw
rw
83H
87H
88H
89H
Type
Type
Type
Type
Type
8AH
8BH
8CH
8DH
94H
95H
96H
SP
rw
DPL7
DPL6
DPL5
DPL4
DPL3
DPL2
DPL1
DPL0
rw
rw
rw
rw
rw
rw
rw
rw
DPH7
DPH6
DPH5
DPH4
DPH3
DPH2
DPH1
DPH0
rw
rw
rw
rw
rw
rw
rw
rw
SMOD
0
GF1
GF0
0
IDLE
rw
r
rw
rw
r
rw
TR0
IE1
IT1
IE0
IT0
rw
rwh
rw
rwh
rw
T1M
GATE
0
T0S
T0M
rw
rw
rw
rw
TL0
Reset: 00H
Timer 0 Register Low
Bit Field
VAL
Type
rwh
TL1
Reset: 00H
Timer 1 Register Low
Bit Field
VAL
Type
rwh
TH0
Reset: 00H
Timer 0 Register High
Bit Field
VAL
Type
rwh
TH1
Reset: 00H
Timer 1 Register High
Bit Field
VAL
Type
rwh
MEX1
Reset: 00H
Memory Extension Register 1
Bit Field
MEX2
Reset: 00H
Memory Extension Register 2
Bit Field
MEX3
Reset: 00H
Memory Extension Register 3
Bit Field
Type
Type
Type
Data Sheet
CB
NB
r
rw
MCM
MCB
IB
rw
rw
rw
MCB1
9
0
MXB1
9
MXM
MXB
rw
r
rw
rw
rw
34
V1.5, 2011-03
XC87xCLM
Functional Description
Table 5
CPU Register Overview (cont’d)
Addr Register Name
Bit
7
97H
MEXSP
Reset: 7FH
Memory Extension Stack
Pointer Register
Bit Field
0
MXSP
Type
r
rwh
SCON
Reset: 00H
Serial Channel Control Register
Bit Field
SBUF
Reset: 00H
Serial Data Buffer Register
Bit Field
VAL
Type
rwh
EO
Reset: 00H
Extended Operation Register
Bit Field
0
TRAP_
EN
0
DPSE
L0
Type
r
rw
r
rw
98H
99H
A2H
A8H
B8H
B9H
D0H
E0H
E8H
F0H
Type
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
rw
rw
rw
rw
rw
rwh
rwh
rwh
IEN0
Reset: 00H
Interrupt Enable Register 0
Bit Field
EA
0
ET2
ES
ET1
EX1
ET0
EX0
Type
rw
r
rw
rw
rw
rw
rw
rw
IP
Reset: 00H
Interrupt Priority Register
Bit Field
0
PT2
PS
PT1
PX1
PT0
PX0
Type
r
rw
rw
rw
rw
rw
rw
IPH
Reset: 00H
Interrupt Priority High Register
Bit Field
0
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Type
r
rw
rw
rw
rw
rw
rw
PSW
Reset: 00H
Program Status Word Register
Bit Field
CY
AC
F0
RS1
RS0
OV
F1
P
Type
rwh
rwh
rw
rw
rw
rwh
rw
rh
ACC
Reset: 00H
Accumulator Register
Bit Field
ACC7
ACC6
ACC5
ACC4
ACC3
ACC2
ACC1
ACC0
rw
rw
rw
rw
rw
rw
rw
rw
IEN1
Reset: 00H
Interrupt Enable Register 1
Bit Field
ECCIP
3
ECCIP
2
ECCIP
1
ECCIP
0
EXM
EX2
ESSC
EADC
Type
rw
rw
rw
rw
rw
rw
rw
rw
Bit Field
B7
B6
B5
B4
B3
B2
B1
B0
Type
rw
rw
rw
rw
rw
rw
rw
rw
PCCIP
3
PCCIP
2
PCCIP
1
PCCIP
0
PXM
PX2
PSSC
PADC
B
B Register
Reset: 00H
Type
F8H
IP1
Reset: 00H
Interrupt Priority 1 Register
F9H
IPH1
Reset: 00H Bit Field
Interrupt Priority 1 High Register
Bit Field
Type
Type
3.2.4.2
rw
rw
rw
rw
rw
rw
rw
rw
PCCIP
3H
PCCIP
2H
PCCIP
1H
PCCIP
0H
PXMH
PX2H
PSSC
H
PADC
H
rw
rw
rw
rw
rw
rw
rw
rw
2
1
0
MDU Registers
The MDU SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 6
MDU Register Overview
Addr Register Name
Bit
7
6
5
4
3
RMAP = 1
B0H
MDUSTAT
Reset: 00H
MDU Status Register
Data Sheet
Bit Field
0
BSY
IERR
IRDY
Type
r
rh
rwh
rwh
35
V1.5, 2011-03
XC87xCLM
Functional Description
Table 6
MDU Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
B1H
Bit Field
IE
IR
RSEL
STAR
T
OPCODE
Type
rw
rw
rw
rwh
rw
MDUCON
Reset: 00H
MDU Control Register
MD0
Reset: 00H
MDU Operand Register 0
Bit Field
B2H
MR0
Reset: 00H
MDU Result Register 0
Bit Field
B3H
MD1
Reset: 00H
MDU Operand Register 1
Bit Field
MR1
Reset: 00H
MDU Result Register 1
Bit Field
MD2
Reset: 00H
MDU Operand Register 2
Bit Field
MR2
Reset: 00H
MDU Result Register 2
Bit Field
MD3
Reset: 00H
MDU Operand Register 3
Bit Field
MR3
Reset: 00H
MDU Result Register 3
Bit Field
MD4
Reset: 00H
MDU Operand Register 4
Bit Field
MR4
Reset: 00H
MDU Result Register 4
Bit Field
MD5
Reset: 00H
MDU Operand Register 5
Bit Field
MR5
Reset: 00H
MDU Result Register 5
Bit Field
B2H
B3H
B4H
B4H
B5H
B5H
B6H
B6H
B7H
B7H
3.2.4.3
3
2
1
0
DATA
Type
rw
DATA
Type
rh
DATA
Type
rw
DATA
Type
rh
DATA
Type
rw
DATA
Type
rh
DATA
Type
rw
DATA
Type
rh
DATA
Type
rw
DATA
Type
rh
DATA
Type
rw
DATA
Type
rh
CORDIC Registers
The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 7
CORDIC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
9AH
9BH
CD_CORDXL
Reset: 00H
CORDIC X Data Low Byte
Bit Field
CD_CORDXH
Reset: 00H
CORDIC X Data High Byte
Bit Field
Data Sheet
DATAL
Type
rw
DATAH
Type
rw
36
V1.5, 2011-03
XC87xCLM
Functional Description
Table 7
CORDIC Register Overview (cont’d)
Addr Register Name
Bit
9CH
CD_CORDYL
Reset: 00H
CORDIC Y Data Low Byte
Bit Field
CD_CORDYH
Reset: 00H
CORDIC Y Data High Byte
Bit Field
CD_CORDZL
Reset: 00H
CORDIC Z Data Low Byte
Bit Field
CD_CORDZH
Reset: 00H
CORDIC Z Data High Byte
Bit Field
CD_STATC
Reset: 00H
CORDIC Status and Data
Control Register
Bit Field
CD_CON
Reset: 00H
CORDIC Control Register
Bit Field
9DH
9EH
9FH
A0H
A1H
7
5
4
2
1
0
rw
DATAH
Type
rw
DATAL
Type
rw
DATAH
Type
Type
3
DATAL
Type
rw
KEEP
Z
KEEP
Y
KEEP
X
DMAP
INT_E
N
EOC
ERRO
R
BSY
rw
rw
rw
rw
rw
rwh
rh
rh
MPS
X_USI
GN
ST_M
ODE
ROTV
EC
MODE
ST
rw
rw
rw
rw
rw
rwh
Type
3.2.4.4
6
System Control Registers
The system control SFRs can be accessed in the mapped memory area (RMAP = 0).
Table 8
SCU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0 or 1
8FH
SYSCON0
Reset: 04H
System Control Register 0
Bit Field
0
IMOD
E
0
1
0
RMAP
Type
r
rw
r
r
r
rw
RMAP = 0
BFH
SCU_PAGE
Page Register
Reset: 00H
Bit Field
Type
OP
STNR
0
PAGE
w
w
r
rwh
RMAP = 0, PAGE 0
B3H
B4H
B5H
B6H
MODPISEL
Reset: 00H
Peripheral Input Select Register
IRCON0
Reset: 00H
Interrupt Request Register 0
IRCON1
Reset: 00H
Interrupt Request Register 1
IRCON2
Reset: 00H
Interrupt Request Register 2
Data Sheet
Bit Field
0
URRIS
H
JTAGT
DIS
JTAGT
CKS
EXINT
2IS
EXINT
1IS
EXINT
0IS
URRIS
Type
r
rw
rw
rw
rw
rw
rw
rw
Bit Field
0
EXINT
6
EXINT
5
EXINT
4
EXINT
EXINT
2
EXINT
1
EXINT
0
3
Type
r
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Bit Field
0
CANS
RC2
CANS
RC1
ADCS
R1
ADCS
R0
RIR
TIR
EIR
Type
r
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Bit Field
0
CANS
RC3
0
CANS
RC0
Type
r
rwh
r
rwh
37
V1.5, 2011-03
XC87xCLM
Functional Description
Table 8
SCU Register Overview (cont’d)
Addr Register Name
Bit
B7H
EXICON0
Reset: F0H
External Interrupt Control
Register 0
Bit Field
EXINT3
EXINT2
EXINT1
EXINT0
Type
rw
rw
rw
rw
EXICON1
Reset: 3FH
External Interrupt Control
Register 1
Bit Field
0
EXINT6
EXINT5
EXINT4
Type
r
rw
rw
rw
NMICON
Reset: 00H
NMI Control Register
Bit Field
0
NMI
ECC
NMI
VDDP
0
NMI
OCDS
NMI
FLASH
NMI
PLL
NMI
WDT
Type
r
rw
rw
r
rw
rw
rw
rw
Bit Field
0
FNMI
ECC
FNMI
VDDP
0
FNMI
OCDS
FNMI
FLASH
FNMI
PLL
FNMI
WDT
Type
r
rwh
rwh
r
rwh
rwh
rwh
rwh
BGSEL
NDOV
EN
BRDIS
BRPRE
R
rw
rw
rw
rw
rw
BAH
BBH
BCH
BDH
NMISR
Reset: 00H
NMI Status Register
BCON
Reset: 20H
Baud Rate Control Register
7
6
Bit Field
Type
BEH
E9H
EAH
EBH
BG
Reset: 00H
Baud Rate Timer/Reload
Register
Bit Field
FDCON
Reset: 00H
Fractional Divider Control
Register
Bit Field
FDSTEP
Reset: 00H
Fractional Divider Reload
Register
Bit Field
FDRES
Reset: 00H
Fractional Divider Result
Register
Bit Field
5
4
3
1
0
BR_VALUE
Type
Type
2
rwh
BGS
SYNE
N
ERRS
YN
EOFS
YN
BRK
NDOV
FDM
FDEN
rw
rw
rwh
rwh
rwh
rwh
rw
rw
STEP
Type
rw
RESULT
Type
rh
RMAP = 0, PAGE 1
B3H
ID
Identity Register
Reset: 49H
Bit Field
B4H
PMCON0
Reset: 80H
Power Mode Control Register 0
Bit Field
B5H
B6H
PMCON1
Reset: 00H
Power Mode Control Register 1
OSC_CON
Reset: XXH
OSC Control Register
Type
PLL_CON
Reset: 18H
PLL Control Register
r
CMCON
Reset: 10H
Clock Control Register
WKRS
WK
SEL
SD
PD
WS
Type
rh
rwh
rwh
rw
rw
rwh
rw
Bit Field
0
CDC_
DIS
CAN_
DIS
MDU_
DIS
T2CC
U_DIS
CCU_
DIS
SSC_
DIS
ADC_
DIS
Type
r
rw
rw
rw
rw
rw
rw
rw
PLLRD
RES
PLLBY
P
PLLPD
0
XPD
OSC
SS
EORD
RES
EXTO
SCR
rwh
rwh
rw
r
rw
rwh
rwh
rh
NDIV
PLLR
PLL_L
OCK
rw
rh
rh
Bit Field
Bit Field
Bit Field
Type
Data Sheet
r
WDT
RST
Type
BAH
VERID
VDDP
WARN
Type
B7H
PRODID
KDIV
0
FCCF
G
CLKREL
rw
r
rw
rw
38
V1.5, 2011-03
XC87xCLM
Functional Description
Table 8
SCU Register Overview (cont’d)
Addr Register Name
Bit
BBH
Bit Field
PASSWD
Reset: 07H
Password Register
7
6
Type
BEH
E9H
COCON
Reset: 00H
Clock Output Control Register
Bit Field
MISC_CON
Reset: 00H
Miscellaneous Control Register
Bit Field
EAH
EBH
PLL_CON1
Reset: 20H
PLL Control Register 1
Bit Field
CR_MISC Reset: 00H or 01H
Reset Status Register
Bit Field
3
2
1
0
PASS
PROT
ECT_S
MODE
w
rh
rw
TLEN
0
COREL
rw
rw
r
rw
ADCE
TR0_
MUX
ADCE
TR1_
MUX
0
DFLAS
HEN
rw
rw
r
rwh
Type
Type
4
COUTS
Type
Type
5
NDIV
PDIV
rw
rw
CCCF
G
MDUC
CFG
CCUC
CFG
T2CCF
G
0
HDRS
T
rw
rw
rw
rw
r
rwh
RMAP = 0, PAGE 3
B3H
B4H
B5H
B6H
B7H
BAH
BBH
BDH
BEH
EAH
XADDRH
Reset: F0H
On-chip XRAM Address Higher
Order
Bit Field
IRCON3
Reset: 00H
Interrupt Request Register 3
Bit Field
0
CANS
RC5
CCU6
SR1
0
CANS
RC4
CCU6
SR0
Type
r
rwh
rwh
r
rwh
rwh
Bit Field
0
CANS
RC7
CCU6
SR3
0
CANS
RC6
CCU6
SR2
Type
r
rwh
rwh
r
rwh
rwh
IRCON4
Reset: 00H
Interrupt Request Register 4
ADDRH
Type
rw
MODIEN
Reset: 07H
Peripheral Interrupt Enable
Register
Bit Field
0
CM5E
N
CM4E
N
RIREN
TIREN
EIREN
Type
r
rw
rw
rw
rw
rw
MODPISEL1
Reset: 00H
Peripheral Input Select Register
1
Bit Field
MODPISEL2
Reset: 00H
Peripheral Input Select Register
2
PMCON2
Reset: 00H
Power Mode Control Register 2
MODSUSP
Reset: 01H
Module Suspend Control
Register
EXINT6IS
UR1RIS
T21EX
IS
0
Type
rw
rw
rw
r
Bit Field
0
T2EXI
S
T21IS
T2IS
T1IS
T0IS
Type
r
rw
rw
rw
rw
rw
Bit Field
0
UART
1_DIS
T21_D
IS
Type
r
rw
rw
Bit Field
0
CCTS
USP
T21SU
SP
T2SUS
P
T13SU
SP
T12SU
SP
WDTS
USP
Type
r
rw
rw
rw
rw
rw
rw
MODPISEL3
Reset: 00H
Peripheral Input Select Register
3
Bit Field
0
CIS
SIS
MIS
Type
r
rw
rw
rw
MODPISEL4
Reset: 00H
Peripheral Input Select Register
4
Bit Field
0
EXINT5IS
EXINT4IS
EXINT3IS
Type
r
rw
rw
rw
Data Sheet
39
V1.5, 2011-03
XC87xCLM
Functional Description
3.2.4.5
WDT Registers
The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 9
WDT Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 1
BBH
BCH
BDH
BEH
BFH
WDTCON
Reset: 00H
Watchdog Timer Control
Register
Bit Field
0
WINB
EN
WDTP
R
0
WDTE
N
WDTR
S
WDTI
N
Type
r
rw
rh
r
rw
rwh
rw
WDTREL
Reset: 00H
Watchdog Timer Reload
Register
Bit Field
WDTWINB
Reset: 00H
Watchdog Window-Boundary
Count Register
Bit Field
WDTL
Reset: 00H
Watchdog Timer Register Low
Bit Field
WDTH
Reset: 00H
Watchdog Timer Register High
Bit Field
1
0
3.2.4.6
WDTREL
Type
rw
WDTWINB
Type
rw
WDT
Type
rh
WDT
Type
rh
Port Registers
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 10
Port Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
RMAP = 0
B2H
PORT_PAGE
Page Register
Reset: 00H
Bit Field
Type
OP
STNR
0
PAGE
w
w
r
rwh
RMAP = 0, PAGE 0
80H
86H
90H
91H
92H
93H
P0_DATA
Reset: 00H
P0 Data Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
P0_DIR
Reset: 00H
P0 Direction Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P1_DATA
Reset: 00H
P1 Data Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
P1_DIR
Reset: 00H
P1 Direction Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P5_DATA
Reset: 00H
P5 Data Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
P5_DIR
Reset: 00H
P5 Direction Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
Data Sheet
40
V1.5, 2011-03
XC87xCLM
Functional Description
Table 10
Port Register Overview (cont’d)
Addr Register Name
Bit
B0H
P3_DATA
Reset: 00H
P3 Data Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
P3_DIR
Reset: 00H
P3 Direction Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P4_DATA
Reset: 00H
P4 Data Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
P4_DIR
Reset: 00H
P4 Direction Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P0_PUDSEL
Reset: FFH
P0 Pull-Up/Pull-Down Select
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P0_PUDEN
Reset: C4H
P0 Pull-Up/Pull-Down Enable
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P1_PUDSEL
Reset: FFH
P1 Pull-Up/Pull-Down Select
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P1_PUDEN
Reset: FFH
P1 Pull-Up/Pull-Down Enable
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P5_PUDSEL
Reset: FFH
P5 Pull-Up/Pull-Down Select
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P5_PUDEN
Reset: FFH
P5 Pull-Up/Pull-Down Enable
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P3_PUDSEL
Reset: BFH
P3 Pull-Up/Pull-Down Select
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P3_PUDEN
Reset: 40H
P3 Pull-Up/Pull-Down Enable
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P4_PUDSEL
Reset: FFH
P4 Pull-Up/Pull-Down Select
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P4_PUDEN
Reset: 04H
P4 Pull-Up/Pull-Down Enable
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P0_ALTSEL0
Reset: 00H
P0 Alternate Select 0 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P0_ALTSEL1
Reset: 00H
P0 Alternate Select 1 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P1_ALTSEL0
Reset: 00H
P1 Alternate Select 0 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
B1H
C8H
C9H
7
6
5
4
3
2
1
0
RMAP = 0, PAGE 1
80H
86H
90H
91H
92H
93H
B0H
B1H
C8H
C9H
RMAP = 0, PAGE 2
80H
86H
90H
Data Sheet
41
V1.5, 2011-03
XC87xCLM
Functional Description
Table 10
Port Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
91H
P1_ALTSEL1
Reset: 00H
P1 Alternate Select 1 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P5_ALTSEL0
Reset: 00H
P5 Alternate Select 0 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P5_ALTSEL1
Reset: 00H
P5 Alternate Select 1 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P3_ALTSEL0
Reset: 00H
P3 Alternate Select 0 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P3_ALTSEL1
Reset: 00H
P3 Alternate Select 1 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P4_ALTSEL0
Reset: 00H
P4 Alternate Select 0 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P4_ALTSEL1
Reset: 00H
P4 Alternate Select 1 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P0_OD
Reset: 00H
P0 Open Drain Control Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P0_DS
Reset: FFH
P0 Drive Strength Control
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P1_OD
Reset: 00H
P1 Open Drain Control Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P1_DS
Reset: FFH
P1 Drive Strength Control
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P5_OD
Reset: 00H
P5 Open Drain Control Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P5_DS
Reset: FFH
P5 Drive Strength Control
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P3_OD
Reset: 00H
P3 Open Drain Control Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P3_DS
Reset: FFH
P3 Drive Strength Control
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P4_OD
Reset: 00H
P4 Open Drain Control Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P4_DS
Reset: FFH
P4 Drive Strength Control
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
92H
93H
B0H
B1H
C8H
C9H
RMAP = 0, PAGE 3
80H
86H
90H
91H
92H
93H
B0H
B1H
C8H
C9H
Data Sheet
42
V1.5, 2011-03
XC87xCLM
Functional Description
3.2.4.7
ADC Registers
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 11
ADC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
D1H
ADC_PAGE
Page Register
Reset: 00H
Bit Field
OP
STNR
0
PAGE
w
w
r
rw
Type
RMAP = 0, PAGE 0
CAH
CBH
CCH
ADC_GLOBCTR Reset: 30H
Global Control Register
Bit Field
ADC_GLOBSTR Reset: 00H
Global Status Register
Bit Field
0
CHNR
0
SAMP
LE
BUSY
Type
r
rh
r
rh
rh
ADC_PRAR
Reset: 00H
Priority and Arbitration Register
Type
Bit Field
Type
CDH
CEH
CFH
ADC_LCBR
Reset: B7H
Limit Check Boundary Register
ANON
DW
CTC
0
rw
rw
rw
r
ASEN
1
ASEN
0
0
ARBM
CSM1
PRIO1
CSM0
PRIO0
rw
rw
r
rw
rw
rw
rw
rw
Bit Field
BOUND1
BOUND0
rw
rw
Type
ADC_INPCR0
Reset: 00H
Input Class 0 Register
Bit Field
ADC_ETRCR
Reset: 00H
External Trigger Control
Register
Bit Field
STC
Type
rw
SYNE
N1
SYNE
N0
ETRSEL1
ETRSEL0
Type
rw
rw
rw
rw
ADC_CHCTR0
Reset: 00H
Channel Control Register 0
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
ADC_CHCTR1
Reset: 00H
Channel Control Register 1
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
ADC_CHCTR2
Reset: 00H
Channel Control Register 2
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
ADC_CHCTR3
Reset: 00H
Channel Control Register 3
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
ADC_CHCTR4
Reset: 00H
Channel Control Register 4
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
ADC_CHCTR5
Reset: 00H
Channel Control Register 5
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
ADC_CHCTR6
Reset: 00H
Channel Control Register 6
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
ADC_CHCTR7
Reset: 00H
Channel Control Register 7
Bit Field
0
LCC
0
RESRSEL
Type
r
rw
r
rw
RMAP = 0, PAGE 1
CAH
CBH
CCH
CDH
CEH
CFH
D2H
D3H
Data Sheet
43
V1.5, 2011-03
XC87xCLM
Functional Description
Table 11
ADC Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
RESULT
0
VF
DRC
CHNR
rh
r
rh
rh
rh
0
RMAP = 0, PAGE 2
ADC_RESR0L
Reset: 00H
Result Register 0 Low
Bit Field
ADC_RESR0H
Reset: 00H
Result Register 0 High
Bit Field
ADC_RESR1L
Reset: 00H
Result Register 1 Low
Bit Field
ADC_RESR1H
Reset: 00H
Result Register 1 High
Bit Field
ADC_RESR2L
Reset: 00H
Result Register 2 Low
Bit Field
CFH
ADC_RESR2H
Reset: 00H
Result Register 2 High
Bit Field
D2H
ADC_RESR3L
Reset: 00H
Result Register 3 Low
Bit Field
ADC_RESR3H
Reset: 00H
Result Register 3 High
Bit Field
CAH
CBH
CCH
CDH
CEH
D3H
Type
RESULT
Type
rh
RESULT
0
VF
DRC
CHNR
rh
r
rh
rh
rh
Type
RESULT
Type
rh
RESULT
0
VF
DRC
CHNR
rh
r
rh
rh
rh
Type
RESULT
Type
rh
RESULT
0
VF
DRC
CHNR
rh
r
rh
rh
rh
Type
RESULT
Type
rh
RMAP = 0, PAGE 3
ADC_RESRA0L Reset: 00H
Result Register 0, View A Low
Bit Field
ADC_RESRA0H Reset: 00H
Result Register 0, View A High
Bit Field
CCH
ADC_RESRA1L Reset: 00H
Result Register 1, View A Low
Bit Field
CDH
ADC_RESRA1H Reset: 00H
Result Register 1, View A High
Bit Field
ADC_RESRA2L Reset: 00H
Result Register 2, View A Low
Bit Field
ADC_RESRA2H Reset: 00H
Result Register 2, View A High
Bit Field
ADC_RESRA3L Reset: 00H
Result Register 3, View A Low
Bit Field
ADC_RESRA3H Reset: 00H
Result Register 3, View A High
Bit Field
CAH
CBH
CEH
CFH
D2H
D3H
RESULT
VF
DRC
CHNR
rh
rh
rh
rh
Type
RESULT
Type
rh
RESULT
VF
DRC
CHNR
rh
rh
rh
rh
Type
RESULT
Type
rh
RESULT
VF
DRC
CHNR
rh
rh
rh
rh
Type
RESULT
Type
rh
RESULT
VF
DRC
CHNR
rh
rh
rh
rh
Type
RESULT
Type
rh
RMAP = 0, PAGE 4
CAH
ADC_RCR0
Reset: 00H
Result Control Register 0
Bit Field
Type
Data Sheet
VFCT
R
WFR
0
IEN
0
DRCT
R
rw
rw
r
rw
r
rw
44
V1.5, 2011-03
XC87xCLM
Functional Description
Table 11
ADC Register Overview (cont’d)
Addr Register Name
Bit
CBH
Bit Field
ADC_RCR1
Reset: 00H
Result Control Register 1
Type
CCH
ADC_RCR2
Reset: 00H
Result Control Register 2
Bit Field
Type
CDH
ADC_RCR3
Reset: 00H
Result Control Register 3
Bit Field
Type
CEH
ADC_VFCR
Reset: 00H
Valid Flag Clear Register
7
6
5
4
3
2
1
0
VFCT
R
WFR
0
IEN
0
DRCT
R
rw
rw
r
rw
r
rw
VFCT
R
WFR
0
IEN
0
DRCT
R
rw
rw
r
rw
r
rw
VFCT
R
WFR
0
IEN
0
DRCT
R
rw
rw
r
rw
r
rw
Bit Field
0
VFC3
VFC2
VFC1
VFC0
Type
r
w
w
w
w
RMAP = 0, PAGE 5
CAH
ADC_CHINFR
Reset: 00H
Channel Interrupt Flag Register
Bit Field
Type
CBH
ADC_CHINCR
Reset: 00H
Channel Interrupt Clear Register
Bit Field
Type
CCH
ADC_CHINSR
Reset: 00H
Channel Interrupt Set Register
Bit Field
Type
CDH
CEH
ADC_CHINPR
Reset: 00H
Channel Interrupt Node Pointer
Register
Bit Field
ADC_EVINFR
Reset: 00H
Event Interrupt Flag Register
Bit Field
Type
Type
CFH
D2H
ADC_EVINCR
Reset: 00H
Event Interrupt Clear Flag
Register
Bit Field
Type
ADC_EVINSR
Reset: 00H
Bit Field
Event Interrupt Set Flag Register
Type
D3H
ADC_EVINPR
Reset: 00H
Event Interrupt Node Pointer
Register
Bit Field
Type
CHINF
7
CHINF
6
CHINF
5
CHINF
4
CHINF
3
CHINF
2
CHINF
1
CHINF
0
rh
rh
rh
rh
rh
rh
rh
rh
CHINC
7
CHINC
6
CHINC
5
CHINC
4
CHINC
3
CHINC
2
CHINC
1
CHINC
0
w
w
w
w
w
w
w
w
CHINS
7
CHINS
6
CHINS
5
CHINS
4
CHINS
3
CHINS
2
CHINS
1
CHINS
0
w
w
w
w
w
w
w
w
CHINP
7
CHINP
6
CHINP
5
CHINP
4
CHINP
3
CHINP
2
CHINP
1
CHINP
0
rw
rw
rw
rw
rw
rw
rw
rw
EVINF
7
EVINF
6
EVINF
5
EVINF
4
0
EVINF
1
EVINF
0
rh
rh
rh
rh
r
rh
rh
EVINC
7
EVINC
6
EVINC
5
EVINC
4
0
EVINC
1
EVINC
0
w
w
w
w
r
w
w
EVINS
7
EVINS
6
EVINS
5
EVINS
4
0
EVINS
1
EVINS
0
w
w
w
w
r
w
w
EVINP
7
EVINP
6
EVINP
5
EVINP
4
0
EVINP
1
EVINP
0
rw
rw
rw
rw
r
rw
rw
RMAP = 0, PAGE 6
CAH
CBH
ADC_CRCR1
Reset: 00H
Conversion Request Control
Register 1
Bit Field
CH7
CH6
CH5
CH4
0
Type
rwh
rwh
rwh
rwh
r
ADC_CRPR1
Reset: 00H
Conversion Request Pending
Register 1
Bit Field
CHP7
CHP6
CHP5
CHP4
0
rwh
rwh
rwh
rwh
r
Data Sheet
Type
45
V1.5, 2011-03
XC87xCLM
Functional Description
Table 11
ADC Register Overview (cont’d)
Addr Register Name
Bit
CCH
ADC_CRMR1
Reset: 00H
Conversion Request Mode
Register 1
Bit Field
ADC_QMR0
Reset: 00H
Queue Mode Register 0
Bit Field
CDH
Type
Type
CEH
ADC_QSR0
Reset: 20H
Queue Status Register 0
Bit Field
Type
CFH
D2H
D2H
ADC_Q0R0
Reset: 00H
Queue 0 Register 0
Bit Field
ADC_QBUR0
Reset: 00H
Queue Backup Register 0
Bit Field
ADC_QINR0
Reset: 00H
Queue Input Register 0
Bit Field
Data Sheet
Type
Type
Type
7
6
5
4
3
2
1
0
Rsv
LDEV
CLRP
ND
SCAN
ENSI
ENTR
0
ENGT
r
w
w
rw
rw
rw
r
rw
CEV
TREV
FLUS
H
CLRV
0
ENTR
0
ENGT
w
w
w
w
r
rw
r
rw
Rsv
0
EMPT
Y
EV
0
FILL
r
r
rh
rh
r
rh
EXTR
ENSI
RF
V
0
REQCHNR
rh
rh
rh
rh
r
rh
EXTR
ENSI
RF
V
0
REQCHNR
rh
rh
rh
rh
r
rh
EXTR
ENSI
RF
0
REQCHNR
w
w
w
r
w
46
V1.5, 2011-03
XC87xCLM
Functional Description
3.2.4.8
Timer 2 Compare/Capture Unit Registers
The Timer 2 Compare/Capture Unit SFRs can be accessed in the standard memory area
(RMAP = 0).
Table 12
T2CCU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
C7H
T2_PAGE
Page Register
Reset: 00H
Bit Field
Type
OP
STNR
0
PAGE
w
w
r
rwh
0
EXEN
2
RMAP = 0, PAGE 0
C0H
T2_T2CON
Reset: 00H
Timer 2 Control Register
Bit Field
C1H
T2_T2MOD
Reset: 00H
Timer 2 Mode Register
Bit Field
Type
Type
C2H
C3H
C4H
C5H
C6H
TF2
EXF2
r
rw
TR2
C/T2
rwh
rw
CP/
RL2
rwh
rwh
T2RE
GS
T2RH
EN
EDGE
SEL
PREN
T2PRE
DCEN
rw
rw
rw
rw
rw
rw
rw
T2_RC2L
Reset: 00H
Timer 2 Reload/Capture
Register Low
Bit Field
RC2
Type
rwh
T2_RC2H
Reset: 00H
Timer 2 Reload/Capture
Register High
Bit Field
RC2
Type
rwh
T2_T2L
Reset: 00H
Timer 2 Register Low
Bit Field
T2_T2H
Reset: 00H
Timer 2 Register High
Bit Field
T2_T2CON1
Reset: 03H
Timer 2 Control Register 1
Bit Field
0
TF2EN
EXF2E
N
Type
r
rw
rw
THL2
Type
rwh
THL2
Type
rwh
RMAP = 0, PAGE 1
C0H
C1H
C2H
C3H
C4H
T2CCU_CCEN
Reset: 00H
T2CCU Capture/Compare
Enable Register
Bit Field
T2CCU_CCTBSELReset: 00H
T2CCU Capture/Compare Time
Base Select Register
Bit Field
CCM3
CCM2
CCM1
CCM0
rw
rw
rw
rw
Type
Type
CASC
CCTT
OV
CCTB
5
CCTB
4
CCTB
3
CCTB
2
CCTB
1
CCTB
0
rw
rwh
rw
rw
rw
rw
rw
rw
T2CCU_CCTRELLReset: 00H
T2CCU Capture/Compare
Timer Reload Register Low
Bit Field
T2CCU_CCTRELHReset: 00H
T2CCU Capture/Compare
Timer Reload Register High
Bit Field
T2CCU_CCTL
Reset: 00H
T2CCU Capture/Compare
Timer Register Low
Bit Field
CCT
Type
rwh
Data Sheet
CCTREL
Type
rw
CCTREL
Type
rw
47
V1.5, 2011-03
XC87xCLM
Functional Description
Table 12
T2CCU Register Overview (cont’d)
Addr Register Name
Bit
C5H
T2CCU_CCTH
Reset: 00H
T2CCU Capture/Compare
Timer Register High
Bit Field
CCT
Type
rwh
T2CCU_CCTCON Reset: 00H
T2CCU CaptureCcompare
Timer Control Register
Bit Field
C6H
7
6
3
2
1
0
CCTPRE
CCTO
VF
CCTO
VEN
TIMSY
N
CCTS
T
rw
rwh
rw
rw
rw
Type
5
4
RMAP = 0, PAGE 2
C0H
C1H
C2H
C3H
C4H
C5H
C6H
T2CCU_COSHDWReset: 00H
T2CCU Capture/compare
Enable Register
Bit Field
T2CCU_CC0L
Reset: 00H
T2CCU Capture/Compare
Register 0 Low
Bit Field
T2CCU_CC0H
Reset: 00H
T2CCU Capture/compare
Register 0 High
Bit Field
T2CCU_CC1L
Reset: 00H
T2CCU Capture/compare
Register 1 Low
Bit Field
T2CCU_CC1H
Reset: 00H
T2CCU Capture/compare
Register 1 High
Bit Field
T2CCU_CC2L
Reset: 00H
T2CCU Capture/compare
Register 2 Low
Bit Field
T2CCU_CC2H
Reset: 00H
T2CCU Capture/compare
Register 2 High
Bit Field
Type
ENSH
DW
TXOV
COOU
T5
COOU
T4
COOU
T3
COOU
T2
COOU
T1
COOU
T0
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
CCVALL
Type
rwh
CCVALH
Type
rwh
CCVALL
Type
rwh
CCVALH
Type
rwh
CCVALL
Type
rwh
CCVALH
Type
rwh
RMAP = 0, PAGE 3
C0H
C1H
C2H
C3H
C4H
C5H
C6H
T2CCU_COCON Reset: 00H
T2CCU Compare Control
Register
Bit Field
T2CCU_CC3L
Reset: 00H
T2CCU Capture/compare
Register 3 Low
Bit Field
T2CCU_CC3H
Reset: 00H
T2CCU Capture/compare
Register 3 High
Bit Field
T2CCU_CC4L
Reset: 00H
T2CCU Capture/compare
Register 4 Low
Bit Field
T2CCU_CC4H
Reset: 00H
T2CCU Capture/compare
Register 4 High
Bit Field
T2CCU_CC5L
Reset: 00H
T2CCU Capture/compare
Register 5 Low
Bit Field
T2CCU_CC5H
Reset: 00H
T2CCU Capture/compare
Register 5 High
Bit Field
Data Sheet
Type
CCM5
CCM4
CM5F
CM4F
POLB
POLA
COMOD
rw
rw
rwh
rwh
rw
rw
rw
CCVALL
Type
rwh
CCVALH
Type
rwh
CCVALL
Type
rwh
CCVALH
Type
rwh
CCVALL
Type
rwh
CCVALH
Type
rwh
48
V1.5, 2011-03
XC87xCLM
Functional Description
Table 12
T2CCU Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0, PAGE 4
C2H
C3H
T2CCU_CCTDTCLReset: 00H
T2CCU Capture/Compare
Timer Dead-Time Control
Register Low
Bit Field
T2CCU_CCTDTCHReset: 00H
T2CCU Capture/Compare
Timer Dead-Time Control
Register High
Bit Field
3.2.4.9
DTM
Type
Type
rw
DTRE
S
DTR2
DTR1
DTR0
DTLEV
DTE2
DTE1
DTE0
rwh
rh
rh
rh
rw
rw
rw
rw
Timer 21 Registers
The Timer 21 SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 13
T21 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
Bit Field
TF2
EXF2
0
EXEN
2
TR2
C/T2
CP/
RL2
Type
rwh
rwh
r
rw
rwh
rw
rw
T2RE
GS
T2RH
EN
EDGE
SEL
PREN
rw
rw
rw
rw
RMAP = 1
C0H
C1H
T21_T2CON
Reset: 00H
Timer 2 Control Register
T21_T2MOD
Reset: 00H
Timer 2 Mode Register
Bit Field
Type
C2H
C3H
C4H
C5H
C6H
T2PRE
rw
rw
DCEN
rw
rw
T21_RC2L
Reset: 00H
Timer 2 Reload/Capture
Register Low
Bit Field
RC2
Type
rwh
T21_RC2H
Reset: 00H
Timer 2 Reload/Capture
Register High
Bit Field
RC2
Type
rwh
T21_T2L
Reset: 00H
Timer 2 Register Low
Bit Field
T21_T2H
Reset: 00H
Timer 2 Register High
Bit Field
T21_T2CON1
Reset: 03H
Timer 2 Control Register 1
Bit Field
0
TF2EN
EXF2E
N
Type
r
rw
rw
Data Sheet
THL2
Type
rwh
THL2
Type
rwh
49
V1.5, 2011-03
XC87xCLM
Functional Description
3.2.4.10 CCU6 Registers
The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 14
CCU6 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
A3H
CCU6_PAGE
Page Register
Reset: 00H
Bit Field
OP
STNR
0
PAGE
w
w
r
rwh
Type
RMAP = 0, PAGE 0
9AH
9BH
9CH
CCU6_CC63SRL
Reset: 00H
Capture/Compare Shadow Register
for Channel CC63 Low
Bit Field
CCU6_CC63SRH
Reset: 00H
Capture/Compare Shadow Register
for Channel CC63 High
Bit Field
CCU6_TCTR4L
Reset: 00H
Timer Control Register 4 Low
Bit Field
Type
CCU6_TCTR4H
Reset: 00H
Timer Control Register 4 High
rw
CC63SH
Type
Type
9DH
CC63SL
Bit Field
Type
9EH
CCU6_MCMOUTSL
Reset: 00H
Multi-Channel Mode Output Shadow
Register Low
Bit Field
9FH
CCU6_MCMOUTSH
Reset: 00H
Multi-Channel Mode Output Shadow
Register High
Bit Field
CCU6_ISRL
Reset: 00H
Capture/Compare Interrupt Status
Reset Register Low
Bit Field
CCU6_ISRH
Reset: 00H
Capture/Compare Interrupt Status
Reset Register High
Bit Field
T12
STD
T12
STR
0
DT
RES
T12
RES
T12R
S
T12R
R
w
w
r
w
w
w
w
T13
STD
T13
STR
0
T13
RES
T13R
S
T13R
R
w
w
r
w
w
w
STRM
CM
0
MCMPS
w
r
STRH
P
0
CURHS
EXPHS
w
r
rw
rw
RT12
PM
RT12
OM
RCC6
2F
RCC6
2R
RCC6
1F
RCC6
1R
RCC6
0F
RCC6
0R
w
w
w
w
w
w
w
w
RSTR
RIDLE
RWH
E
RCHE
0
RTRP
F
RT13
PM
RT13
CM
Type
w
w
w
w
r
w
w
w
CCU6_CMPMODIFL
Reset: 00H
Compare State Modification Register
Low
Bit Field
0
MCC6
3S
0
MCC6
2S
MCC6
1S
MCC6
0S
Type
r
w
r
w
w
w
A7H
CCU6_CMPMODIFH Reset: 00H
Compare State Modification Register
High
Bit Field
0
MCC6
3R
0
MCC6
2R
MCC6
1R
MCC6
0R
Type
r
w
r
w
w
w
FAH
CCU6_CC60SRL
Reset: 00H
Capture/Compare Shadow Register
for Channel CC60 Low
Bit Field
CCU6_CC60SRH
Reset: 00H
Capture/Compare Shadow Register
for Channel CC60 High
Bit Field
A4H
A5H
A6H
FBH
Data Sheet
Type
rw
Type
Type
rw
CC60SL
Type
rwh
CC60SH
Type
rwh
50
V1.5, 2011-03
XC87xCLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
FCH
CCU6_CC61SRL
Reset: 00H
Capture/Compare Shadow Register
for Channel CC61 Low
Bit Field
CCU6_CC61SRH
Reset: 00H
Capture/Compare Shadow Register
for Channel CC61 High
Bit Field
CCU6_CC62SRL
Reset: 00H
Capture/Compare Shadow Register
for Channel CC62 Low
Bit Field
CCU6_CC62SRH
Reset: 00H
Capture/Compare Shadow Register
for Channel CC62 High
Bit Field
FDH
FEH
FFH
7
6
5
4
3
2
1
0
CC61SL
Type
rwh
CC61SH
Type
rwh
CC62SL
Type
rwh
CC62SH
Type
rwh
RMAP = 0, PAGE 1
9AH
9BH
9CH
9DH
9EH
9FH
A4H
A5H
A6H
CCU6_CC63RL
Reset: 00H
Capture/Compare Register for
Channel CC63 Low
Bit Field
CCU6_CC63RH
Reset: 00H
Capture/Compare Register for
Channel CC63 High
Bit Field
CCU6_T12PRL
Reset: 00H
Timer T12 Period Register Low
Bit Field
CCU6_T12PRH
Reset: 00H
Timer T12 Period Register High
Bit Field
CCU6_T13PRL
Reset: 00H
Timer T13 Period Register Low
Bit Field
CCU6_T13PRH
Reset: 00H
Timer T13 Period Register High
Bit Field
Type
rwh
CCU6_T12DTCL
Reset: 00H
Dead-Time Control Register for
Timer T12 Low
Bit Field
DTM
CCU6_T12DTCH
Reset: 00H
Dead-Time Control Register for
Timer T12 High
Bit Field
0
DTR2
DTR1
DTR0
0
DTE2
DTE1
DTE0
Type
r
rh
rh
rh
r
rw
rw
rw
CCU6_TCTR0L
Reset: 00H
Timer Control Register 0 Low
Bit Field
CTM
CDIR
STE1
2
T12R
T12
PRE
T12CLK
rw
rh
rh
rh
rw
rw
Type
FAH
FBH
FCH
CCU6_TCTR0H
Reset: 00H
Timer Control Register 0 High
CC63VH
rh
T12PVL
Type
rwh
T12PVH
Type
rwh
T13PVL
Type
rwh
T13PVH
Type
rw
Bit Field
0
STE1
3
T13R
T13
PRE
T13CLK
Type
r
rh
rh
rw
rw
CCU6_CC60RL
Reset: 00H
Capture/Compare Register for
Channel CC60 Low
Bit Field
CCU6_CC60RH
Reset: 00H
Capture/Compare Register for
Channel CC60 High
Bit Field
CCU6_CC61RL
Reset: 00H
Capture/Compare Register for
Channel CC61 Low
Bit Field
Data Sheet
rh
Type
Type
A7H
CC63VL
CC60VL
Type
rh
CC60VH
Type
rh
CC61VL
Type
rh
51
V1.5, 2011-03
XC87xCLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
FDH
CCU6_CC61RH
Reset: 00H
Capture/Compare Register for
Channel CC61 High
Bit Field
CCU6_CC62RL
Reset: 00H
Capture/Compare Register for
Channel CC62 Low
Bit Field
CCU6_CC62RH
Reset: 00H
Capture/Compare Register for
Channel CC62 High
Bit Field
FEH
FFH
7
6
5
4
3
2
1
0
CC61VH
Type
rh
CC62VL
Type
rh
CC62VH
Type
rh
RMAP = 0, PAGE 2
CCU6_T12MSELL
Reset: 00H
T12 Capture/Compare Mode Select
Register Low
Bit Field
CCU6_T12MSELH
Reset: 00H
T12 Capture/Compare Mode Select
Register High
Bit Field
9CH
CCU6_IENL
Reset: 00H
Capture/Compare Interrupt Enable
Register Low
Bit Field
9DH
CCU6_IENH
Reset: 00H
Capture/Compare Interrupt Enable
Register High
Bit Field
CCU6_INPL
Reset: 40H
Capture/Compare Interrupt Node
Pointer Register Low
Bit Field
9AH
9BH
9FH
A4H
A5H
A6H
A7H
FAH
FBH
FCH
MSEL60
rw
rw
Type
Type
Type
9EH
MSEL61
Type
DBYP
HSYNC
MSEL62
rw
rw
rw
ENT1
2
PM
ENT1
2
OM
ENCC
62F
ENCC
62R
ENCC
61F
ENCC
61R
ENCC
60F
ENCC
60R
rw
rw
rw
rw
rw
rw
rw
rw
EN
STR
EN
IDLE
EN
WHE
EN
CHE
0
EN
TRPF
ENT1
3PM
ENT1
3CM
rw
rw
rw
rw
r
rw
rw
rw
INPCHE
INPCC62
INPCC61
INPCC60
Type
rw
rw
rw
rw
CCU6_INPH
Reset: 39H
Capture/Compare Interrupt Node
Pointer Register High
Bit Field
0
INPT13
INPT12
INPERR
Type
r
rw
rw
rw
CCU6_ISSL
Reset: 00H
Capture/Compare Interrupt Status
Set Register Low
Bit Field
CCU6_ISSH
Reset: 00H
Capture/Compare Interrupt Status
Set Register High
Bit Field
CCU6_PSLR
Reset: 00H
Passive State Level Register
Bit Field
Type
Type
Type
ST12
PM
ST12
OM
SCC6
2F
SCC6
2R
SCC6
1F
SCC6
1R
SCC6
0F
SCC6
0R
w
w
w
w
w
w
w
w
SSTR
SIDLE
SWHE
SCHE
SWH
C
STRP
F
ST13
PM
ST13
CM
w
w
w
w
w
w
w
w
PSL63
0
PSL
rwh
r
rwh
CCU6_MCMCTR
Reset: 00H Bit Field
Multi-Channel Mode Control Register
Type
CCU6_TCTR2L
Reset: 00H
Timer Control Register 2 Low
CCU6_TCTR2H
Reset: 00H
Timer Control Register 2 High
CCU6_MODCTRL
Reset: 00H
Modulation Control Register Low
SWSYN
0
SWSEL
r
rw
r
rw
Bit Field
0
T13TED
T13TEC
T13
SSC
T12
SSC
Type
r
rw
rw
rw
rw
Bit Field
0
T13RSEL
T12RSEL
Type
r
rw
rw
Bit Field
Type
Data Sheet
0
MCM
EN
0
T12MODEN
rw
r
rw
52
V1.5, 2011-03
XC87xCLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
FDH
Bit Field
CCU6_MODCTRH
Reset: 00H
Modulation Control Register High
Type
FEH
FFH
CCU6_TRPCTRL
Reset: 00H
Trap Control Register Low
CCU6_TRPCTRH
Reset: 00H
Trap Control Register High
7
6
5
4
3
2
ECT1
3O
0
T13MODEN
rw
r
rw
1
0
Bit Field
0
TRPM
2
TRPM
1
TRPM
0
Type
r
rw
rw
rw
Bit Field
TRPP
EN
TRPE
N13
TRPEN
Type
rw
rw
rw
CCU6_MCMOUTL
Reset: 00H
Multi-Channel Mode Output Register
Low
Bit Field
0
R
MCMP
Type
r
rh
rh
CCU6_MCMOUTH
Reset: 00H
Multi-Channel Mode Output Register
High
Bit Field
0
CURH
EXPH
Type
r
rh
rh
CCU6_ISL
Reset: 00H
Capture/Compare Interrupt Status
Register Low
Bit Field
CCU6_ISH
Reset: 00H
Capture/Compare Interrupt Status
Register High
Bit Field
CCU6_PISEL0L
Reset: 00H
Port Input Select Register 0 Low
Bit Field
9FH
CCU6_PISEL0H
Reset: 00H
Port Input Select Register 0 High
Bit Field
A4H
CCU6_PISEL2
Reset: 00H
Port Input Select Register 2
Bit Field
0
IST13HR
Type
r
rw
CCU6_T12L
Reset: 00H
Timer T12 Counter Register Low
Bit Field
CCU6_T12H
Reset: 00H
Timer T12 Counter Register High
Bit Field
CCU6_T13L
Reset: 00H
Timer T13 Counter Register Low
Bit Field
CCU6_T13H
Reset: 00H
Timer T13 Counter Register High
Bit Field
CCU6_CMPSTATL
Reset: 00H
Compare State Register Low
Bit Field
0
CC63
ST
CC
POS2
CC
POS1
CC
POS0
CC62
ST
CC61
ST
CC60
ST
Type
r
rh
rh
rh
rh
rh
rh
rh
T13IM
COUT
63PS
COUT
62PS
CC62
PS
COUT
61PS
CC61
PS
COUT
60PS
CC60
PS
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
RMAP = 0, PAGE 3
9AH
9BH
9CH
9DH
9EH
FAH
FBH
FCH
FDH
FEH
FFH
CCU6_CMPSTATH
Reset: 00H
Compare State Register High
Type
Type
T12
OM
ICC62
F
ICC62
R
ICC61
F
ICC61
R
ICC60
F
ICC60
R
rh
rh
rh
rh
rh
rh
rh
rh
STR
IDLE
WHE
CHE
TRPS
TRPF
T13
PM
T13
CM
rh
rh
rh
rh
rh
rh
rh
rh
ISTRP
ISCC62
ISCC61
ISCC60
rw
rw
rw
rw
IST12HR
ISPOS2
ISPOS1
ISPOS0
rw
rw
rw
Type
Type
rwh
T12CVH
Type
rwh
T13CVL
Type
rwh
T13CVH
Type
Bit Field
rw
T12CVL
Type
Type
Data Sheet
T12
PM
rwh
53
V1.5, 2011-03
XC87xCLM
Functional Description
3.2.4.11 UART1 Registers
The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 15
UART1 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
rw
rw
rw
rw
rw
rwh
rwh
rwh
RMAP = 1
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
SCON
Reset: 00H
Serial Channel Control Register
Bit Field
SBUF
Reset: 00H
Serial Data Buffer Register
Bit Field
VAL
Type
rwh
BCON
Reset: 00H
Baud Rate Control Register
Bit Field
0
BRPRE
R
Type
r
rw
rw
BG
Reset: 00H
Baud Rate Timer/Reload
Register
Bit Field
FDCON
Reset: 00H
Fractional Divider Control
Register
Bit Field
0
NDOV
FDM
FDEN
Type
r
rwh
rw
rw
FDSTEP
Reset: 00H
Fractional Divider Reload
Register
Bit Field
FDRES
Reset: 00H
Fractional Divider Result
Register
Bit Field
SCON1
Reset: 07H
Serial Channel Control Register
1
Bit Field
0
NDOV
EN
TIEN
RIEN
Type
r
rw
rw
rw
2
1
0
Type
BR_VALUE
Type
rwh
STEP
Type
rw
RESULT
Type
rh
3.2.4.12 SSC Registers
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 16
SSC Register Overview
Addr Register Name
Bit
7
6
5
4
3
RMAP = 0
A9H
AAH
AAH
ABH
SSC_PISEL
Reset: 00H
Port Input Select Register
Bit Field
0
CIS
SIS
MIS
Type
r
rw
rw
rw
SSC_CONL
Reset: 00H
Control Register Low
Programming Mode
Bit Field
LB
PO
PH
HB
BM
Type
rw
rw
rw
rw
rw
SSC_CONL
Reset: 00H
Control Register Low
Operating Mode
Bit Field
0
BC
Type
r
rh
SSC_CONH
Reset: 00H
Control Register High
Programming Mode
Bit Field
EN
MS
0
AREN
BEN
PEN
REN
TEN
Type
rw
rw
r
rw
rw
rw
rw
rw
Data Sheet
54
V1.5, 2011-03
XC87xCLM
Functional Description
Table 16
SSC Register Overview (cont’d)
Addr Register Name
Bit
ABH
SSC_CONH
Reset: 00H
Control Register High
Operating Mode
SSC_TBL
Reset: 00H
Transmitter Buffer Register Low
Bit Field
SSC_RBL
Reset: 00H
Receiver Buffer Register Low
Bit Field
SSC_BRL
Reset: 00H
Baud Rate Timer Reload
Register Low
Bit Field
SSC_BRH
Reset: 00H
Baud Rate Timer Reload
Register High
Bit Field
ACH
ADH
AEH
AFH
7
6
5
4
3
2
1
0
Bit Field
EN
MS
0
BSY
BE
PE
RE
TE
Type
rw
rw
r
rh
rwh
rwh
rwh
rwh
TB_VALUE
Type
rw
RB_VALUE
Type
rh
BR_VALUE
Type
rw
BR_VALUE
Type
rw
3.2.4.13 MultiCAN Registers
The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0).
Table 17
CAN Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
ADCON
Reset: 00H
CAN Address/Data Control
Register
Bit Field
V3
V2
V1
V0
AUAD
BSY
RWEN
Type
rw
rw
rw
rw
rw
rh
rw
ADL
Reset: 00H
CAN Address Register Low
Bit Field
CA9
CA8
CA7
CA6
CA5
CA4
CA3
CA2
Type
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
DAH
ADH
Reset: 00H
CAN Address Register High
Bit Field
0
CA13
CA12
CA11
CA10
Type
r
DBH
DATA0
Reset: 00H
CAN Data Register 0
Bit Field
CD
rwh
rwh
rwh
rwh
Type
rwh
DATA1
Reset: 00H
CAN Data Register 1
Bit Field
CD
Type
rwh
DATA2
Reset: 00H
CAN Data Register 2
Bit Field
CD
Type
rwh
DATA3
Reset: 00H
CAN Data Register 3
Bit Field
CD
Type
rwh
RMAP = 0
D8H
D9H
DCH
DDH
DEH
3.2.4.14 OCDS Registers
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).
Data Sheet
55
V1.5, 2011-03
XC87xCLM
Functional Description
Table 18
OCDS Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
STMO
DE
EXBC
DSUS
P
MBCO
N
ALTDI
MMEP
MMOD
E
JENA
rw
rw
rw
rwh
rw
rwh
rh
rh
RMAP = 1
Bit Field
E9H
MMCR2
Reset: 8UH
Monitor Mode Control 2
Register
EAH
MEXTCR
Reset: 0UH
Memory Extension Control
Register
Bit Field
0
BANKBPx
Type
r
rw
MMWR1
Reset: 00H
Monitor Work Register 1
Bit Field
MMWR2
Reset: 00H
Monitor Work Register 2
Bit Field
MMCR
Reset: 00H
Monitor Mode Control Register
Bit Field
EBH
ECH
F1H
Type
Type
MMSR
Reset: 00H
Monitor Mode Status Register
Bit Field
Type
F3H
MMBPCR
Reset: 00H
Breakpoints Control Register
Bit Field
Type
F4H
F5H
F6H
F7H
rw
MMWR2
Type
Type
F2H
MMWR1
rw
MEXIT
_P
MEXIT
0
MSTE
P
MRAM
S_P
MRAM
S
TRF
RRF
w
rwh
r
rw
w
rwh
rh
rh
MBCA
M
MBCIN
EXBF
SWBF
HWB3
F
HWB2
F
HWB1
F
HWB0
F
rw
rwh
rwh
rwh
rwh
rwh
rwh
rwh
SWBC
HWB3C
HWB2C
HWB1
C
HWB0C
rw
rw
rw
rw
rw
MMICR
Reset: 00H
Monitor Mode Interrupt Control
Register
Bit Field
MMDR
Reset: 00H
Monitor Mode Data Transfer
Register
Receive
Bit Field
HWBPSR
Reset: 00H
Hardware Breakpoints Select
Register
Bit Field
0
BPSEL
_P
BPSEL
Type
r
w
rw
HWBPDR
Reset: 00H
Hardware Breakpoints Data
Register
Bit Field
Data Sheet
Type
DVEC
T
DRET
R
COMR
ST
MSTS
EL
MMUI
E_P
MMUI
E
RRIE_
P
RRIE
rwh
rwh
rwh
rh
w
rw
w
rw
MMRR
Type
rh
HWBPxx
Type
rw
56
V1.5, 2011-03
XC87xCLM
Functional Description
3.2.4.15 Flash Registers
The Flash SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 19
Flash Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
Bit Field
0
FBSY
YE
1
NVST
R
MAS1
ERAS
E
PROG
Type
r
rh
rwh
r
rw
rw
rw
rw
Bit Field
0
EEBS
Y
YE
1
NVST
R
MAS1
ERAS
E
PROG
Type
r
rh
rwh
r
rw
rw
rw
rw
FCS
Reset: 80H
Flash Control and Status
Register
Bit Field
1
SBEIE
FTEN
0
EEDE
RR
EESE
RR
FDER
R
FSER
R
Type
r
rw
rwh
r
rwh
rwh
rwh
rwh
FEAL
Reset: 00H
Flash Error Address Register,
Low Byte
Bit Field
FEAH
Reset: 00H
Flash Error Address Register,
High Byte
Bit Field
FTVAL
Reset: 78H
Flash Timer Value Register
Bit Field
FCS1
Reset: 00H
Flash Control and Status
Register 1
Bit Field
0
EEAB
ORT
Type
r
rwh
RMAP = 1
D1H
D2H
D3H
D4H
D5H
D6H
DDH
FCON
Reset: 10H
P-Flash Control Register
EECON
Reset: 10H
D-Flash Control Register
Data Sheet
ECCEADDR
Type
rh
ECCEADDR
Type
Type
rh
MODE
OFVAL
rw
rw
57
V1.5, 2011-03
XC87xCLM
Functional Description
3.3
Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory,
allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V
supply from the Embedded Voltage Regulator (EVR) and does not require additional
programming or erasing voltage. The pagination of the Flash memory allows each page
to be erased independently.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
In-System Programming (ISP) via UART
In-Application Programming (IAP)
Error Correction Code (ECC) for dynamic correction of single-bit errors
Background program and erase operations for CPU load minimization
Support for aborting erase operation
Minimum program width
of 1-byte for D-Flash and 2-bytes for P-Flash
1-page minimum erase width
1-byte read access
Flash is delivered in erased state (read all ones)
Operating supply voltage: 2.5 V ± 7.5 %
Read access time: 1 × tCCLK = 38 ns1)
Program time for 1 wordline: 1.6 ms2)
Page erase time: 20 ms
Mass erase time: 200 ms
1) Values shown here are typical values. fsys = 144 MHz ± 7.5% (fCCLK = 24 MHz ± 7.5 %) is the maximum
frequency range for Flash read access.
2) Values shown here are typical values. fsys = 144 MHz ± 7.5% (fCCLK = 24 MHz ± 7.5 %) is the typical frequency
range for Flash programming and erasing. fsysmin is used for obtaining the worst case timing.
Data Sheet
58
V1.5, 2011-03
XC87xCLM
Functional Description
Table 20 and Table 21 shows the Flash data retention and endurance targets for
Industrial profile and Automotive profile respectively.
Table 20
Flash Data Retention and Endurance for Industrial Profile
(Operating Conditions apply)
Endurance1)2)
Size
1000 cycles
up to 60 Kbytes
15 years
1000 cycles
4 Kbytes
10 years
10,000 cycles
4 Kbytes
5 years
30,000 cycles
4 Kbytes
1 year
100,000 cycles
4 Kbytes
Retention
Remarks
Program Flash
15 years
Data Flash
80,000 cycles
SAF and SAX variant
SAK variant
1) In Program Flash, one cycle refers to the programming of all pages in the flash bank and a mass erase.
2) In Data Flash, one cycle refers to the programming of all wordlines in a page and a page erase.
Table 21
Flash Data Retention and Endurance for Automotive Profile
(Operating Conditions apply)
Endurance1)2)
Size
1000 cycles
up to 60 Kbytes
15 years
1000 cycles
4 Kbytes
5 years
10,000 cycles
1 Kbytes
2 years
15,000 cycles
512 Bytes
2 years
30,000 cycles
256 Bytes
1 year
100,000 cycles
128 Bytes
Retention
Remarks
Program Flash
15 years
Data Flash
1) In Program Flash, one cycle refers to the programming of all pages in the flash bank and a mass erase.
2) In Data Flash, one cycle refers to the programming of all wordlines in a page and a page erase.
Data Sheet
59
V1.5, 2011-03
XC87xCLM
Functional Description
3.3.1
Flash Bank Pagination
The XC87x product family offers Flash devices with either 64 Kbytes or 52 Kbytes of
embedded Flash memory. Each Flash device consists of a Program Flash (P-Flash) and
a single Data Flash (D-Flash) bank. P-Flash has 120 pages of 8 wordlines per page with
64 bytes per wordline. D-Flash has 64 pages of 2 wordlines per page with 32 bytes per
wordline. Both types can be used for code and data storage.. The label “Data” neither
implies that the D-Flash is mapped to the data memory region, nor that it can only be
used for data storage. It is used to distinguish the different page width and wordline of
each Flash bank.
The internal structure of each Flash bank represents a page architecture for flexible
erase capability. The minimum erase width is always a complete page. The D-Flash
bank is divided into smaller size for extended erasing and reprogramming capability;
even numbers for each page size are provided to allow greater flexibility and the ability
to adapt to a wide range of application requirements.
Data Sheet
60
V1.5, 2011-03
XC87xCLM
Functional Description
3.4
Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt
requests. In addition to the standard interrupt functions supported by the core, e.g.,
configurable interrupt priority and interrupt masking, the XC87x interrupt system
provides extended interrupt support capabilities such as the mapping of each interrupt
vector to several interrupt sources to increase the number of interrupt sources
supported, and additional status registers for detecting and determining the interrupt
source.
3.4.1
Interrupt Source
Figure 12 to Figure 16 give a general overview of the interrupt sources and nodes, and
their corresponding control and status flags.
WDT Overflow
FNMIWDT
NMIISR.0
NMIWDT
NMICON.0
PLL Loss of Clock
FNMIPLL
NMIISR.1
NMIPLL
NMICON.1
Flash Timer Overflow
FNMIFLASH
NMIISR.2
>=1
NMIFLASH
NMICON.2
VDDP Pre-Warning
0073
H
Non
Maskable
Interrupt
FNMIVDDP
NMIISR.5
NMIVDDP
NMICON.5
Flash ECC Error
FNMIECC
NMIISR.6
NMIECC
NMICON.6
Figure 12
Data Sheet
Non-Maskable Interrupt Request Sources
61
V1.5, 2011-03
XC87xCLM
Functional Description
Highest
Timer 0
Overflow
TF0
TCON.5
ET0
000B
H
IEN0.1
Timer 1
Overflow
Lowest
Priority Level
IP.1/
IPH.1
TF1
TCON.7
ET1
001B
H
IEN0.3
UART
Receive
IP.3/
IPH.3
RI
SCON.0
UART
Transmit
>=1
TI
ES
SCON.1
IEN0.4
0023
H
IP.4/
IPH.4
IE0
EINT0
P
o
l
l
i
n
g
TCON.1
IT0
EX0
0003
H
IEN0.0
TCON.0
S
e
q
u
e
n
c
e
IP.0/
IPH.0
EXINT0
EXICON0.0/1
IE1
EINT1
TCON.3
IT1
EX1
0013
H
IEN0.2
TCON.2
EXINT1
IP.2/
IPH.2
EA
EXICON0.2/3
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 13
Data Sheet
Interrupt Request Sources (Part 1)
62
V1.5, 2011-03
XC87xCLM
Functional Description
Timer 2
Overflow
TF2
T2_T2CON.7 TF2EN
T2_T2CON1.1
>=1
T2EX
EXEN2
EDGES
EL
T2_T2MOD.5
Highest
EXF2
T2_T2CON.6 EXF2EN
T2_T2CON1.0
T2_T2CON.3
CCT
Overflow
Lowest
Priority Level
CCTOVF
T2CCU_CCTCON.3
CCTOVEN
T2CCU_CCTCON.2 >=1
Normal Divider
Overflow
NDOV
FDCON.2
NDOVEN
BCON.5
End of
Syn Byte
ET2
EOFSYN
FDCON.4
Syn Byte Error
ERRSYN
MultiCAN
Node 0
FDCON.5
002B
H
IEN0.5
SYNEN
FDCON.6
IP.5/
IPH.5
CANSRC0
IRCON2.0
ADC Service
Request 0
ADCSRC0
IRCON1.3
ADC Service
Request 1
ADCSRC1
IRCON1.4
MultiCAN
Node 1
MultiCAN
Node 2
>=1
CANSRC1
EADC
IRCON1.5
0033
H
IEN1.0
CANSRC2
IP1.0/
IPH1.0
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
EA
IEN0.7
IRCON1.6
Bitaddressable
Request flag is cleared by hardware
Figure 14
Data Sheet
Interrupt Request Sources (Part 2)
63
V1.5, 2011-03
XC87xCLM
Functional Description
SSC Error
Highest
EIR
IRCON1.0
EIREN
Lowest
Priority Level
MODIEN.0
SSC Transmit
TIR
>=1
IRCON1.1
TIREN
ESSC
MODIEN.1
RIR
SSC Receive
003B
H
IEN1.1
IRCON1.2
IP1.1/
IPH1.1
RIREN
MODIEN.2
P
o
l
l
i
n
g
EXINT2
EINT2
IRCON0.2
EXINT2
EXICON0.4/5
RI
UART1_SCON.0
UART1
RIEN
>=1
UART1_SCON1.0
TI
UART1_SCON.1
TIEN
UART1_SCON1.1
Timer 21
Overflow
TF2
EX2
T21_T2CON.7
TF2EN
>=1
T21_T2CON1.1
0043
H
IEN1.2
IP1.2/
IPH1.2
S
e
q
u
e
n
c
e
>=1
EXF2
T21EX
EXEN2
EDGES
EL
T21_T2MOD.5
T21_T2CON.6
EXF2EN
T21_T2CON.3
T21_T2CON1.0
UART1 Normal
Divider Overflow
NDOV
UART1_FDCON.2
NDOVEN
UART1_SCON1.2
CORDIC
EOC
CDSTATC.2
MDU
Result Ready
MDU Error
IRDY
EA
MDUSTAT.0
IEN0.7
IERR
MDUSTAT.1
Bitaddressable
Request flag is cleared by hardware
Figure 15
Data Sheet
Interrupt Request Sources (Part 3)
64
V1.5, 2011-03
XC87xCLM
Functional Description
Highest
Lowest
Priority Level
T2CC0/
EINT3
EXINT3
IRCON0.3
EXINT3
EXICON0.6/7
T2CC1/
EINT4
P
o
l
l
i
n
g
EXINT4
IRCON0.4
EXINT4
EXICON1.0/1
T2CC2/
EINT5
EXINT5
EXM
IRCON0.5
004B
H
IEN1.3
EXINT5
EXICON1.2/3
>=1
T2CC3/
EINT6
EXINT6
IRCON0.6
IP1.3/
IPH1.3
S
e
q
u
e
n
c
e
EXINT6
EXICON1.4/5
Compare Channel 4
CM4F
T2CCU_COCON.4
CM4EN
MODIEN.3
Compare Channel 5
CM5F
T2CCU_COCON.5
IEN0.7
CM5EN
MODIEN.4
MultiCAN Node 3
CANSRC3
EA
IRCON2.4
Bitaddressable
Request flag is cleared by hardware
Figure 16
Data Sheet
Interrupt Request Sources (Part 4)
65
V1.5, 2011-03
XC87xCLM
Functional Description
Highest
Lowest
CCU6 Interrupt node 0
CCU6SR0
IRCON3.0
MultiCAN Node 4
Priority Level
>=1
CANSRC4
ECCIP0
IRCON3.1
CCU6 Interrupt node 1
IEN1.4
CANSRC5
ECCIP1
IEN1.5
>=1
ECCIP2
CANSRC6
IP1.5/
IPH1.5
0063
H
IP1.6/
IPH1.6
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
CCU6SRC3
IRCON4.4
MultiCAN Node 7
H
IEN1.6
IRCON4.1
CCU6 Interrupt node 3
005B
CCU6SR2
IRCON4.0
MultiCAN Node 6
IP1.4/
IPH1.4
>=1
IRCON3.5
CCU6 Interrupt node 2
H
CCU6SR1
IRCON3.4
MultiCAN Node 5
0053
>=1
CANSRC7
IRCON4.5
ECCIP3
IEN1.7
006B
H
IP1.7/
IPH1.7
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 17
Data Sheet
Interrupt Request Sources (Part 5)
66
V1.5, 2011-03
XC87xCLM
Functional Description
3.4.2
Interrupt Source and Vector
Each interrupt event source has an associated interrupt vector address for the interrupt
node it belongs to. This vector is accessed to service the corresponding interrupt node
request. The interrupt service of each interrupt source can be individually enabled or
disabled via an enable bit. The assignment of the XC87x interrupt sources to the
interrupt vector address and the corresponding interrupt node enable bits are
summarized in Table 22.
Table 22
Interrupt
Source
NMI
Interrupt Vector Addresses
Vector
Address
Assignment for XC87x
Enable Bit
SFR
0073H
Watchdog Timer NMI
NMIWDT
NMICON
PLL NMI
NMIPLL
Flash Timer NMI
NMIFLASH
VDDP Prewarning NMI
NMIVDDP
Flash ECC NMI
NMIECC
XINTR0
0003H
External Interrupt 0
EX0
XINTR1
000BH
Timer 0
ET0
XINTR2
0013H
External Interrupt 1
EX1
XINTR3
001BH
Timer 1
ET1
XINTR4
0023H
UART
ES
XINTR5
002BH
T2CCU
ET2
IEN0
UART Fractional Divider
(Normal Divider Overflow)
MultiCAN Node 0
LIN
Data Sheet
67
V1.5, 2011-03
XC87xCLM
Functional Description
Table 22
Interrupt
Source
XINTR6
Interrupt Vector Addresses (cont’d)
Vector
Address
Assignment for XC87x
Enable Bit
SFR
0033H
MultiCAN Nodes 1 and 2
EADC
IEN1
ADC[1:0]
XINTR7
003BH
SSC
ESSC
XINTR8
0043H
External Interrupt 2
EX2
T21
CORDIC
UART1
UART1 Fractional Divider
(Normal Divider Overflow)
MDU[1:0]
XINTR9
004BH
External Interrupt 3
EXM
External Interrupt 4
External Interrupt 5
External Interrupt 6
T2CCU
MultiCAN Node 3
XINTR10
0053H
CCU6 INP0
ECCIP0
MultiCAN Node 4
XINTR11
005BH
CCU6 INP1
ECCIP1
MultiCAN Node 5
XINTR12
0063H
CCU6 INP2
ECCIP2
MultiCAN Node 6
XINTR13
006BH
CCU6 INP3
ECCIP3
MultiCAN Node 7
Data Sheet
68
V1.5, 2011-03
XC87xCLM
Functional Description
3.4.3
Interrupt Priority
An interrupt that is currently being serviced can only be interrupted by a higher-priority
interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of
the highest priority cannot be interrupted by any other interrupt request.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority are
received simultaneously, then an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence shown in Table 23.
Table 23
Priority Structure within Interrupt Level
Source
Level
Non-Maskable Interrupt (NMI)
(highest)
External Interrupt 0
1
Timer 0 Interrupt
2
External Interrupt 1
3
Timer 1 Interrupt
4
UART Interrupt
5
T2CCU,UART Normal Divider Overflow,
MultiCAN, LIN Interrupt
6
ADC, MultiCAN Interrupt
7
SSC Interrupt
8
External Interrupt 2, Timer 21, UART1, UART1
9
Normal Divider Overflow, MDU, CORDIC Interrupt
External Interrupt [6:3], MultiCAN Interrupt
10
CCU6 Interrupt Node Pointer 0, MultiCAN interrupt 11
CCU6 Interrupt Node Pointer 1, MultiCAN Interrupt 12
CCU6 Interrupt Node Pointer 2, MultiCAN Interrupt 13
CCU6 Interrupt Node Pointer 3, MultiCAN Interrupt 14
Data Sheet
69
V1.5, 2011-03
XC87xCLM
Functional Description
3.5
Parallel Ports
The XC87x has 40 port pins organized into five parallel ports: Port 0 (P0), Port 1 (P1),
Port 3 (P3), Port 4 (P4) and Port 5 (P5). Each pin has a pair of internal pull-up and pulldown devices that can be individually enabled or disabled. These ports are bidirectional
and can be used as general purpose input/output (GPIO) or to perform alternate
input/output functions for the on-chip peripherals. When configured as an output, the
open drain mode can be selected.
Bidirectional Port Features
•
•
•
•
•
•
Configurable pin direction
Configurable pull-up/pull-down devices
Configurable open drain mode
Configurable drive strength
Transfer of data through digital inputs and outputs (general purpose I/O)
Alternate input/output for on-chip peripherals
Data Sheet
70
V1.5, 2011-03
XC87xCLM
Functional Description
Figure 18 shows the structure of a bidirectional port pin.
Px_PUDSEL
Pull-up/Pull-down
Select Register
Pull-up/Pull-down
Control Logic
Internal Bus
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_DS
Drive Strength
Control Register
Px_OD
Open Drain
Control Register
OpenDrain/Output
Control Logic
Px_DIR
Direction Register
Px_ALTSEL0
Alternate Select Register 0
Px_ALTSEL1
Pull
Device
Alternate Select Register 1
AltDataOut 3
Output
Driver
11
AltDataOut 2
AltDataOut1
10
Px_Data
Data Register
01
0
00
1
Out
Pin
Input
Driver
In
Schmitt Trigger
AltDataIn
Pad
Figure 18
Data Sheet
General Structure of Bidirectional Port
71
V1.5, 2011-03
XC87xCLM
Functional Description
3.6
Power Supply System with Embedded Voltage Regulator
The XC87x microcontroller requires two different levels of power supply:
•
•
3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports
2.5 V for the core, memory, on-chip oscillator, and peripherals
Figure 19 shows the XC87x power supply system. A power supply of 3.3 V or 5.0 V
must be provided from the external power supply pin. The 2.5 V power supply for the
logic is generated by the EVR. The EVR helps to reduce the power consumption of the
whole chip and the complexity of the application board design.
The EVR consists of a main voltage regulator and a low power voltage regulator. In
active mode, both voltage regulators are enabled. In power-down mode1), the main
voltage regulator is switched off, while the low power voltage regulator continues to
function and provide power supply to the system with low power consumption.
CPU &
Memory
On-chip
OSC
Peripheral
logic
ADC
VDDC (2.5V)
FLASH
PLL
GPIO Ports
(P0-P5)
XTAL1&
XTAL2
EVR
VDDP (3.3V/5.0V)
VSSP
Figure 19
XC87x Power Supply System
EVR Features
•
•
•
•
•
Input voltage (VDDP): 3.3 V/5.0 V
Output voltage (VDDC): 2.5 V ± 7.5%
Low power voltage regulator provided in power-down mode1)
VDDP prewarning detection
VDDC brownout detection
1) SAK product variant does not support power-down mode.
Data Sheet
72
V1.5, 2011-03
XC87xCLM
Functional Description
3.7
Reset Control
The XC87x has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC87x is first powered up, the status of certain pins (see Table 25) must be
defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
The second type of reset in XC87x is the hardware reset. This reset function can be used
during normal operation or when the chip is in power-down mode. A reset input pin
RESET is provided for the hardware reset.
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system.
Another type of reset that needs to be detected is a reset while the device is in
power-down mode (wake-up reset). While the contents of the static RAM are undefined
after a power-on reset, they are well defined after a wake-up reset from power-down
mode.
3.7.1
Module Reset Behavior
Table 24 lists the functions of the XC87x and the various reset types that affect these
functions. The symbol “■” signifies that the particular function is reset to its default state.
Table 24
Effect of Reset on Device Functions
Module/
Function
Wake-Up
Reset
Watchdog
Reset
Hardware
Reset
Power-On
Reset
Brownout
Reset
CPU Core
■
■
■
■
■
Peripherals
■
■
■
■
■
On-Chip
Static RAM
Not affected, Not affected, Not affected, Affected, un- Affected, unReliable
Reliable
Reliable
reliable
reliable
Oscillator,
PLL
■
Not affected ■
■
■
Port Pins
■
■
■
■
EVR
The voltage
regulator is
switched on
Not affected Not affected ■
■
FLASH
■
■
■
■
■
NMI
Disabled
Disabled
■
■
■
Data Sheet
■
73
V1.5, 2011-03
XC87xCLM
Functional Description
3.7.2
Booting Scheme
When the XC87x is reset, it must identify the type of configuration with which to start the
different modes once the reset sequence is complete. Thus, boot configuration
information that is required for activation of special modes and conditions needs to be
applied by the external world through input pins. After power-on reset or hardware reset,
the pins MBC, TMS and P0.0 collectively select the different boot options. Table 25
shows the available boot options in the XC87x.
Table 25
MBC
TMS
XC87x Boot Selection 1)
P0.0
Type of Mode
PC Start Value
2)
1
0
X
User Mode ; on-chip OSC/PLL non-bypassed 0000H
0
0
X
BSL Mode; (LIN Mode3), UART/ MultiCAN
Mode4)5) and Alternate BSL Mode6)); on-chip
OSC/PLL non-bypassed
0000H
0
1
0
OCDS Mode; on-chip OSC/PLL nonbypassed
0000H
1
1
0
User (JTAG) Mode7); on-chip OSC/PLL nonbypassed (normal)
0000H
1) In addition to the pins MBC, TMS and P0.0, TM pin also requires an external pull down for all the boot options.
2) BSL mode is automatically entered if no valid password is installed and data at memory address 0000H equals
zero.
3) If a device is programmed as LIN, LIN BSL is always used instead of UART/MultiCAN.
4) UART or MultiCAN BSL is decoded by firmware based on the protocol for product variant with MultiCAN. If no
MultiCAN and LIN variant, UART BSL is used.
5) In MultiCAN BSL mode, the clock source is switched to XTAL by firmware, bypassing the on-chip oscillator.
This avoids any frequency invariance with the on-chip oscillator and allows other frequency clock input, thus
ensuring accurate baud rate detection (especially at high bit rates).
6) Alternate BSL Mode is a user defined BSL code programmed in Flash. It is entered if the AltBSLPassword is
valid.
7) Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.
Note: The boot options are valid only with the default set of UART and JTAG pins.
Data Sheet
74
V1.5, 2011-03
XC87xCLM
Functional Description
3.8
Clock Generation Unit
The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the
XC87x. The power consumption is indirectly proportional to the frequency, whereas the
performance of the microcontroller is directly proportional to the frequency. During user
program execution, the frequency can be programmed for an optimal ratio between
performance and power consumption. Therefore the power consumption can be
adapted to the actual application state.
Features
•
•
•
•
•
Phase-Locked Loop (PLL) for multiplying clock source by different factors
PLL Base Mode
Prescaler Mode
PLL Mode
Power-down mode support1)
The CGU consists of an oscillator circuit and a PLL. In the XC87x, the oscillator can be
from either of these two sources: the on-chip oscillator (4 MHz) or the external oscillator
(2 MHz to 20 MHz). The term “oscillator” is used to refer to both on-chip oscillator and
external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be
used by default.The external oscillator can be selected via software. In addition, the PLL
provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows
emergency routines to be executed for system recovery or to perform system shut down.
1) SAK product variant does not support power-down mode.
Data Sheet
75
V1.5, 2011-03
XC87xCLM
Functional Description
PLL_LOCK
Wrapper
PLL
OSC
fosc
NR:1
External
oscillator
watchdog
lock
detect
fp
fn
PLL
core
EXTOSCR
fvco
OD:1
Switching
circuitry
fSYS
PLLR
NF:1
PLL
watchdog
OSCSS
PDIV
Figure 20
PLLPD
NDIV
KDIV
PLLBYP
CGU Block Diagram
Direct Drive (PLL Bypass Operation)
During PLL bypass operation, the system clock has the same frequency as the external
clock source.
(3.1)
f SYS = f OSC
PLL Mode
The CPU clock is derived from the oscillator clock, divided by the NR factor (PDIV),
multiplied by the NF factor (NDIV), and divided by the OD factor (KDIV). PLL output must
Data Sheet
76
V1.5, 2011-03
XC87xCLM
Functional Description
not be bypassed for this PLL mode. The PLL mode is used during normal system
operation.
(3.2)
f SYS = f OSC x
NF
NR x OD
System Frequency Selection
For the XC87x, the value of NF, NR and OD can be selected by bits NDIV, PDIV and
KDIV respectively for different oscillator inputs inorder to obtain the required fsys. But the
combination of these factors must fulfill the following condition:
•
•
100 MHz < fVCO < 175 MHz
800 KHz < fOSC / (2 * NR) < 8 MHz
Table 26 provides examples on how the typical system frequency of fsys = 144 MHz
and maximum frequency of 160 MHz (CPU clock = 26.67 MHz)can be obtained for the
different oscillator sources.
Table 26
System frequency (fsys = 144 MHz)
Oscillator
fosc
N
P
K
fsys
On-chip
4 MHz
72
2
1
144 MHz
4 MHz
80
2
1
160 MHz
8 MHz
72
4
1
144 MHz
6 MHz
72
3
1
144 MHz
4 MHz
72
2
1
144 MHz
External
3.8.1
Recommended External Oscillator Circuits
The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal
oscillator or an external stable clock source. It basically consists of an inverting amplifier
and a feedback element with XTAL1 as input, and XTAL2 as output.
When using a crystal, a proper external oscillator circuitry must be connected to both
pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 2 MHz to
20 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and
depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ
may be temporarily inserted to measure the oscillation allowance (negative resistance)
of the oscillator circuitry. RQ values are typically specified by the crystal vendor. An
external feedback resistor Rf is also required in the external oscillator circuitry. The exact
values and related operating range are dependent on the crystal frequency and have to
be determined and optimized together with the crystal vendor using the negative
Data Sheet
77
V1.5, 2011-03
XC87xCLM
Functional Description
resistance method. Oscillation measurement with the final target system is strongly
recommended to verify the input amplitude at XTAL1 and to determine the actual
oscillation allowance (margin negative resistance) for the oscillator-crystal system.
When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is
left open (unconnected).
The oscillator can also be used in combination with a ceramic resonator. The final
circuitry must also be verified by the resonator vendor. Figure 21 shows the
recommended external oscillator circuitries for both operating modes, external crystal
mode and external input clock mode.
2 - 20
MHz
RQ
XTAL1
Rf
RX2
fOSC
External Clock
Signal
XC87x
Oscillator
XTAL2
CX2
Fundamental
Mode Crystal
Figure 21
fOSC
XC87x
Oscillator
XTAL2
CX1
XTAL1
VSS
VSS
External Oscillator Circuitry
Note: For crystal operation, it is strongly recommended to measure the negative
resistance in the final target system (layout) to determine the optimum parameters
for the oscillator operation. Please refer to the minimum and maximum values of
the negative resistance specified by the crystal supplier.
Data Sheet
78
V1.5, 2011-03
XC87xCLM
Functional Description
3.8.2
Clock Management
The CGU generates all clock signals required within the microcontroller from a single
clock, fsys. During normal system operation, the typical frequencies of the different
modules are as follow:
•
•
•
•
•
•
•
CPU clock: CCLK, SCLK = 24 MHz
MultiCAN clock : MCANCLK = 24 or 48 MHz
MDU clock : MDUCLK = 24 or 48 MHz
CORDIC clock : CORDICCLK = 24 or 48 MHz
CCU6 clock : CCU6CLK = 24 or 48 MHz
T2CCU clock : T2CCUCLK = 24 or 48 MHz
Peripheral clock: PCLK = 24 MHz
In addition, different clock frequencies can be output to pin CLKOUT (P0.0 or P0.7). The
clock output frequency, which is derived from the clock output divider (bit COREL), can
further be divided by 2 using toggle latch (bit TLEN is set to 1). The resulting output
frequency has a 50% duty cycle. Figure 22 shows the clock distribution of the XC87x.
Data Sheet
79
V1.5, 2011-03
XC87xCLM
Functional Description
T2CCFG
CCCFG
T2CCU
CLK
CORDIC
CLK
CORDIC
T2CCU
CCUCCFG
MDUCCFG
MDU
CLK
CCU6
CLK
CCU6
MDU
FCCFG
MCAN
CLK
MultiCAN
CLKREL
SD
1
OSCSS
External
OSC
PCLK
FCLK
SCLK
/2
fosc
PLL
On-chip
OSC
fsys
Peripherals
CCLK
CORE
0
/3
NF,NR,OD
COREL
TLEN
Toggle
Latch
CLKOUT
COUTS
Figure 22
Data Sheet
Clock Generation from fsys
80
V1.5, 2011-03
XC87xCLM
Functional Description
For power saving purposes, the clocks may be disabled or slowed down according to
Table 27.
Table 27
System frequency (fsys = 144 MHz)
Power Saving Mode
Action
Idle
Clock to the CPU is disabled.
Slow-down
Clocks to the CPU and all the peripherals are divided by a
common programmable factor defined by bit field
CMCON.CLKREL.
Power-down1)
Oscillator and PLL are switched off.
1) SAK product variant does not support power-down mode.
Data Sheet
81
V1.5, 2011-03
XC87xCLM
Functional Description
3.9
Power Saving Modes
The power saving modes of the XC87x provide flexible power consumption through a
combination of techniques, including:
•
•
•
•
Stopping the CPU clock
Stopping the clocks of individual system components
Reducing clock speed of some peripheral components
Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see
Figure 23) and the system runs in the main system clock frequency. From active mode,
different power saving modes can be selected by software. They are:
•
•
•
Idle mode
Slow-down mode
Power-down mode
ACTIVE
any interrupt
& SD=0
set PD
bit
set IDLE
bit
set SD
bit
IDLE
EXINT0/RXD pin
& SD=0
clear SD
bit
set IDLE
bit
any interrupt
& SD=1
Figure 23
POWER-DOWN
set PD
bit
SLOW-DOWN
EXINT0/RXD pin
& SD=1
Transition between Power Saving Modes
Note: SAK product variant does not support power-down mode.
Data Sheet
82
V1.5, 2011-03
XC87xCLM
Functional Description
3.10
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC87x system reset. Hence, routine service of the WDT confirms
that the system is functioning properly. This ensures that an accidental malfunction of
the XC87x will be aborted in a user-specified time period.
In debug mode, the WDT is default suspended and stops counting. Therefore, there is
no need to refresh the WDT during debugging.
Features
•
•
•
•
•
16-bit Watchdog Timer
Programmable reload value for upper 8 bits of timer
Programmable window boundary
Selectable input frequency of fPCLK/2 or fPCLK/128
Time-out detection with NMI generation and reset prewarning activation (after which
a system reset will be performed)
The WDT is a 16-bit timer incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit
timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be
preset to a user-programmable value via a watchdog service access in order to modify
the watchdog expire time period. The lower 8 bits are reset on each service access.
Figure 24 shows the block diagram of the WDT unit.
WDT
Control
Clear
1:2
MUX
f PCLK
WDTREL
WDT Low Byte
WDT High Byte
1:128
Overflow/Time-out Control &
Window-boundary control
WDTIN
ENWDT
FNMIWDT
.
WDTRST
Logic
ENWDT_P
Figure 24
Data Sheet
WDTWINB
WDT Block Diagram
83
V1.5, 2011-03
XC87xCLM
Functional Description
If the WDT is not serviced before the timer overflow, a system malfunction is assumed.
As a result, the WDT NMI is triggered (assert FNMIWDT) and the reset prewarning is
entered. The prewarning period lasts for 30H count, after which the system is reset
(assert WDTRST).
The WDT has a “programmable window boundary” which disallows any refresh during
the WDT’s count-up. A refresh during this window boundary constitutes an invalid
access to the WDT, causing the reset prewarning to be entered but without triggering the
WDT NMI. The system will still be reset after the prewarning period is over. The window
boundary is from 0000H to the value obtained from the concatenation of WDTWINB and
00H.
After being serviced, the WDT continues counting up from the value (<WDTREL> * 28).
The time period for an overflow of the WDT is programmable in two ways:
•
•
The input frequency to the WDT can be selected to be either fPCLK/2 or fPCLK/128
The reload value WDTREL for the high byte of WDT can be programmed in register
WDTREL
The period, PWDT, between servicing the WDT and the next overflow can be determined
by the following formula:
2 ( 1 + WDTIN × 6 ) × ( 2 16 – WDTREL × 2 8 )
P WDT = -----------------------------------------------------------------------------------------------------f PCLK
(3.3)
If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT
between servicing the WDT and the next overflow is shortened if WDTWINB is greater
than WDTREL, see Figure 25. This period can be calculated using the same formula by
replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB cannot be
smaller than WDTREL.
Data Sheet
84
V1.5, 2011-03
XC87xCLM
Functional Description
Count
FFFFH
WDTWINB
WDTREL
time
No refresh
allowed
Figure 25
Refresh allowed
WDT Timing Diagram
Table 28 lists the possible watchdog time ranges that can be achieved using a certain
module clock. Some numbers are rounded to 3 significant digits.
Table 28
Reload value
In WDTREL
Watchdog Time Ranges
Prescaler for fPCLK
2 (WDTIN = 0)
128 (WDTIN = 1)
24 MHz
24 MHz
FFH
21.3 µs
1.37 ms
7FH
2.75 ms
176 ms
00H
5.46 ms
350 ms
Data Sheet
85
V1.5, 2011-03
XC87xCLM
Functional Description
3.11
Multiplication/Division Unit
The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and
32-bit division as well as shift and normalize features. It has been integrated to support
the XC87x Core in real-time control applications, which require fast mathematical
computations.
Features
•
•
•
•
Fast signed/unsigned 16-bit multiplication
Fast signed/unsigned 32-bit divide by 16-bit and 16-bit divide by 16-bit operations
32-bit unsigned normalize operation
32-bit arithmetic/logical shift operations
Table 29 specifies the number of clock cycles used for calculation in various operations.
Table 29
MDU Operation Characteristics
Operation
Result
Remainder
Signed 32-bit/16-bit
32-bit
16-bit
33
Signed 16-bit/16bit
16-bit
16-bit
17
Signed 16-bit x 16-bit
32-bit
-
16
Unsigned 32-bit/16-bit
32-bit
16-bit
32
Unsigned 16-bit/16-bit
16-bit
16-bit
16
Unsigned 16-bit x 16-bit
32-bit
-
16
32-bit normalize
-
-
No. of shifts + 1 (Max. 32)
32-bit shift L/R
-
-
No. of shifts + 1 (Max. 32)
Data Sheet
86
No. of Clock Cycles
used for calculation
V1.5, 2011-03
XC87xCLM
Functional Description
3.12
CORDIC Coprocessor
The CORDIC Coprocessor provides CPU with hardware support for the solving of
circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Modes of operation
– Supports all CORDIC operating modes for solving circular (trigonometric), linear
(multiply-add, divide-add) and hyperbolic functions
– Integrated look-up tables (LUTs) for all operating modes
Circular vectoring mode: Extended support for values of initial X and Y data up to full
range of [-215,(215-1)] for solving angle and magnitude
Circular rotation mode: Extended support for values of initial Z data up to full range
of [-215,(215-1)], representing angles in the range [-π,((215-1)/215)π] for solving
trigonometry
Implementation-dependent operational frequency of up to 80 MHz
Gated clock input to support disabling of module
16-bit accessible data width
– 24-bit kernel data width plus 2 overflow bits for X and Y each
– 20-bit kernel data width plus 1 overflow bit for Z
– With KEEP bit to retain the last value in the kernel register for a new calculation
16 iterations per calculation: Approximately 41 clock-cycles or less, from set of start
(ST) bit to set of end-of-calculation flag, excluding time taken for write and read
access of data bytes.
Twos complement data processing
– Only exception: X result data with user selectable option for unsigned result
X and Y data generally accepted as integer or rational number; X and Y must be of
the same data form
Entries of LUTs are 20-bit signed integers
– Entries of atan and atanh LUTs are integer representations (S19) of angles with
the scaling such that [-215,(215-1)] represents the range [-π,((215-1)/215)π]
– Accessible Z result data for circular and hyperbolic functions is integer in data form
of S15
Emulated LUT for linear function
– Data form is 1 integer bit and 15-bit fractional part (1.15)
– Accessible Z result data for linear function is rational number with fixed data form
of S4.11 (signed 4Q16)
Truncation Error
– The result of a CORDIC calculation may return an approximation due to truncation
of LSBs
– Good accuracy of the CORDIC calculated result data, especially in circular mode
Interrupt
– On completion of a calculation
Data Sheet
87
V1.5, 2011-03
XC87xCLM
Functional Description
– Interrupt enabling and corresponding flag
3.13
UART and UART1
The XC87x provides two Universal Asynchronous Receiver/Transmitter (UART and
UART1) modules for full-duplex asynchronous reception/transmission. Both are also
receive-buffered, i.e., they can commence reception of a second byte before a
previously received byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second byte is complete, one of
the bytes will be lost.
Features
•
•
•
•
Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– Fixed or variable baud rate
Receive buffered
Multiprocessor communication
Interrupt generation on the completion of a data transmission or reception
The UART modules can operate in the four modes shown in Table 30.
Table 30
UART Modes
Operating Mode
Baud Rate
Mode 0: 8-bit shift register
fPCLK/2
Mode 1: 8-bit shift UART
Variable
Mode 2: 9-bit shift UART
fPCLK/32 or fPCLK/641)
Mode 3: 9-bit shift UART
Variable
1) For UART1 module, the baud rate is fixed at fPCLK/64.
There are several ways to generate the baud rate clock for the serial port, depending on
the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at
fPCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock
and can be configured to eitherfPCLK/32 or fPCLK/64. For UART1 module, only fPCLK/64 is
available. The variable baud rate is set by the underflow rate on the dedicated baud-rate
generator. For UART module, the variable baud rate alternatively can be set by the
overflow rate on Timer 1.
3.13.1
Baud-Rate Generator
Both UART modules have their own dedicated baud-rate generator, which is based on
a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and
Data Sheet
88
V1.5, 2011-03
XC87xCLM
Functional Description
fractional divider) for generating a wide range of baud rates based on its input clock fPCLK,
see Figure 26.
Fractional Divider
8-Bit Reload Value
FDSTEP
1
FDM
1
FDEN&FDM
0
Adder
fDIV
00
01
0
FDRES
FDEN
fMOD (overflow)
0
1
11
8-Bit Baud Rate Timer
fBR
10
R
fPCLK
Prescaler
fDIV
clk
11
10
NDOV
01
‘0’
Figure 26
00
Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the
output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See Section 3.14.
The baud rate (fBR) value is dependent on the following parameters:
•
•
•
•
Input clock fPCLK
Prescaling factor (2BRPRE) defined by bit field BRPRE in register BCON
Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional
divider mode)
8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
Data Sheet
89
V1.5, 2011-03
XC87xCLM
Functional Description
The following formulas calculate the final baud rate without and with the fractional divider
respectively:
f PCLK
- where 2 BRPRE × ( BR_VALUE + 1 ) > 1
baud rate = ---------------------------------------------------------------------------------BRPRE
16 × 2
× ( BR_VALUE + 1 )
(3.4)
f PCLK
STEP
- × --------------baud rate = ---------------------------------------------------------------------------------BRPRE
256
16 × 2
× ( BR_VALUE + 1 )
(3.5)
The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module
clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud.
Standard LIN protocol can support a maximum baud rate of 20 kHz, the baud rate
accuracy is not critical and the fractional divider can be disabled. Only the prescaler is
used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of
20 kHz to 57.6 kHz, the higher baud rates require the use of the fractional divider for
greater accuracy.
Table 31 lists the various commonly used baud rates with their corresponding parameter
settings and deviation errors. The fractional divider is disabled and a module clock of
24 MHz is used.
Table 31
Typical Baud rates for UART with Fractional Divider disabled
Baud rate
Prescaling Factor
(2BRPRE)
Reload Value
(BR_VALUE + 1)
Deviation Error
19.2 kBaud
1 (BRPRE=000B)
78 (4EH)
0.17 %
9600 Baud
1 (BRPRE=000B)
156 (9CH)
0.17 %
4800 Baud
2 (BRPRE=001B)
156 (9CH)
0.17 %
2400 Baud
4 (BRPRE=010B)
156 (9CH)
0.17 %
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated. Table 32 lists the resulting deviation errors from generating a baud rate of
57.6 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet
90
V1.5, 2011-03
XC87xCLM
Functional Description
Table 32
fPCLK
Deviation Error for UART with Fractional Divider enabled
Prescaling Factor Reload Value
STEP
(2BRPRE)
(BR_VALUE + 1)
Deviation
Error
24 MHz
1
6 (6H)
59 (3BH)
+0.03 %
12 MHz
1
3 (3H)
59 (3BH)
+0.03 %
8 MHz
1
2 (2H)
59 (3BH)
+0.03 %
6 MHz
1
6 (6H)
236 (ECH)
+0.03 %
3.13.2
Baud Rate Generation using Timer 1
In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the
variable baud rates. In theory, this timer could be used in any of its modes. But in
practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set
to the appropriate value for the required baud rate. The baud rate is determined by the
Timer 1 overflow rate and the value of SMOD as follows:
SMOD
× f PCLK
2
Mode 1, 3 baud rate = ---------------------------------------------------32 × 2 × ( 256 – TH1 )
(3.6)
3.14
Normal Divider Mode (8-bit Auto-reload Timer)
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see Figure 26). Once the
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP.
The output frequency in normal divider mode is derived as follows:
1
f MOD = f DIV × -----------------------------256 – STEP
(3.7)
Data Sheet
91
V1.5, 2011-03
XC87xCLM
Functional Description
3.15
LIN Protocol
The UART module can be used to support the Local Interconnect Network (LIN) protocol
for both master and slave operations. The LIN baud rate detection feature, which
consists of the hardware logic for Break and Synch Byte detection, provides the
capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART
to be synchronized to the LIN baud rate for data transmission and reception.
Note: The LIN baud rate detection feature is available for use only with UART. To use
UART1 for LIN communication, software has to be implemented to detect the
Break and Synch Byte.
LIN is a holistic communication concept for local interconnected networks in vehicles.
The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An
attractive feature of LIN is self-synchronization of the slave nodes without a crystal or
ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the
baud rate must be calculated and returned with every message frame.
The structure of a LIN frame is shown in Figure 27. The frame consists of the:
•
•
•
•
Header, which comprises a Break (13-bit time low), Synch Byte (55H), and ID field
Response time
Data bytes (according to UART protocol)
Checksum
Frame slot
Frame
Header
Synch
Figure 27
3.15.1
Response
space
Protected
identifier
Response
Data 1
Data 2
Data N
Checksum
Structure of LIN Frame
LIN Header Transmission
LIN header transmission is only applicable in master mode. In the LIN communication,
a master task decides when and which frame is to be transferred on the bus. It also
identifies a slave task to provide the data transported by each frame. The information
Data Sheet
92
V1.5, 2011-03
XC87xCLM
Functional Description
needed for the handshaking between the master and slave tasks is provided by the
master task through the header portion of the frame.
The header consists of a break and synch pattern followed by an identifier. Among these
three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.
The break must contain a dominant value of 13 bits or more to ensure proper
synchronization of slave nodes.
In the LIN communication, a slave task is required to be synchronized at the beginning
of the protected identifier field of frame. For this purpose, every frame starts with a
sequence consisting of a break field followed by a synch byte field. This sequence is
unique and provides enough information for any slave task to detect the beginning of a
new frame and be synchronized at the start of the identifier field.
Upon entering LIN communication, a connection is established and the transfer speed
(baud rate) of the serial communication partner (host) is automatically synchronized in
the following steps:
STEP 1: Initialize interface for reception and timer for baud rate measurement
STEP 2: Wait for an incoming LIN frame from host
STEP 3: Synchronize the baud rate to the host
STEP 4: Enter for Master Request Frame or for Slave Response Frame
Note: Re-synchronization and setup of baud rate are always done for every Master
Request Header or Slave Response Header LIN frame.
Data Sheet
93
V1.5, 2011-03
XC87xCLM
Functional Description
3.16
High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and
half-duplex synchronous communication. The serial clock signal can be generated by
the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be
received from an external master (slave mode). Data width, shift direction, clock polarity
and phase are programmable. This allows communication with SPI-compatible devices
or devices using other synchronous serial interfaces.
Features
•
•
•
•
•
•
Master and slave mode operation
– Full-duplex or half-duplex operation
Transmit and receive buffered
Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
Variable baud rate
Compatible with Serial Peripheral Interface (SPI)
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 28 shows the block diagram of the SSC.
Data Sheet
94
V1.5, 2011-03
XC87xCLM
Functional Description
PCLK
Baud-rate
Generator
SS_CLK
MS_CLK
Clock
Control
Shift
Clock
RIR
SSC Control Block
Register CON
Status
Receive Int. Request
TIR
Transmit Int. Request
EIR
Error Int. Request
Control
TXD(Master)
Pin
Control
16-Bit Shift
Register
RXD(Slave)
TXD(Slave)
RXD(Master)
Transmit Buffer
Register TB
Receive Buffer
Register RB
Internal Bus
Figure 28
Data Sheet
SSC Block Diagram
95
V1.5, 2011-03
XC87xCLM
Functional Description
3.17
Timer 0 and Timer 1
Timer 0 and Timer 1 can function as both timers or counters. When functioning as a
timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input
clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are
incremented in response to a 1-to-0 transition (falling edge) at their respective external
input pins, T0 or T1.
Timer 0 and 1 are fully compatible and can be configured in four different operating
modes for use in a variety of applications, see Table 33. In modes 0, 1 and 2, the two
timers operate independently, but in mode 3, their functions are specialized.
Table 33
Timer 0 and Timer 1 Modes
Mode
Operation
0
13-bit timer
The timer is essentially an 8-bit counter with a divide-by-32 prescaler.
This mode is included solely for compatibility with Intel 8048 devices.
1
16-bit timer
The timer registers, TLx and THx, are concatenated to form a 16-bit
counter.
2
8-bit timer with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx
upon overflow.
3
Timer 0 operates as two 8-bit timers
The timer registers, TL0 and TH0, operate as two separate 8-bit counters.
Timer 1 is halted and retains its count even if enabled.
Data Sheet
96
V1.5, 2011-03
XC87xCLM
Functional Description
3.18
Timer 2 and Timer 21
Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible
and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel
capture mode, see Table 34. As a timer, the timers count with an input clock of PCLK/12
(if prescaler is disabled). As a counter, they count 1-to-0 transitions on pin T2. In the
counter mode, the maximum resolution for the count is PCLK/24 (if prescaler is
disabled).
Table 34
Timer 2 Modes
Mode
Description
Auto-reload Up/Down Count Disabled
• Count up only
• Start counting from 16-bit reload value, overflow at FFFFH
• Reload event configurable for trigger by overflow condition only, or by
negative/positive edge at input pin T2EX as well
• Programmble reload value in register RC2
• Interrupt is generated with reload event
Up/Down Count Enabled
• Count up or down, direction determined by level at input pin T2EX
• No interrupt is generated
• Count up
– Start counting from 16-bit reload value, overflow at FFFFH
– Reload event triggered by overflow condition
– Programmble reload value in register RC2
• Count down
– Start counting from FFFFH, underflow at value defined in register
RC2
– Reload event triggered by underflow condition
– Reload value fixed at FFFFH
Channel
capture
Data Sheet
•
•
•
•
•
•
•
Count up only
Start counting from 0000H, overflow at FFFFH
Reload event triggered by overflow condition
Reload value fixed at 0000H
Capture event triggered by falling/rising edge at pin T2EX
Captured timer value stored in register RC2
Interrupt is generated with reload or capture event
97
V1.5, 2011-03
XC87xCLM
Functional Description
3.19
Timer 2 Capture/Compare Unit
The T2CCU (Timer 2 Capture/Compare Unit) consists of the standard Timer 2 unit and
a Capture/compare unit (CCU). The Capture/Compare Timer (CCT) is part of the CCU.
Control is available in the T2CCU to select individually for each of its 16-bit
capture/compare channel, either the Timer 2 or the Capture/Compare Timer (CCT) as
the time base. Both timers have a resolution of 16 bits.The clock frequency of T2CCU,
fT2CCU, could be set at PCLK frequency or 2 times the PCLK frequency.
The T2CCU can be used for various digital signal generation and event capturing like
pulse generation, pulse width modulation, pulse width measuring etc. Target
applications include various automotive control as well as industrial (frequency
generation, digital-to-analog conversion, process control etc.).
T2CCU Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Option to select individually for each channel, either Timer 2 or Capture/Compare
Timer as time base
Extremely flexible Capture/Compare Timer count rate by cascading with Timer 2
Capture/Compare Timer may be ‘reset’ immediately by triggering overflow event
16-bit resolution
Six compare channels in total
Four capture channels multiplexed with the compare channels, in total
Shadow register for each compare register
– Transfer via software control or on timer overflow.
Compare Mode 0: Compare output signal changes from the inactive level to active
level on compare match. Returns to inactive level on timer overflow.
– Active level can be defined by register bit for channel groups A and B.
– Support of 0% to 100% duty cycle in compare mode 0.
Compare Mode 1: Full control of the software on the compare output signal level, for
the next compare match.
Concurrent Compare Mode with channel 0
Capture Mode 0: Capture on any external event (rising/falling/both edge) at the 4 pins
T2CC0 to T2CC3.
Capture Mode 1: Capture upon writing to the low byte of the corresponding channel
capture register.
Capture mode 0 or 1 can be established independently on the 4 capture channels.
Data Sheet
98
V1.5, 2011-03
XC87xCLM
Functional Description
3.20
Capture/Compare Unit 6
The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which
can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor
control. The CCU6 also supports special control modes for block commutation and
multi-phase machines.
The timer T12 can function in capture and/or compare mode for its three channels. The
timer T13 can work in compare mode only.
The multi-channel control unit generates output patterns, which can be modulated by
T12 and/or T13. The modulation sources can be selected and combined for the signal
modulation.
Timer T12 Features
•
•
•
•
•
•
•
•
•
Three capture/compare channels, each channel can be used either as a capture or
as a compare channel
Supports generation of a three-phase PWM (six outputs, individual signals for
highside and lowside switches)
16-bit resolution, maximum count frequency = peripheral clock frequency
Dead-time control for each channel to avoid short-circuits in the power stage
Concurrent update of the required T12/13 registers
Generation of center-aligned and edge-aligned PWM
Supports single-shot mode
Supports many interrupt request sources
Hysteresis-like control mode
Timer T13 Features
•
•
•
•
•
One independent compare channel with one output
16-bit resolution, maximum count frequency = peripheral clock frequency
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Supports single-shot mode
Additional Features
•
•
•
•
•
•
•
Implements block commutation for Brushless DC-drives
Position detection via Hall-sensor pattern
Automatic rotational speed measurement for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
The block diagram of the CCU6 module is shown in Figure 29.
Data Sheet
99
V1.5, 2011-03
XC87xCLM
Functional Description
module kernel
compare
1
channel 2
1
multichannel
control
compare
channel 3
compare
capture
T13
compare
start
compare
interrupt
control
1
2
3
2
2
trap
control
3
trap input
clock
control
channel 1
deadtime
control
output select
T12
1
Hall input
address
decoder
output select
channel 0
1
CTRAP
CCPOS2
CCPOS1
CCPOS0
CC62
COUT62
CC61
COUT61
CC60
COUT60
COUT63
T13HR
T12HR
input / output control
port control
CCU6_block_diagram
Figure 29
Data Sheet
CCU6 Block Diagram
100
V1.5, 2011-03
XC87xCLM
Functional Description
3.21
Controller Area Network (MultiCAN)
The MultiCAN module contains two Full-CAN nodes operating independently or
exchanging data and remote frames via a gateway function. Transmission and reception
of CAN frames is handled in accordance to CAN specification V2.0 B active. Each CAN
node can receive and transmit standard frames with 11-bit identifiers as well as extended
frames with 29-bit identifiers.
Both CAN nodes share a common set of message objects, where each message object
may be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects may be combined to build
gateways between the CAN nodes or to setup a FIFO buffer.
The message objects are organized in double chained lists, where each CAN node has
it’s own list of message objects. A CAN node stores frames only into message objects
that are allocated to the list of the CAN node. It only transmits messages from objects of
this list. A powerful, command driven list controller performs all list operations.
The bit timings for the CAN nodes are derived from the peripheral clock (fCAN) and are
programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects
each CAN node to a bus transceiver.
MultiCAN Module Kernel
CANSRC[7:0]
Interrupt
Controller
fCAN
Clock
Control
Message
Object
Buffer
32
Objects
Address
Decoder &
Data
control
Linked
List
Control
CAN
Node 1
CAN
Node 0
TXDC1
RXDC1
TXDC0
Port
Control
RXDC0
A[13: 2]
D[31:0]
Access Mediator
CAN Control
MultiCAN_XC8_overview
Figure 30
Overview of the MultiCAN
Features
•
Compliant to ISO 11898.
Data Sheet
101
V1.5, 2011-03
XC87xCLM
Functional Description
•
•
•
•
•
•
•
•
•
•
CAN functionality according to CAN specification V2.0 B active.
Dedicated control registers are provided for each CAN node.
A data transfer rate up to 1 MBaud is supported.
Flexible and powerful message transfer control and error handling capabilities are
implemented.
Advanced CAN bus bit timing analysis and baud rate detection can be performed for
each CAN node via the frame counter.
Full-CAN functionality: A set of 32 message objects can be individually
– allocated (assigned) to any CAN node
– configured as transmit or receive object
– setup to handle frames with 11-bit or 29-bit identifier
– counted or assigned a timestamp via a frame counter
– configured to remote monitoring mode
Advanced Acceptance Filtering:
– Each message object provides an individual acceptance mask to filter incoming
frames.
– A message object can be configured to accept only standard or only extended
frames or to accept both standard and extended frames.
– Message objects can be grouped into 4 priority classes.
– The selection of the message to be transmitted first can be performed on the basis
of frame identifier, IDE bit and RTR bit according to CAN arbitration rules.
Advanced Message Object Functionality:
– Message Objects can be combined to build FIFO message buffers of arbitrary
size, which is only limited by the total number of message objects.
– Message objects can be linked to form a gateway to automatically transfer frames
between 2 different CAN buses. A single gateway can link any two CAN nodes. An
arbitrary number of gateways may be defined.
Advanced Data Management:
– The Message objects are organized in double chained lists.
– List reorganizations may be performed any time, even during full operation of the
CAN nodes.
– A powerful, command driven list controller manages the organization of the list
structure and ensures consistency of the list.
– Message FIFOs are based on the list structure and can easily be scaled in size
during CAN operation.
– Static Allocation Commands offer compatibility with TwinCAN applications, which
are not list based.
Advanced Interrupt Handling:
– Up to 8 interrupt output lines are available. Most interrupt requests can be
individually routed to one of the 8 interrupt output lines.
– Message postprocessing notifications can be flexibly aggregated into a dedicated
register field of 64 notification bits.
Data Sheet
102
V1.5, 2011-03
XC87xCLM
Functional Description
3.22
Analog-to-Digital Converter
The XC87x includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with
eight multiplexed analog input channels. The ADC uses a successive approximation
technique to convert the analog voltage levels from up to eight different sources. The
analog input channels of the ADC are available at AN0 - AN7.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Successive approximation
8-bit or 10-bit resolution
Eight analog channels
Four independent result registers
Result data protection for slow CPU access
(wait-for-read mode)
Single conversion mode
Autoscan functionality
Limit checking for conversion results
Data reduction filter
(accumulation of up to 2 conversion results)
Two independent conversion request sources with programmable priority
Selectable conversion request trigger
Flexible interrupt generation with configurable service nodes
Programmable sample time
Programmable clock divider
Cancel/restart feature for running conversions
Integrated sample and hold circuitry
Compensation of offset errors
Low power modes
3.22.1
ADC Clocking Scheme
A common module clock fADC generates the various clock signals used by the analog and
digital parts of the ADC module:
•
•
•
fADCA is input clock for the analog part.
fADCI is internal clock for the analog part (defines the time base for conversion length
and the sample time). This clock is generated internally in the analog part, based on
the input clock fADCA to generate a correct duty cycle for the analog components.
fADCD is input clock for the digital part.
Figure 31 shows the clocking scheme of the ADC module. The prescaler ratio is
selected by bit field CTC in register GLOBCTR. A prescaling ratio of 32 can be selected
when the maximum performance of the ADC is not required.
Data Sheet
103
V1.5, 2011-03
XC87xCLM
Functional Description
fADC = fPCLK
fADCD
arbiter
registers
interrupts
digital part
fADCA
CTC
÷ 32
÷4
÷3
÷2
MUX
fADCI
clock prescaler
Figure 31
analog
components
analog part
ADC Clocking Scheme
For module clock fADC = 24 MHz, the analog clock fADCI frequency can be selected as
shown in Table 35.
Table 35
fADCI Frequency Selection
Module Clock fADC
CTC
Prescaling Ratio
Analog Clock fADCI
24 MHz
00B
÷2
12 MHz
01B
÷3
8 MHz
10B
÷4
6 MHz
11B (default)
÷ 32
750 kHz
During slow-down mode, fADC may be reduced further, for example, to 12 MHz or 6 MHz.
However, it is important to note that the conversion error could increase due to loss of
charges on the capacitors, if fADC becomes too low during slow-down mode.
3.22.2
ADC Conversion Sequence
The analog-to-digital conversion procedure consists of the following phases:
Data Sheet
104
V1.5, 2011-03
XC87xCLM
Functional Description
•
•
•
•
Synchronization phase (tSYN)
Sample phase (tS)
Conversion phase
Write result phase (tWR)
conversion start
trigger
Source
interrupt
Sample Phase
Channel
interrupt
Result
interrupt
Conversion Phase
fADCI
BUSY Bit
SAMPLE Bit
tSYN
tS
Write Result Phase
tCONV
Figure 32
Data Sheet
tWR
ADC Conversion Timing
105
V1.5, 2011-03
XC87xCLM
Functional Description
3.23
On-Chip Debug Support
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
•
•
•
•
Use the built-in debug functionality of the XC800 Core
Add a minimum of hardware overhead
Provide support for most of the operations by a Monitor Program
Use standard interfaces to communicate with the Host (a Debugger)
Features
•
•
•
•
•
Set breakpoints on instruction address and on address range within the Program
Memory
Set breakpoints on internal RAM address range
Support unlimited software breakpoints in Flash/RAM code region
Process external breaks via JTAG and upon activating a dedicated pin
Step through the program code
The OCDS functional blocks are shown in Figure 33. The Monitor Mode Control (MMC)
block at the center of OCDS system brings together control signals and supports the
overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals.
After processing memory address and control signals from the core, the MMC provides
proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and
a Monitor RAM (for work-data and Monitor-stack).
The OCDS system is accessed through the JTAG1), which is an interface dedicated
exclusively for testing and debugging activities and is not normally used in an
application. The dedicated MBC pin is used for external configuration and debugging
control.
Note: All the debug functionality described here can normally be used only after XC87x
has been started in OCDS mode.
1) The pins of the JTAG port can be assigned to either the primary port (Port 0) or either of the secondary ports
(Ports 1 and 2/Port 5).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
Data Sheet
106
V1.5, 2011-03
XC87xCLM
Functional Description
JTAG Module
Debug
Interface
TMS
TCK
TDI
TDO
JTAG
Memory
Control
Unit
TCK
TDI
TDO
Control
User
Program
Memory
Boot/
Monitor
ROM
User
Internal
RAM
Monitor
RAM
Reset
Monitor Mode Control
MBC
Monitor &
Bootstrap loader
Control line
System
Control
Unit
Suspend
Control
Reset
Clock
- parts of
OCDS
Reset Clock Debug PROG PROG Memory
Interface & IRAM Data Control
Addresses
XC800 Core
OCDS_XC886C-Block_Diagram-UM-v0.2
Figure 33
3.23.1
OCDS Block Diagram
JTAG ID Register
This is a read-only register located inside the JTAG module, and is used to recognize the
device(s) connected to the JTAG interface. Its content is shifted out when
INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is
also true immediately after reset.
The JTAG ID register contents for the XC87x Flash devices are given in Table 36.
Table 36
JTAG ID Summary
Device Type
Device Name
JTAG ID
Flash
XC87x*-16FF
1018 2083H
XC87x*-13FF
1018 3083H
Note: The asterisk (*) above denotes all possible device configurations.
Data Sheet
107
V1.5, 2011-03
XC87xCLM
Functional Description
3.24
Chip Identification Number
The XC87x identity (ID) register is located at Page 1 of address B3H. The value of ID
register is 49H. However, for easy identification of product variants, the Chip
Identification Number, which is an unique number assigned to each product variant, is
available. The differentiation is based on the product, variant type and device step
information.
Two methods are provided to read a device’s chip identification number:
•
•
In-application subroutine, GET_CHIP_INFO
Bootstrap loader (BSL) mode A
Table 37 lists the chip identification numbers of available XC87x Flash device variants.
Table 37
Chip Identification Number
Product Variant
Chip Identification Number
AC-step
Flash Devices
XC878-16FF 5V
4B580063H
XC878M-16FF 5V
4B580023H
XC878CM-16FF 5V
4B580003H
XC878LM-16FF 5V
4B500023H
XC878CLM-16FF 5V
4B500003H
XC878-13FF 5V
4B590463H
XC878M-13FF 5V
4B590423H
XC878CM-13FF 5V
4B590403H
XC878LM-13FF 5V
4B510423H
XC878CLM-13FF 5V
4B510403H
XC878-16FF 3V3
4B180063H
XC878M-16FF 3V3
4B180023H
XC878CM-16FF 3V3
4B180003H
XC878-13FF 3V3
4B190463H
XC878M-13FF 3V3
4B190423H
XC878CM-13FF 3V3
4B190403H
XC874CM-16FV 5V
4B580002H
XC874LM-16FV 5V
4B500022H
XC874-16FV 5V
4B580062H
Data Sheet
108
V1.5, 2011-03
XC87xCLM
Functional Description
Table 37
Chip Identification Number (cont’d)
Product Variant
Chip Identification Number
AC-step
XC874CM-13FV 5V
4B590402H
XC874LM-13FV 5V
4B510422H
XC874-13FV 5V
4B590462H
Data Sheet
109
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4
Electrical Parameters
Chapter 4 provides the characteristics of the electrical parameters which are
implementation-specific for the XC87x.
4.1
General Parameters
The general parameters are described here to aid the users in interpreting the
parameters mainly in Section 4.2 and Section 4.3.
4.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XC87x
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
•
•
CC
These parameters indicate Controller Characteristics, which are distinctive features
of the XC87x and must be regarded for a system design.
SR
These parameters indicate System Requirements, which must be provided by the
microcontroller system in which the XC87x is designed in.
Data Sheet
108
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.1.2
Absolute Maximum Rating
Maximum ratings are the extreme limits to which the XC87x can be subjected to without
permanent damage.
Table 38
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
TA
Storage temperature
TST
Junction temperature
TJ
Voltage on power supply pin with VDDP
-40
125
°C
-65
150
°C
-40
140
°C
-0.5
6
V
Voltage on any pin with respect
to VSS
VIN
-0.5
VDDP +
0.5 or
max. 6
V
Input current on any pin during
overload condition
IIN
-10
10
mA
–
50
mA
Ambient temperature
under bias
under bias
respect to VSS
Absolute sum of all input currents Σ|IIN|
during overload condition
Whatever is
lower
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pin with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
109
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.1.3
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the XC87x. All parameters mentioned in the following table refer to these
operating conditions, unless otherwise noted.
Table 39
Operating Condition Parameters
Parameter
Digital power supply voltage
Digital power supply voltage
Digital ground voltage
CPU Clock Frequency1)
Ambient temperature
Symbol
VDDP
VDDP
VSS
fCCLK
TA
Limit Values
min.
max.
Unit Notes/
Conditions
4.5
5.5
V
5V Device
3.0
3.6
V
3.3V Device
0
V
26.672)
MHz
-40
85
°C
SAF-XC878/874...
-40
105
°C
SAX-XC878...
-40
125
°C
SAK-XC878/874...
1) fCCLK is the input frequency to the XC800 core. Please refer to Figure 22 for detailed description.
2)Default setting of fCCLK upon reset is 24 MHz.
Data Sheet
110
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.2
DC Parameters
The electrical characteristics of the DC Parameters are detailed in this section.
4.2.1
Input/Output Characteristics
Table 40 provides the characteristics of the input/output pins of the XC87x.
Table 40
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
Unit Test Conditions
max.
VDDP = 5 V Range
IOL = 9 mA (DS = 0)1)
IOL = 12 mA (DS = 1)2)
IOH = -20 mA (DS = 0)1)
IOH = -25 mA (DS = 1)2)
Output low voltage
VOL
CC –
0.6
V
Output high voltage
VOH
CC 2.4
–
V
Input low voltage
VIL
VIH
HYS
VILX
SR -0.3
0.8
V
CMOS Mode
SR 2.2
VDDP
V
CMOS Mode
CC 0.35
–
V
CMOS Mode3)7)
SR -0.3
0.8
V
Input high voltage at
XTAL1
VIHX
SR 3.4
VDDP
V
Pull-up current
IPU
SR –
-20
µA
–
µA
10
µA
66
–
µA
Input high voltage
Input Hysteresis
Input low voltage at
XTAL1
-88
Pull-down current
IPD
SR –
VIH,min
VIL,max
VIL,max
VIH,min
0 < VIN < VDDP,
TA ≤ 105°C4)
Input leakage current
IOZ1
CC -1
1
µA
Overload current on
any pin
IOV
SR -5
5
mA
Absolute sum of
overload currents
Σ|IOV|
SR –
25
mA
5)
Voltage on any pin
during VDDP power off
VPO
SR –
0.3
V
6)
Data Sheet
111
V1.5, 2011-03
XC87xCLM
Electrical Parameters
Table 40
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values
min.
Unit Test Conditions
max.
Maximum current per
pin (excluding VDDP
and VSS)
IM SR SR –
25
mA
Maximum current for
all pins (excluding
VDDP and VSS)
Σ|IM|
SR –
150
mA
Maximum current into
IMVDDP SR –
200
mA
5)
IMVSS
SR –
200
mA
5)
Output low voltage
VOL
CC –
0.5
V
Output high voltage
VOH
CC 2.2
–
V
IOL = 6 mA (DS = 0)1)
IOL = 8 mA (DS = 1)2)
IOH = -5 mA (DS = 0)1)
IOH = -7 mA (DS = 1)2)
Input low voltage
VIL
VIH
HYS
VILX
SR -0.3
0.7
V
CMOS Mode
SR 2
VDDP
V
CMOS Mode
CC 0.28
–
V
CMOS Mode3)7)
SR -0.3
0.7
V
Input high voltage at
XTAL1
VIHX
SR 2.3
VDDP
V
Pull-up current
IPU
SR –
-7
µA
–
µA
12
µA
60
–
µA
VDDP
Maximum current out
of VSS
VDDP = 3.3 V Range
Input high voltage
Input Hysteresis
Input low voltage at
XTAL1
-35
Pull-down current
IPD
SR –
Input leakage current
IOZ1
CC -1
1
µA
Overload current on
any pin
IOV
SR -5
5
mA
Absolute sum of
overload currents
Σ|IOV|
SR –
25
mA
Data Sheet
112
VIH,min
VIL,max
VIL,max
VIH,min
0 < VIN < VDDP,
TA ≤ 105°C4)
5)
V1.5, 2011-03
XC87xCLM
Electrical Parameters
Table 40
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values
min.
Voltage on any pin
during VDDP power off
VPO
Maximum current per
pin (excluding VDDP
and VSS)
max.
6)
0.3
V
IM SR SR –
8
mA
Maximum current for
all pins (excluding
VDDP and VSS)
Σ|IM|
SR –
150
mA
Maximum current into
IMVDDP SR –
200
mA
5)
IMVSS
200
mA
5)
VDDP
Maximum current out
of VSS
SR –
Unit Test Conditions
SR –
1) DS = 0 refers to the pin having a weak drive strength which is programmable via Px_DS register.
2) DS = 1 refers to the pin having a strong drive strength which is programmable via Px_DS register.
3) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta
stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses
switching due to external system noise.
4) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and
RESET pin have internal pull devices and are not included in the input leakage current characteristic.
5) Not subjected to production test, verified by design/characterization.
6) Not subjected to production test, verified by design/characterization. However, for applications with strict low
power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin
when VDDP is powered off.
7) P0.1 has a minimum input hysteresis of 0.25V.
Data Sheet
113
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.2.2
Supply Threshold Characteristics
Table 41 provides the characteristics of the supply threshold in the XC87x.
5.0V
VDDPPW
VDDP
2.5V
V DDCBO
VDDC
VDDCRDR
VDDCPOR
Figure 34
Supply Threshold Parameters
Table 41
Supply Threshold Parameters (Operating Conditions apply)
Parameters
Symbol
1)
VDDC brownout voltage
RAM data retention voltage
VDDP prewarning voltage2)
Power-on reset voltage1)3)
Limit Values
VDDCBO
VDDCRDR
VDDPPW
VDDCPOR
Unit
min.
typ.
max.
CC
1.7
1.9
2.2
V
CC
1.2
–
–
V
CC
3.8
4.2
4.5
V
CC
1.7
1.9
2.2
V
1) Detection is enabled in both active and power-down mode.
2) Detection is enabled for 5.0V power supply variant.
Detection is disabled for 3.3V power supply variant.
3) The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage.
Data Sheet
114
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.2.3
ADC Characteristics
The values in the table below are given for an analog power supply between 4.5 V to
5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case,
the analog parameters may show a reduced performance. All ground pins (VSS) must be
externally connected to one single star point in the system. The voltage difference
between the ground pins must not exceed 200mV.
Table 42
ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)
Parameter
Symbol
Limit Values
min.
typ .
max.
Unit Test Conditions/
Remarks
Analog reference
voltage
VAREF
SR VAGND VDDP
+1
VDDP
V
1)
Analog reference
ground
VAGND
SR VSS 0.05
VAREF V
1)
Analog input
voltage range
VAIN
SR VAGND –
ADC clocks
fADC
fADCI
Sample time
Conversion time
Differential
Nonlinearity
tS
VSS
+ 0.05
-1
VAREF V
–
24
–
MHz module clock1)
–
–
142)
MHz internal analog clock1)
See Figure 31
CC (2 + INPCR0.STC) × µs
1)
tADCI
1)
tC
CC See Section 4.2.3.1 µs
|EADNL| CC –
–
1.5
LSB 10-bit conversion
Integral
Nonlinearity
|EAINL|
CC –
–
2
LSB 10-bit conversion
Offset
|EAOFF| CC –
|EAGAIN| CC –
CAREFSW CC –
–
3
LSB 10-bit conversion
–
2.5
LSB 10-bit conversion
10
14
pF
1)3)
CAINSW
4
5
pF
1)4)
Gain
Switched
capacitance at the
reference voltage
input
Switched
capacitance at the
analog voltage
inputs
Data Sheet
CC –
115
V1.5, 2011-03
XC87xCLM
Electrical Parameters
Table 42
Parameter
ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)
Symbol
Limit Values
min.
typ .
max.
Unit Test Conditions/
Remarks
Input resistance of RAREF
the reference input
CC –
1
2
kΩ
1)
Input resistance of RAIN
the selected analog
channel
CC –
1
3
kΩ
1)
1) Not subjected to production test, verified by design/characterization.
2) This value includes the maximum oscillator deviation.
3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this, smaller capacitances are successively switched to the reference voltage.
4) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to
the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2.
Data Sheet
116
V1.5, 2011-03
XC87xCLM
Electrical Parameters
Analog Input Circuitry
REXT
VAIN
RAIN, On
ANx
CEXT
C AINSW
VAGNDx
Reference Voltage Input Circuitry
R AREF, On
VAREFx
VAREF
C AREFSW
VAGNDx
Figure 35
4.2.3.1
ADC Input Circuits
ADC Conversion Timing
Conversion time, tC = tADC × ( 1 + r × (3 + n + STC) ) , where
r = CTC + 2 for CTC = 00B, 01B or 10B,
r = 32 for CTC = 11B,
CTC = Conversion Time Control (GLOBCTR.CTC),
STC = Sample Time Control (INPCR0.STC),
n = 8 or 10 (for 8-bit and 10-bit conversion respectively),
tADC = 1 / fADC
Data Sheet
117
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.2.4
Power Supply Current
Table 43, Table 44, Table 45 and Table 46 provide the characteristics of the power
supply current in the XC87x.
Table 43
Power Supply Current Parameters (Operating Conditions apply;
VDDP = 5V range)
Parameter
Symbol
Limit Values
typ.1)
Unit Test Conditions
max.2)
VDDP = 5V Range
Active Mode
Idle Mode
IDDP
IDDP
Active Mode with slowdown enabled
IDDP
Idle Mode with slowdown enabled
IDDP
37.5
45
mA
3)
SAF and SAX variants
40.5
48
mA
3)
SAK variant
29.2
35
mA
4)
SAF and SAX variants
32.2
38
mA
4)
SAK variant
10
15
mA
5)
SAF and SAX variants
13
18
mA
5)
SAK variant
9.2
14
mA
6)
SAF and SAX variants
mA
6)
SAK variant
12.2
17
1) The typical IDDP values are based on preliminary measurements and are to be used as reference only. These
values are periodically measured at TA = + 25 °C and VDDP = 5.0 V.
2) The maximum IDDP values are measured under worst case conditions (TA = + 105 °C and VDDP = 5.5 V).
3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz with onchip oscillator of 4 MHz, RESET = VDDP; all other pins are disconnected, no load on ports.
4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
enabled and running at 24 MHz, RESET = VDDP; all other pins are disconnected, no load on ports.
5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
running at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP; all other pins are disconnected, no
load on ports.
6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
clock to all peripherals enabled and running at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP;
all other pins are disconnected, no load on ports.
Data Sheet
118
V1.5, 2011-03
XC87xCLM
Electrical Parameters
Table 44
Power Down Current1)(Operating Conditions apply; VDDP = 5V range)
Parameter
Symbol
Limit Values
typ.2)
Unit Test Conditions
max.3)
VDDP = 5V Range
Power-Down Mode
IPDP
20
80
µA
-
250
µA
TA = + 25 °C4)5)
TA = + 85 °C5)6)
1) The table is only applicable to SAF and SAX variants. SAK variant does not support power-down mode
2) The typical IPDP values are based on preliminary measurements and are to be used as reference only. These
values are measured at VDDP = 5.0 V.
3) The maximum IPDP values are measured at VDDP = 5.5 V.
4) IPDP has a maximum value of 450 µA at TA = + 105 °C.
5) IPDP is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be
input with either internal pull devices enabled or driven externally to ensure no floating inputs.
6) Not subjected to production test, verified by design/characterization.
Data Sheet
119
V1.5, 2011-03
XC87xCLM
Electrical Parameters
Table 45
Power Supply Current Parameters1) (Operating Conditions apply;
VDDP = 3.3V range)
Parameter
Symbol
Limit Values
typ.2)
max.3)
Unit Test
Conditions
VDDP = 3.3V Range
Active Mode
Idle Mode
Active Mode with slow-down
enabled
Idle Mode with slow-down enabled
IDDP
IDDP
IDDP
35.4
43
mA
4)
27.6
33
mA
5)
8.6
13
mA
6)
IDDP
8
12
mA
7)
1) The table is only applicable to SAF and SAX variants.
2) The typical IDDP values are based on preliminary measurements and are to be used as reference only. These
values are periodically measured at TA = + 25 °C and VDDP = 3.3 V.
3) The maximum IDDP values are measured under worst case conditions (TA = + 105 °C and VDDP = 3.6 V).
4) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz with onchip oscillator of 4 MHz, RESET = VDDP; all other pins are disconnected, no load on ports.
5) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
enabled and running at 24 MHz, RESET = VDDP; all other pins are disconnected, no load on ports.
6) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running
at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP; all other pins are disconnected, no load on
ports.
7) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
clock to all peripherals enabled and running at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP;
all other pins are disconnected, no load on ports.
Data Sheet
120
V1.5, 2011-03
XC87xCLM
Electrical Parameters
Table 46
Power Down Current1)(Operating Conditions apply; VDDP = 3.3V
range)
Parameter
Symbol
Limit Values
typ.2)
Unit Test Conditions
max.3)
VDDP = 3.3V Range
Power-Down Mode
IPDP
20
80
µA
-
250
µA
TA = + 25 °C4)5)
TA = + 85 °C5)6)
1) The table is only applicable to SAF and SAX variants.
2) The typical IPDP values are based on preliminary measurements and are to be used as reference only. These
values are measured at VDDP = 3.3 V.
3) The maximum IPDP values are measured at VDDP = 3.6 V.
4) IPDP has a maximum value of 450 µA at TA = + 105 °C.
5) IPDP is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be
input with either internal pull devices enabled or driven externally to ensure no floating inputs.
6) Not subjected to production test, verified by design/characterization.
Data Sheet
121
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.3
AC Parameters
The electrical characteristics of the AC Parameters are detailed in this section.
4.3.1
Testing Waveforms
The testing waveforms for rise/fall time, output delay and output high impedance are
shown in Figure 36, Figure 37 and Figure 38.
VDDP
90%
10%
10%
VSS
Figure 36
90%
tF
tR
Rise/Fall Time Parameters
VDDP
VDDE / 2
Test Points
VDDE / 2
VSS
Figure 37
Testing Waveform, Output Delay
VLoad + 0.1 V
VLoad - 0.1 V
Figure 38
Data Sheet
Timing
Reference
Points
VOH - 0.1 V
VOL - 0.1 V
Testing Waveform, Output High Impedance
122
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.3.2
Output Rise/Fall Times
Table 47 provides the characteristics of the output rise/fall times in the XC87x.
Table 47
Output Rise/Fall Times Parameters (Operating Conditions apply)
Parameter
Symbol
Limit
Values
Unit Test Conditions
min. max.
VDDP = 5V Range
Rise/fall times
t R , tF
–
10
ns
20 pF.1) 2)3)
t R , tF
–
10
ns
20 pF.1) 2)4)
VDDP = 3.3V Range
Rise/fall times
1) Rise/Fall time measurements are taken with 10% - 90% of pad supply.
2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
3) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF.
4) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.225 ns/pF.
VDDP
90%
90%
VSS
10%
10%
tF
tR
Figure 39
Data Sheet
Rise/Fall Times Parameters
123
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.3.3
Power-on Reset and PLL Timing
Table 48 provides the characteristics of the power-on reset and PLL timing in the XC87x.
Table 48
Power-On Reset and PLL Timing (Operating Conditions apply)
Parameter
Symbol
Limit Values
min. typ.
On-Chip Oscillator
start-up time
tOSCST
tLOCK
PLL accumulated jitter DP
PLL lock-in in time
Unit Test Conditions
max.
CC –
–
500
ns
1)
CC –
–
200
µs
1)
–
–
1.8
ns
1)2)
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
2) PLL lock at 144 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 72 and P = 1.
VDDP
VDDC
VPAD
tOSCST
OSC
PLL unlock
PLL
PLL lock
t LOCK
Pads
3)As Programmed
2)Pull/Input
1)
Pad state undefined
I)until EVR is stable
Figure 40
Data Sheet
II)until PLL is locked
III) Reset is released
and start of program
Power-on Reset Timing
124
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.3.4
On-Chip Oscillator Characteristics
Table 49 provides the characteristics of the on-chip oscillator in the XC87x.
Table 49
On-chip Oscillator Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Conditions
min. typ. max.
Nominal frequency
fNOM CC
Long term frequency ∆fLT
deviation
CC
Short term frequency ∆fST CC
deviation
3.88 4
4.12
MHz under nominal
conditions1) after
IFX-backend trimming
-5
–
5
%
with respect to fNOM, over
lifetime and temperature
(-40°C to 105°C), for one
given device after
trimming
-1.0
–
1.0
%
within one LIN message
(<10 ms .... 100 ms)
1) Nominal condition: VDDC = 2.5 V, TA = + 25°C.
Data Sheet
125
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.3.5
External Data Memory Characteristics
Table 50 shows the timing of the external data memory read cycle.
Table 50
External Data Memory Read Timing1) (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
t1
Address valid to RD
t2
RD to valid data in
t3
Address to valid data in t4
Data hold after RD
t5
RD pulse width
Unit
Test
Conditions
Max.
CC 2*fCCLK - 17
-
ns
2)
CC fCCLK - 12
-
ns
2)
SR -
1.5*fCCLK - 27 ns
2)
SR -
3*fCCLK - 7
ns
2)
ns
2)
SR 0.5*fCCLK -17 -
1) External Bus Interface is not available in XC874.
2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
Addresses
DATA ADDRESS
t1
RD
t2
t3
D[7:0]
t5
VALID
t4
Figure 41
Data Sheet
External Data Memory Read Cycle
126
V1.5, 2011-03
XC87xCLM
Electrical Parameters
Table 51 shows the timing of the external data memory write cycle.
Table 51
External Data Memory Write Timing1) (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
t1
Address valid to WR
t2
Data valid to WR transition t3
Data setup before WR
t4
Data hold after WR
t5
WR pulse width
Unit
Test
Conditions
Max.
CC fCCLK - 10
-
ns
2)
CC 2*fCCLK - 7
-
ns
2)
SR fCCLK - 5
-
ns
2)
SR 9*fCCLK - 13
-
ns
2)
SR 6*fCCLK - 3
-
ns
2)
1) External Bus Interface is not available in XC874.
2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
Addresses
DATA ADDRESS
t2
t1
WR
t3
t5
D[7:0]
VALID
t4
Figure 42
Data Sheet
External Data Memory Write Cycle
127
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.3.6
External Clock Drive XTAL1
Table 52 shows the parameters that define the external clock supply for XC87x. These
timing parameters are based on the direct XTAL1 drive of clock input signals. They are
not applicable if an external crystal or ceramic resonator is considered.
Table 52
External Clock Drive Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
tosc
t1
t2
t3
t4
Oscillator period
High time
Low time
Rise time
Fall time
Unit
Test Conditions
Max.
SR 50
500
ns
1)2)
SR 15
-
ns
2)3)
SR 15
-
ns
2)3)
SR -
10
ns
2)3)
SR -
10
ns
2)3)
1) The clock input signals with 45-55% duty cycle are used.
2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
3) The clock input signal must reach the defined levels VILX and VIHX.
t1
t3
t4
VIHX
0.5 V DDC
VILX
t2
tOSC
Figure 43
Data Sheet
External Clock Drive XTAL1
128
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.3.7
JTAG Timing
Table 53 provides the characteristics of the JTAG timing in the XC87x.
Table 53
TCK Clock Timing (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
tTCK
t1
t2
t3
t4
Unit
Test Conditions
max
SR
50
-
ns
1)
SR
20
-
ns
1)
SR
20
-
ns
1)
SR
-
4
ns
1)
SR
-
4
ns
1)
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
0.9 V DDP
0.5 V DDP
TCK
0.1 V DDP
t1
t TCK
t2
t4
t3
Figure 44
TCK Clock Timing
Table 54
JTAG Timing (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min
Unit
Test Conditions
max
TMS setup to TCK
t1
SR
8
-
ns
1)
TMS hold to TCK
t2
SR
0
-
ns
1)
TDI setup to TCK
t1
SR
8
-
ns
1)
TDI hold to TCK
t2
SR
4
-
ns
1)
TDO valid output from TCK
t3
CC
-
24
ns
5V Device1)
-
31
ns
3.3V Device1)
Data Sheet
129
V1.5, 2011-03
XC87xCLM
Electrical Parameters
Table 54
JTAG Timing (Operating Conditions apply; CL = 50 pF) (cont’d)
Parameter
Symbol
Limits
min
TDO high impedance to valid t4
output from TCK
CC
t5
CC
TDO valid output to high
impedance from TCK
Unit
Test Conditions
max
-
18
ns
5V Device1)
-
21
ns
3.3V Device1)
-
21
ns
5V Device1)
-
20
ns
3.3V Device1)
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
TCK
t1
t2
t1
t2
TMS
TDI
t4
t3
t5
TDO
Figure 45
Data Sheet
JTAG Timing
130
V1.5, 2011-03
XC87xCLM
Electrical Parameters
4.3.8
SSC Master Mode Timing
Table 55 provides the characteristics of the SSC timing in the XC87x.
Table 55
SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limit Values
min.
max.
Unit
Test Conditions
CC
2*TSSC
–
ns
1)2)
MTSR delay from SCLK
t0
t1
CC
0
5
ns
2)
MRST setup to SCLK
t2
SR
13
–
ns
2)
MRST hold from SCLK
t3
SR
0
–
ns
2)
SCLK clock period
1) TSSCmin = TCPU = 1/fCPU. When fCPU = 24 MHz, t0 = 83.3ns. TCPU is the CPU clock period.
2) 1Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
t0
SCLK1)
t1
t1
MTSR1)
t2
t3
Data
valid
MRST1)
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC_Tmg1
Figure 46
Data Sheet
SSC Master Mode Timing
131
V1.5, 2011-03
XC87xCLM
Package and Quality Declaration
5
Package and Quality Declaration
Chapter 5 provides the information of the XC87x package and reliability section.
5.1
Package Parameters
Table 56 provides the thermal characteristics of the package used in XC878 and XC874.
Table 56
Thermal Characteristics of the Packages
Parameter
Symbol
Limit Values
Min.
Unit
Notes
Max.
PG-LQFP-64-4 (XC878)
Thermal resistance junction RTJC
case1)
CC -
13.8
K/W
-
Thermal resistance junction RTJL
lead1)
CC -
34.6
K/W
-
Thermal resistance junction RTJC
case1)
CC -
16.6
K/W
-
Thermal resistance junction RTJL
lead1)
CC -
30.7
K/W
-
PG-VQFN-48-22 (XC874)
1) The thermal resistances between the case and the ambient (RTCA) , the lead and the ambient (RTLA) are to be
combined with the thermal resistances between the junction and the case (RTJC), the junction and the lead
(RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient
(RTJA). The thermal resistances between the case and the ambient (RTCA), the lead and the ambient (RTLA)
depend on the external system (PCB, case) characteristics, and are under user responsibility.
The junction temperature can be calculated using the following equation: TJ=TA+RTJA × PD, where the RTJA is
the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA
can be obtained from the upper four partial thermal resistances, by
a) simply adding only the two thermal resistances (junction lead and lead ambient), or
b) by taking all four resistances into account, depending on the precision needed.
Data Sheet
133
V1.5, 2011-03
XC87xCLM
Package and Quality Declaration
5.2
Package Outline
Figure 47 shows the package outlines of the XC878.
Figure 47
Data Sheet
PG-LQFP-64-4 Package Outline
134
V1.5, 2011-03
XC87xCLM
Package and Quality Declaration
Figure 48 shows the package outlines of the XC874.
Figure 48
Data Sheet
PG-VQFN-48-22 Package Outline
135
V1.5, 2011-03
XC87xCLM
Package and Quality Declaration
5.3
Quality Declaration
Table 57 shows the characteristics of the quality parameters in the XC87x.
Table 57
Quality Parameters
Parameter
Symbol Limit Values
Unit
Notes
Min.
Max.
-
15000
hours
TJ = 110°C
-
2000
hours
TJ = -40°C
-
120
hours
TJ = 140°C
-
960
hours
TJ = 135°C
-
7800
hours
TJ = 91°C
-
2400
hours
TJ = 38°C
-
720
hours
TJ = -25°C
ESD susceptibility
VHBM
according to Human Body
Model (HBM)
-
2000
V
Conforming to
EIA/JESD22A114-B
VCDM
-
750
V
Conforming to
JESD22-C101-C
Operation Lifetime when
the device is used at the
two stated TJ1)
tOP1
Operation Lifetime when
the device is used at the
five stated TJ1)
tOP2
ESD susceptibility
according to Charged
Device Model (CDM) pins
1) This lifetime refers only to the time when device is powered-on.
Data Sheet
136
V1.5, 2011-03
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG