19-3386; Rev 0; 8/04 Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier Features ♦ SFP Reference Design Available ♦ Low 115mW Power Consumption ♦ 16-Pin QFN Package with 3mm x 3mm Footprint ♦ 70ps Rise and Fall Time ♦ Loss-of-Signal with Programmable Threshold ♦ RSSI Interface (with MAX3744/MAX3724 TIA) ♦ Output Disable ♦ Polarity Select ♦ 8.4psP-P Deterministic Jitter (3.2Gbps) ♦ Improved EMI Performance The combination of the MAX3746 and the MAX3744/ MAX3724 allows for the implementation of all the smallform-factor SFF-8472 digital diagnostic specifications using a standard 4-pin TO-46 header. The MAX3746 is pin-for-pin compatible with the MAX3748A limiting amplifier and consumes 30% less power. The MAX3746 is packaged in a 3mm x 3mm, 16-pin QFN package. ♦ Selectable CML Output levels ♦ Pin Compatible with MAX3748A Ordering Information PART TEMP RANGE PIN-PACKAGE PKG CODE MAX3746ETE -40°C to +85°C 16 QFN T1633F-3 Applications Gigabit Ethernet SFF/SFP Transceiver Modules Fibre-Channel SFF/SFP Transceiver Modules Pin Configuration appears at end of data sheet. Multirate OC-12 to OC48-FEC SFF/SFP Transceiver Modules Typical Operating Circuits continued at end of data sheet. Typical Operating Circuits SFP OPTICAL RECEIVER HOST BOARD SUPPLY FILTER HOST FILTER 4-PIN TO HEADER VCC_RX OUTPOL VCC 0.1µF IN+ MAX3744 TIA OUT+ 50Ω SERDES 0.1µF OUT- IN- 50Ω MAX3746 RSSI GND TH DISABLE LOS 4.7kΩ TO 10kΩ RTH = 14kΩ DS1859 3-INPUT DIAGNOSTIC MONITOR 2.97V TO 3.6V LOS R1 3kΩ C1 0.1µF ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3746 General Description The MAX3746 multirate limiting amplifier functions as a data quantizer for SONET, Fibre-Channel, and Gigabit Ethernet optical receivers. The amplifier accepts a wide range of input voltages and provides selectable-level, current-mode logic (CML) output voltages with controlled edge speeds. A received-signal-strength indicator (RSSI) is available when the MAX3746 is DC-coupled to the MAX3744/MAX3724 SFP transimpedance amplifier (TIA). A receiver consisting of the MAX3744/MAX3724 and the MAX3746 can provide up to 19dB RSSI dynamic range. Additional features include a programmable loss-of-signal (LOS) detect, an optional disable function (DISABLE), and an output-signal polarity reversal (OUTPOL). Output disable can be used to implement squelch. MAX3746 Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Power-Supply Voltage (VCC) .................................-0.5V to +4.5V Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V) Voltage at DISABLE, OUTPOL, RSSI, LOS, TH ...................................................-0.5V to (VCC + 0.5V) Current into LOS.....................................................1mA to +9mA Differential Input Voltage (IN+ - IN-) .....................................2.5V Continuous Current at CML Outputs (OUT+, OUT-) ................................................-25mA to +25mA Continuous Power Dissipation (TA = + 70°C) 16-Pin QFN (derate 17.7mW above +70°C) .....................1.4W Operating Junction Temperature Range (TJ) ....-55°C to +150°C Storage Ambient Temperature Range (Ts) .......-55°C to +150°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +2.97V to +3.63V, CML output load is 50Ω to VCC, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise specified. The data input transition time is controlled by 4th-order Bessel filter with f-3dB = 0.75 x 2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB = 0.75 x 3.2GHz for a data rate of 3.2Gbps.) PARAMETER Single-Ended Input Resistance SYMBOL RIN CONDITIONS Single ended to VCC MIN TYP MAX UNITS 42 50 58 Ω se S11 Single ended, f < 3GHz, DUT is powered on 14 diff S11 Differential, f < 3GHz, DUT is powered on 15 Input Sensitivity VIN-MIN (Note 1) Input Overload VIN-MAX (Note 1) Input Return Loss Single-Ended Output Resistance Output Return Loss ROUT diff S22 CML Differential Output Voltage Differential Output Signal when Disabled Deterministic Jitter (Note 3) 2 Single ended to VCC 2 4 50 58 1200 42 Differential, f < 3GHz, DUT is powered on 20 Ω dB 4mVP-P < VIN < 1200mVP-P, OUTPOL connected to VCC or GND 600 800 1000 4mVP-P < VIN < 1200mVP-P, OUTPOL open or connected to 30kΩ 400 500 600 mVP-P 10 K28.5 pattern at 3.2Gbps (Note 2) 8.4 K28.5 pattern at 3.2Gbps at TA = +100°C 10.2 223 - 1 PRBS equivalent at 2.7Gbps (Note 2) 11.6 223 - 1 PRBS equivalent pattern at 2.7Gbps at TA = +100°C 13.1 K28.5 pattern at 2.1Gbps mVP-P mVP-P Outputs AC-coupled, VIN-MAX applied to input (Note 2) DJ dB 8 K28.5 pattern at 2.1Gbps at TA = +100°C 9.7 223 - 1 PRBS equivalent pattern at 622Mbps (Note 2) 42.5 223 - 1 PRBS equivalent pattern at 622Mbps at TA = +100°C 47.8 _______________________________________________________________________________________ mVP-P 18 23 20 69 psP-P Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier (VCC = +2.97V to +3.63V, CML output load is 50Ω to VCC, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise specified. The data input transition time is controlled by 4th-order Bessel filter with f-3dB = 0.75 x 2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB = 0.75 x 3.2GHz for a data rate of 3.2Gbps.) TYP MAX UNITS Random Jitter PARAMETER SYMBOL Input = 4mVP-P (Notes 2, 4) CONDITIONS MIN 3 7 psRMS Data Output Transition Time 4mVP-P < VINP-P < 1200mVP-P, 20% to 80% (Note 2) 70 114 ps Input-ReferredNoise (Note 2) 150 µVRMS Low-Frequency Cutoff Power-Supply Current Power-Supply Noise Rejection 20 ICC PSNR kHz Includes the CML output current; OUTPOL connected to VCC or GND 35 41.5 Includes the CML output current; OUTPOL open or connected to 30kΩ to GND 29 35 Excludes the CML output current and the CM_RSSI circuitry; OUTPOL connected to VCC or GND (Note 5) 20 25 f < 2MHz 40 dB 2.2 dB mA LOSS-OF-SIGNAL (Notes 2, 6) LOS Hysteresis 10 log (VDEASSERT / VASSERT) 1.25 LOS Assert/Deassert Time (Note 7) 2.3 Low LOS Assert Level RTH = 2kΩ 2.6 Low LOS Deassert Level RTH = 2kΩ Medium LOS Assert Level RTH = 14kΩ Medium LOS Deassert Level RTH = 14kΩ High LOS Assert Level RTH = 25kΩ High LOS Deassert Level RTH = 25kΩ 19.6 36 50 µs 4 6.4 mVP-P 6 9.6 mVP-P 28 31.8 mVP-P 42 54.7 mVP-P 50 54.3 mVP-P 84 114 mVP-P CM_RSSI SPECIFICATION RSSI Current Gain ARSSI IRSSI / ICM_RSSI (Note 8) 0.031 VCM to IRSSI 3dB Bandwidth 40 Input-Referred RSSI Current Stability IRSSI ARSSI RSSI Output Compliance Voltage VRSSI Input < 6.6mA, 0V ≤ VRSSI ≤ 2.5V (Note 9) kHz -40 +36 µA 0 2.0 V TTL/CMOS I/O LOS Output High Voltage VOH RLOS = 4.7kΩ to 10kΩ to Vcc_host (3V) LOS Output Low Voltage VOL RLOS = 4.7kΩ to 10kΩ to Vcc_host (3.6V) 2.4 V 0.4 V _______________________________________________________________________________________ 3 MAX3746 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.97V to +3.63V, CML output load is 50Ω to VCC, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise specified. The data input transition time is controlled by 4th-order Bessel filter with f-3dB = 0.75 x 2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB = 0.75 x 3.2GHz for a data rate of 3.2Gbps.) PARAMETER SYMBOL DISABLE Input High VIH DISABLE Input Low VIL Note 6: Note 7: Note 8: Note 9: CONDITIONS MIN TYP MAX 2.0 DISABLE Input Current Note 1: Note 2: Note 3: Note 4: Note 5: UNITS V RLOS = 4.7kΩ to 10kΩ to Vcc_host 0.8 V 10 µA Between sensitivity and overload, all AC specifications are met. Guaranteed by design and characterization. The deterministic jitter caused by the filter is not included in the DJ generation specification. Random jitter was measured without using a filter at the input. The supply current measurement excludes the CML output currents by connecting the CML outputs to a separate VCC. (See Figure 1.) Hysteresis is calculated as 10 log (VDEASSERT / VASSERT). Unless otherwise specified, the data rate for all LOS detect specifications varies from 622Mbps up to 3.2Gbps, and the patterns are 1010 or 223 - 1 PRBS. The signal is switched between two amplitudes, Signal_On and Signal _Off as shown in Figure 2. ICM_RSSI is the input common-mode current. IRSSI is the current at the RSSI output. Stability is defined as the variation over temperature and power supply with respect to the typical gain of the part. Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) 70 60 50 CML OUTPUTS INCLUDED 40 30 20 10 CML OUTPUTS NOT INCLUDED 700 600 500 400 300 200 -40 -30-20 -10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) 10 9 8 7 6 5 4 3 2 100 1 0 0 4 OUTPOL = VCC 800 RANDOM JITTER (psRMS) 80 900 MAX3746 toc02 OUTPOL = VCC DIFFERENTIAL OUTPUT (mVP-P) 90 MAX3746 toc01 100 RANDOM JITTER vs. TEMPERATURE (INPUT LEVEL 10mVP-P) TRANSFER FUNCTION MAX3746 toc03 SUPPLY CURRENT vs. TEMPERATURE CURRENT (mA) MAX3746 Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier 0 1 2 3 4 DIFFERENTIAL INPUT (mVP-P) 5 6 0 -40 -30-20 -10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) _______________________________________________________________________________________ Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier BIT-ERROR RATIO (10-12) 8 1000 7 6 5 4 3 2 800 600 400 24 200 0 5 10 15 20 25 30 35 40 20 18 16 14 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 DIFFERENTIAL INPUT (mVP-P) INPUT VOLTAGE (mVP-P) COMMON-MODE VOLTAGE (VCC + X) OUTPUT EYE DIAGRAM (MINIMUM INPUT) OUTPUT EYE DIAGRAM (MAXIMUM INPUT) OUTPUT EYE DIAGRAM (MINIMUM INPUT) MAX3746 toc07 MAX3746 toc08 3.2Gbps, K28.5, 4mVP-P MAX3746 toc09 2.7Gbps, 223 - 1 PRBS, 4mVP-P 100mV/div 100mV/div 100mV/div 3.2Gbps, K28.5, 1200mVP-P 50ps/div 50ps/div OUTPUT EYE DIAGRAM (MAXIMUM INPUT) OUTPUT EYE DIAGRAM AT +100°C (MINIMUM INPUT) MAX3746 toc10 ASSERT/DEASSERT LEVELS vs. RTH MAX3746 toc11 120 LOS ASSERT/DEASSERT (mVP-P) 2.7Gbps, 223 - 1 PRBS, 4mVP-P 100mV/div 2.7Gbps, 223 - 1 PRBS, 1200mVP-P 100mV/div 100ps/div MAX3726 toc12 0 22 12 1 0 MAX3746 toc06 9 MAX3746 toc05 1200 MAX3746 toc04 10 RANDOM JITTER (psRMS) DETERMINISTIC JITTER vs. INPUT COMMON-MODE VOLTAGE (2.7Gbps, K28.5) BIT-ERROR RATIO vs. INPUT VOLTAGE DETERMINISTIC JITTER (psP-P) RANDOM JITTER vs. INPUT AMPLITUDE 100 DEASSERT 80 60 40 20 ASSERT 0 50ps/div 50ps/div 0 10 20 30 RTH (kΩ) _______________________________________________________________________________________ 5 MAX3746 Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) OUTPUT RETURN GAIN (SDD22) (INPUT SIGNAL LEVEL = -50dBm) (WITH INPUT DC OFFSET) 20 10 GAIN (dB) 10 0 -10 0 -10 -20 -20 -30 -30 -40 100M -40 100M 1G 10G 14 12 10 8 6 4 10G -6 -5 -4 -3 -2 -1 0 FREQUENCY (MHz) RTH = 25kΩ RTH = 14kΩ 3 2 MAX3746 toc17 700 600 OUTPUT RSSI CURRENT (µA) 5 RTH = 2.00kΩ 500 400 300 200 100 0 0 0 100 200 300 400 500 600 700 800 900 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) INPUT TIA CURRENT (µA) SINGLE-ENDED OUTPUT SIGNAL RSSI CURRENT vs. OPTICAL POWER (MAX3744 and MAX3746) MAX3746 toc18 MAX3746 toc19 700 2.7Gbps, 27 - 1, 1000mVP-P 50mV/div OUTPUT RSSI CURRENT (µA) 600 500 400 300 200 100 0 200ps/div -30 -25 -20 -15 -10 -5 OPTICAL POWER (dBm) 6 1 2 3 4 INPUT OFFSET VOLTAGE (mVP-P) RSSI CURRENT vs. INPUT TIA CURRENT (MAX3744 and MAX3746) MAX3746 toc16 6 10 log (DEASSERT/ASSERT) (dB) 16 0 1G LOS HYSTERESIS vs. TEMPERATURE (2.667Gbps, 223 - 1 PRBS) 1 18 2 FREQUENCY (Hz) 4 20 MAX3746 toc15 20 MAX3746 toc14 30 MAX3746 toc13 30 DETERMINISTIC JITTER vs. INPUT OFFSET VOLTAGE (2.667Gbps, K28.5) DETERMINISTIC JITTER (psP-P) INPUT RETURN GAIN (SDD11) (INPUT SIGNAL LEVEL = -50dBm) (OUTPUT DISABLED) GAIN (dB) MAX3746 Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier _______________________________________________________________________________________ 0 5 6 Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier PIN NAME 1, 4 VCC1 2 IN+ Noninverted Input Signal, CML 3 IN- Inverted Input Signal, CML 5 TH Loss-of-Signal Threshold Pin. Resistor to ground (RTH) sets the LOS threshold. Connecting this pin to VCC disables the LOS circuitry and reduces power consumption. 6 DISABLE 7 LOS 8, 16 GND 9 FUNCTION Supply Voltage Disable Input, CMOS/TTL. The data outputs are held static when this pin is asserted high. The LOS function remains active when the outputs are disabled. Noninverted Loss-of-Signal Output. LOS is asserted high when the signal drops below the assert threshold set by the TH input. The output is open collector. Supply Ground OUTPOL Output Polarity Control. Connect to GND for an inversion of polarity through the limiting amplifier and connect to VCC for normal operation. See Table 1 for all settings. 10 OUT- 11 OUT+ Inverted Data Output, CML Noninverted Data Output, CML 12 VCC2 Output Supply 13 RSSI Received-Signal-Strength Indicator. This current output can be used to obtain a ground-referenced voltage proportional to the photodiode current with the MAX3744 by connecting an external resistor between this pin and GND. 14,15 N.C. No Connection. Leave open. EP EXPOSED PAD Connect the exposed pad to board ground for optimal electrical and thermal performance. Detailed Description The MAX3746 limiting amplifier consists of an input buffer, a multistage amplifier, offset-correction circuitry, an output buffer, power-detection circuitry, and signaldetect circuitry (see the Functional Diagram). Input Buffer The input buffer is shown in Figure 3. It provides 50Ω termination for each input signal IN+ and IN-. The MAX3746 can be DC- or AC-coupled to a TIA (TIA output offset degrades receiver performance if DC-coupled). The CML input buffer is optimized for the MAX3744/ MAX3724 TIA. Gain Stage The high-bandwidth multistage amplifier provides approximately 60dB of gain. Offset Correction Loop The MAX3746 is susceptible to DC offsets in the signal path because it has high gain. In communication systems using NRZ data with a 50% duty cycle, pulsewidth distortion present in the signal, or generated in the transimpedance amplifier, appears as an input offset and is reduced by the offset correction loop. CML Output Buffer The MAX3746 limiting amplifier’s CML output provides high tolerance to impedance mismatches and inductive connectors. The OUTPOL setting programs the output current. Connecting the DISABLE pin to VCC disables the output. If the LOS pin is connected to the DISABLE pin, the outputs OUT+ and OUT- are at a static voltage (squelch) whenever the input signal level drops below the LOS threshold. The output common mode remains constant when the part is disabled. The output buffer can be AC- or DC-coupled to the load (Figure 4). _______________________________________________________________________________________ 7 MAX3746 Pin Description MAX3746 Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier VCC VIN IOUT (CML OUTPUT CURRENT) ICC (SUPPLY CURRENT) 50Ω SIGNAL ON 1dB MAX DEASSERT LEVEL 6dB POWER-DETECT WINDOW 50Ω MIN ASSERT LEVEL MAX3746 SIGNAL OFF RTH Figure 1. Power-Supply Current Measurement TIME 0V Figure 2. LOS Assert Threshold Set 1dB Below the Minimum by Receiver Sensitivity for Selected RTH VCC 0.25pF 50Ω VCC 50Ω 50Ω 50Ω OUT+ IN+ OUTQ3 IN0.25pF Q4 Q1 Q2 ESD STRUCTURES DISABLE DATA ESD STRUCTURES Figure 3. CML Input Buffer Power Detect and Loss-of-Signal Indicator The MAX3746 is equipped with multirate LOS circuitry that indicates when the input signal is below a programmable threshold, set by resistor RTH at the TH pin (see the Typical Operating Characteristics for appropriate resistor sizing). An averaging RMS power detector compares the input signal amplitude with this threshold and feeds the signal-detect information to the open-collector LOS output. To prevent LOS chatter in the region of the programmed threshold, approximately 2dB of hysteresis is 8 I1 = f (OUTPOL, DISABLE) I2 = f (OUTPOL, DISABLE) Figure 4. CML Output Buffer built into the LOS assert/deassert function. Once asserted, the LOS is not deasserted until the input amplitude rises to the required level (VDEASSERT). (See Figures 2 and 5.) Design Procedure Program the LOS Assert Threshold External resistor, R TH, programs the loss-of-signal threshold. See the LOS Threshold vs. RTH graph in the Typical Operating Characteristics to select the appropriate resistor. _______________________________________________________________________________________ Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier LOS ESD STRUCTURE GND Figure 5. LOS Output Circuit The MAX3746 RSSI output is connected to an analog input channel of the DS1858/DS1859 SFP controller to convert the analog information into a 16-bit word. The DS1858/DS1859 provide the receive-power information to the host board of the optical receiver through a 2wire interface. The DS1859 allows for internal calibration of the receive power monitor. The MAX3744/MAX3724 and the MAX3746 have been optimized to achieve RSSI stability of 2.5dB within the 6µA to 500µA range of average input photodiode current. To achieve the best accuracy, MAXIM recommends receive-power calibration at the low end (6µA) and the high end (500µA) of the required range. See the RSSI Current Gain graph in the Typical Operating Characteristics. Select the Coupling Capacitor Connecting to the Dallas DS1858/DS1859 When AC coupling is desired, coupling capacitors CIN and COUT should be selected to minimize the receiver’s deterministic jitter. Jitter is decreased as the input low-frequency cutoff (fIN) is decreased. fIN = 1 / [2π(50)(CIN)] For ATM/SONET or other applications using scrambled NRZ data, select (CIN, COUT) ≥ 0.1µF, which provides fIN < 32kHz. For Fibre Channel, Gigabit Ethernet, or other applications using 8B/10B data coding, select (CIN, COUT) ≥ 0.01µF, which provides fIN < 320kHz. Refer to Application Note HFAN-1.1, Choosing ACCoupling Capacitors. For best use of the RSSI monitor, capacitor C1 and resistor R1 shown in the first Typical Application Circuit need to be placed as close as possible to the Dallas diagnostic monitor with the ground of C1 and R1 the same as the DS1858/DS1859 ground. Capacitor C1 suppresses system noise on the RSSI signal. R1 = 3kΩ and C1 = 0.1µF is recommended. RSSI Implementation The SFF-8472 Digital Diagnostic specification requires monitoring of input receive power. The MAX3746 and MAX3744 receiver chipset allows for the monitoring of the average receive power by measuring the average DC current of the photodiode. The MAX3744/MAX3724 preamp measures the average photodiode current and provides the information to the output common mode. The MAX3746 RSSI detect block senses the common-mode DC level of input signals. IN+ and IN- provide a ground-referenced output signal (RSSI) proportional to the photodiode current. The advantage of this implementation is that it allows the TIA to be packaged in a low-cost, conventional 4pin TO-46 header. EMI Performance The MAX3746 has been designed for better EMI performance. To help reduce EMI, special care has been taken to produce symmetrical signal outputs. See the eye diagram of the single-ended output in the Typical Operating Characteristics. Table 1. Logic Table for Polarity and CML Output-Level Settings OUTPOL DESCRIPTION VCC Noninverting output with full CML output level Open Noninverting output with reduced CML output level 30kΩ to GND Inverting output with reduced CML output level GND Inverting output with full CML output level Chip Information TRANSISTOR COUNT: 1385 PROCESS: SiGe Bipolar _______________________________________________________________________________________ 9 MAX3746 VCC Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier MAX3746 Functional Diagram VCC VCC 50Ω 50Ω 50Ω MAX3746 50Ω OFFSET CORRECTION OUTOUT+ IN+ INOUTPOL DECODE RSSI DETECT RSSI DISABLE POWER DETECT TH LOS OUTPOL Typical Operating Circuits (continued) SFP OPTICAL RECEIVER VCC (+3.3V OR APD REFERENCE VOLTAGE) HOST BOARD VCC (+3.3V) SUPPLY FILTER HOST FILTER VCC_RX 5-PIN TO HEADER OUTPOL VCC 0.1µF PIN OR APD IN+ MAX3744 TIA OUT+ 50Ω SERDES 0.1µF OUT- IN- 50Ω MAX3746 RSSI GND TH DISABLE LOS 4.7kΩ TO 10kΩ RTH = 14kΩ DS1859 3-INPUT DIAGNOSTIC MONITOR R1 3.01kΩ 10 2.97V TO 3.6V LOS C1 0.1µF ______________________________________________________________________________________ Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier SFP OPTICAL RECEIVER HOST BOARD VCC (+3.3V OR APD REFERENCE VOLTAGE) VCC (+3.3V) MAX4004 SUPPLY FILTER HOST FILTER VCC_RX 5-PIN TO HEADER OUTPOL VCC COUT 0.1µF CIN 0.1µF PIN OR APD IN+ OUT+ IN- OUT- 50Ω SERDES MAX3744 TIA CIN 0.1µF COUT 0.1µF MAX3746 RSSI 50Ω GND TH DISABLE LOS 4.7kΩ TO 10kΩ RTH = 14kΩ DS1859 3-INPUT DIAGNOSTIC MONITOR 2.97V TO 3.6V LOS Pin Configuration GND N.C. N.C. RSSI 16 15 14 13 VCC1 1 12 VCC2 IN+ 2 11 OUT+ IN- 3 VCC1 4 MAX3746 10 OUT9 5 6 7 TH DISABLE LOS OUTPOL 8 GND 3mm x 3mm QFN ______________________________________________________________________________________ 11 MAX3746 Typical Operating Circuits (continued) Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 12x16L QFN THIN.EPS MAX3746 Low-Power, 622Mbps to 3.2Gbps Limiting Amplifier D2 0.10 M C A B b D D2/2 D/2 E/2 E2/2 CL (NE - 1) X e E E2 L k e CL (ND - 1) X e CL 0.10 C CL 0.08 C A A2 A1 L L e e PACKAGE OUTLINE 12, 16L, THIN QFN, 3x3x0.8mm E 21-0136 1 2 EXPOSED PAD VARIATIONS DOWN BONDS ALLOWED NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220 REVISION C. PACKAGE OUTLINE 12, 16L, THIN QFN, 3x3x0.8mm 21-0136 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.