19-2391; Rev 0; 4/02 +3.3V, 10.7Gbps Limiting Amplifier Features ♦ Single +3.3V Power Supply ♦ 2mVP-P Input Sensitivity ♦ 1.8ps Typical Deterministic Jitter (VIN = 800mVP-P) ♦ Dice and 4mm × 4mm QFN Package Available ♦ Output Disable Feature The MAX3971A is offered in die form and in a compact 4mm × 4mm 20-pin QFN package. Applications VSR OC-192 Receivers Ordering Information 10Gbps Ethernet Optical Receivers 10Gbps Fibre Channel Receivers PART TEMP RANGE PIN-PACKAGE MAX3971AUGP 0°C to +85°C 20 QFN-EP* MAX3971AU/D 0°C to +85°C Dice** *EP = exposed pad **Dice are designed to operate over a 0°C to +110°C junction temperature (TJ) range, but are tested and guaranteed at TA = +25°C. Pin Configuration appears at end of data sheet. Typical Application Circuit +3.3V 0.1µF SUPPLY FILTER +3.3V CZ- CZ+ VCC1 VCC2 VCC3 GNDIN+ 0.1µF TIA OUT+ IN+ 100Ω 0.1µF 0.1µF 50Ω 0.1µF OUT- IN- 50Ω GNDIN- MAX3970 MAX3971A DISABLE ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3971A General Description The MAX3971A is a compact 10.7Gbps limiting amplifier. It accepts signals over a wide range of input voltage levels and provides constant-level output voltages with controlled edge speeds. It functions as a data quantizer with a 240mVP-P differential CML output signal with a 100Ω differential termination. The MAX3971A has a disable function that allows the outputs to be squelched if required by the application. The MAX3971A is designed to work with the MAX3970 transimpedance amplifier (TIA). The limiting amplifier operates on a single +3.3V supply and functions over a 0°C to +85°C temperature range. MAX3971A +3.3V, 10.7Gbps Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC1, VCC2, VCC3 ......................-0.5V to +5.0 V Voltage at IN+, IN-, DISABLE, CZ+, CZ-, OUT+, OUT- .........................................+0.5V to (VCC + 0.5V) Differential Voltage Between CZ+ and CZ- ...........................±1V Differential Voltage Between IN+ and IN-...........................±2.5V Continuous Power Dissipation (TA = +85°C) 20-Pin QFN (derate 20mW/°C above +85°C) .................1.3W Operating Ambient Temperature Range .............-40°C to +85°C Storage Temperature Range .............................-55°C to +150°C Die Attach Temperature...................................................+400°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, output load = 50Ω to VCC, TA = 0°C to +85°C, unless otherwise noted. All AC parameters are measured with a 223 - 1 PRBS pattern applied to the input at 10.7Gbps. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL TYP MAX Supply Current ICC CONDITIONS 50 85 Small-Signal Bandwidth BW 10 Input Sensitivity VIN-min (Notes 1, 2) Input Overload VIN-max (Note 1) Low-Frequency Cutoff 2 Random Jitter tr, tf UNITS mA GHz 5 1200 CZ = 0.1µF (Note 1) Deterministic Jitter Transition Time MIN mVP-P mVP-P 60 75 kHz 5mVP-P input (Notes 1, 3) 5.2 16.0 10mVP-P input (Notes 1, 3) 3.5 14.0 800mVP-P input (Notes 1, 3) 1.8 7.0 1200mVP-P input (Notes 1, 3) 1.9 11.0 20mVP-P < input < 1200mVP-P (Notes 1, 4) 0.6 1.1 psRMS 20% to 80%, differential output (Note 1) 20 30 ps ps Data Input Impedance Single ended 42 50 58 Ω Data Output-Voltage Swing Differential signal amplitude between OUT+ and OUT- 190 240 400 mVP-P Data Output Voltage when Disabled Differential signal amplitude between OUT+ and OUT- 0.25 50 mVP-P Data Output Common-Mode Voltage VCC 75 Data Output Impedance Single ended 42 Data Output Offset when DISABLE is High Disable Input Current DISABLE High Voltage VIH DISABLE Low Voltage VIL Disable Response Time mV 50 58 Ω 75 200 mV 30 60 µA 2 V 0.8 20 V ns Note 1: Guaranteed by design and characterization. Note 2: The output signal amplitude at the sensitivity is > .95 ✕ the amplitude with large input. Note 3: Deterministic jitter is measured with K28.5 pattern (0011 1110 1011 0000 0101) at 10.7Gbps. It is the peak-to-peak deviation from the ideal time crossing, measured at the zero-level crossing of the differential output. Note 4: For a bit-error rate of 10-12, the peak-to-peak random jitter is 14.1 ✕ the RMS random jitter. 2 _______________________________________________________________________________________ +3.3V, 10.7Gbps Limiting Amplifier OUTPUT EYE DIAGRAM (INPUT SIGNAL = 5mVP-P, AT 10.3Gbps) 45mV/div 20ps/div OUTPUT EYE DIAGRAM (INPUT SIGNAL = 800mVP-P, AT 10.7Gbps) SUPPLY CURRENT vs. AMBIENT TEMPERATURE 20ps/div SMALL-SIGNAL GAIN 58 56 45 40 54 35 52 30 GAIN (dB) SUPPLY CURRENT (mA) 50 MAX3971A toc05 60 MAX3971A toc04 45mV/div 50 48 15 10 42 5 OUTPUT VOLTAGE vs. INPUT VOLTAGE 190 170 30 40 50 60 70 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TEMPERATURE (°C) FREQUENCY (GHz) RANDOM JITTER vs. INPUT AMPLITUDE DETERMINISTIC JITTER vs. INPUT AMPLITUDE MAX3971A toc08 2.0 1.5 1 2 3 VIN (mVP-P) 4 5 6 4 3 2 1.0 1 0 0 0 10.7Gbps, K28.5, VCC = +3V, TEMP = 85°C 5 2.5 0.5 150 6 JITTER (psP-P) 210 20 3.0 RANDOM JITTER (psRMS) 230 10 3.5 MAX3971A toc07 250 VOUT (mVP-P) 0 0 270 20 44 40 MAX3971A UGP 25 46 20ps/div MAX3971A toc03 45mV/div 20ps/div 223 - 1PRBS 223 - 1PRBS MAX3971A toc06 45mV/div 223 - 1PRBS MAX39971A toc09 223 - 1PRBS OUTPUT EYE DIAGRAM (INPUT SIGNAL = 1200mVP-P, AT 10.3Gbps) MAX3971A toc02 MAX3971A toc01 OUTPUT EYE DIAGRAM (INPUT SIGNAL = 10mVP-P, AT 10.7Gbps) 1 10 100 1000 INPUT AMPLITUDE (mVP-P) 10,000 1 10 100 1000 10,000 INPUT AMPLITUDE (mVP-P) _______________________________________________________________________________________ 3 MAX3971A Typical Operating Characteristics (VCC = +3.3V, output load = 50Ω to VCC, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +3.3V, output load = 50Ω to VCC, TA = +25°C, unless otherwise noted.) INPUT RETURN LOSS (S11) (VCC = +3.3V) 6 VIN = 5mV 0 -5 -10 -15 3 VIN = 800mV 2 LOSS (dB) 4 MAX3971A -5 -10 LOSS (dB) JITTER (psP-P) 5 0 MAX3971A toc11 10.7Gbps with K28.5 MAX3971A toc10 7 OUTPUT RETURN LOSS (S22) (VCC = +3.3V) MAX3971A toc12 DETERMINISTIC JITTER vs. TEMPERATURE MAX3971A -15 -20 -25 -30 -20 -35 -25 1 -40 -30 10 20 30 40 50 60 70 80 -45 0 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 FREQUENCY (GHz) FREQUENCY (GHz) OUTPUT NOISE POWER (INPUT CONNECTED TO 50Ω TO GND) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY INPUT COMMON-MODE REJECTION RATIO vs. FREQUENCY 45 MAX3971A toc13 -19.0 -19.1 70 CMRR (dB) 35 -19.4 10 60 PSRR (dB) -19.3 VIN = VIN+ = VIN- 65 40 -19.2 55 50 -19.5 45 30 -19.6 0 10 20 30 40 50 60 TEMPERATURE (°C) 4 0 AMBIENT TEMPERATURE (°C) MAX3971A toc14 0 MAX3971A toc15 0 NOISE POWER (dBm) MAX3971A +3.3V, 10.7Gbps Limiting Amplifier 70 80 PSRR = -20log ∆VOUT/∆VCC 10k 100k 1M FREQUENCY (Hz) 40 10M 100M CMRR = -20log(VOUT/VIN) 100 1M 10M 100M FREQUENCY (Hz) _______________________________________________________________________________________ 1G 10G +3.3V, 10.7Gbps Limiting Amplifier PIN NAME 1 GNDIN+ FUNCTION 2 IN+ Noninverting Input Signal 3 IN- Inverting Input Signal 4 GNDIN- 5, 7, 9, 10 N.C. No Connection. Leave unconnected. 6, 8, 11 GND Ground 12, 15 VCC3 Output Circuitry Power Supply 13 OUT- Inverting Output of Amplifier 14 OUT+ Input Ground for Shielding Input Signal IN+. Not connected internally. Input Ground for Shielding Input Signal IN-. Not connected internally. Noninverting Output of Amplifier When DISABLE is connected to VCC or left floating, outputs are disabled. When DISABLE is connected to GND, outputs are enabled. 16 DISABLE 17 VCC2 Power Supply to Circuitry other than Input and Output Circuits 18 CZ+ Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed Description section. 19 CZ- Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed Description section. 20 VCC1 EP EXPOSED PAD Input Circuitry Power Supply Exposed Pad. Must be soldered to supply ground for proper electrical and thermal operation. Detailed Description and Applications Information Figure 1 is a functional diagram of the MAX3971A limiting amplifier. The signal path consists of an input buffer followed by a gain stage and output amplifier. A feedback loop provides offset correction by driving the average value of the differential output to zero. CZ CZ- MAX3971A GNDIN+ OFFSET CORRECTION AMP CZ+ DISABLE LOWPASS FILTER OUT+ IN+ 100Ω Gain Stage and Offset Correction The limiting amplifier provides approximately 42dB gain. The large gain makes the amplifier susceptible to small DC offsets, which cause deterministic jitter. A low-frequency loop is integrated into the limiting amplifier to reduce output offset, typically to less than 2mV. The external capacitor (CZ) is required for stability and to set the low-frequency cutoff for the offset correction loop. The time constant of the loop is set by the product of an equivalent 20kΩ on-chip resistor and the value of the off-chip capacitor (CZ). For stable operation, the minimum value of CZ is 0.01µF. To minimize patterndependent jitter, CZ should be as large as possible. For 10Gbps ethernet and SONET applications, the typical value of CZ is 0.1µF. Keep CZ close to the package to reduce parasitic inductance. CML Input Circuit INPUT AMPLIFIER GAIN 42dB IN- GNDIN- OUTPUT AMPLIFIER OUT- The input buffer is designed to accept CML input signals such as the output from the MAX3970 transimpedance amplifier. An equivalent circuit for the input is shown in Figure 2. For lowest deterministic jitter in all operating conditions, AC-coupling capacitors are recommended on the input. Figure 1. Functional Diagram _______________________________________________________________________________________ 5 MAX3971A Pin Description MAX3971A +3.3V, 10.7Gbps Limiting Amplifier +3.3V VCC1 GNDIN+ 50Ω 50Ω 100kΩ IN+ INGNDIN- ESD STRUCTURES DISABLE 20µA Figure 2. CML Input Equivalent Circuit VCC3 Figure 4. TTL Input Stage 50Ω 50Ω OUT+ OUTDISABLE Q3 Q4 Q1 +3.3V Q2 ESD STRUCTURES L SUPPLY FILTER DATA 0.001µF Figure 3. CML Output Equivalent Circuit VCC1 CML Output Circuit An equivalent circuit for the output network is shown in Figure 3. It consists of a pair of 50Ω resistors connected to VCC driven by the collectors of an output differential transistor pair (Q1 and Q2). The differential output signals are clamped by transistors Q3 and Q4 when the DISABLE input is high. 0.001µF 0.001µF VCC2 MAX3971A Figure 5. Power-Supply Filter DISABLE Function A logic signal can be applied to the DISABLE pin to squelch the output signal. When the output is disabled, an offset is added to the output, preventing the following stage from oscillating, if DC-coupled. See Figure 4 for the input stage of the DISABLE function. 6 _______________________________________________________________________________________ VCC3 +3.3V, 10.7Gbps Limiting Amplifier Chip Information VCC1 CZ- CZ+ VCC2 DISABLE Pin Configuration 20 19 18 17 16 GNDIN+ 1 15 VCC3 IN+ 2 14 OUT+ IN- 3 GNDIN- 4 12 VCC3 N.C. 5 11 GND 13 OUT- 6 7 8 9 10 GND N.C. GND N.C. N.C. MAX3971A 20 QFN 4mm x 4mm TRANSISTOR COUNT: 324 PROCESS: SiGe Bipolar SUBSTRATE: Electrically Isolated _______________________________________________________________________________________ 7 MAX3971A Layout Considerations Circuit board layout and design can significantly affect the performance of the MAX3971A. Use good high-frequency techniques, including fixed-impedance transmission lines for the high-frequency data signal. Use a multilayer board with solid ground plane. Minimize the inductance between the MAX3971A and the ground plane. The MAX3971A uses three power-supply pins (VCC1, VCC2, and VCC3). The input circuitry of the MAX3971A is supplied by VCC1. The output drivers have a separate supply (VCC3), which usually has large pulsing currents. All other circuitry is powered by VCC2. It is possible to simply connect the three pins together. However, using a supply filter ensures better isolation of the input circuitry. For optimal isolation, Figure 5 shows a possible supplyfiltering circuit. Element L, a ferrite bead, provides isolation between a noisy VCC3 and a sensitive VCC1. +3.3V, 10.7Gbps Limiting Amplifier MAX3971A Chip Topography VCC1 CZ- CZ+ VCC2 DISABLE VCC3 GNDIN+ OUT+ IN+ OUTIN0.052" (1.33mm) VCC3 GNDIN- GND NC (0, 0) GND N.C. GND N.C. N.C. 0.042" (1.10mm) 8 _______________________________________________________________________________________ +3.3V, 10.7Gbps Limiting Amplifier • MAX3971A PAD NUMBER X DIMENSION (µm) Y DIMENSION (µm) 1 16 554 2 26 418 3 26 287 4 16 151 5 16 39 6 191 -92 7 303 -92 8 415 -92 9 527 -92 10 639 -92 11 978 67 12 978 179 13 974 315 14 974 446 15 978 582 16 825 647 17 713 647 18 601 647 19 489 647 20 377 647 Pad dimensions: PASSIVATION OPENING: 94.4µm ✕ 94.4µm METAL: 102.4µm ✕ 102.4µm • All measurements specify the lower left corner of the pad. Refer to Application Note H Fan-08.0: Understanding Bonding Coordinates and Physical Die Size. _______________________________________________________________________________________ 9 MAX3971A Chip Topography (continued) Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 12,16,20, 24L QFN.EPS MAX3971A +3.3V, 10.7Gbps Limiting Amplifier Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.