SINGLE SUPPLY QUAD PECL/TTL-TO-PECL FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100S815 is a low skew 1-to-4 PECL differential driver designed for clock distribution in new, highperformance PECL systems. It accepts either a PECL clock input or a TTL input by using the TTL enable pin TEN. When the TTL enable pin is HIGH, the TTL input is enabled and the PECL input is disabled. When the enable pin is set LOW, the TTL input is disabled and the PECL input is enabled. The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. Since the S815 shares a common set of “basic” processing with the other members of the ECLinPS family, wafer characterization at the point of device personalization allows for tighter control of parameters, including propagation delay. To ensure that the skew specification is met, it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used. In most applications, all nine differential pairs will be used and, therefore, terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO as the pair(s) being used on that side) in order to maintain minimum skew. Quad PECL version of popular ECLinPS E111 Low skew Guaranteed skew spec TTL enable input Selectable TTL or PECL clock input Single +5V supply Differential internal design PECL I/O fully compatible with industry standard Internal 75kΩ PECL input pull-down resistors Available in 16-pin SOIC package BLOCK DIAGRAM Q0 Q0 Q1 EIN Q1 0 EIN Q2 Q2 Q3 1 TIN ClockWorks™ SY100S815 Q3 PIN CONFIGURATION TEN PIN NAMES Pin Function EIN, EIN Differential PECL Input Pair TIN TTL Input TEN TTL Input Enable Q0, Q0 – Q3, Q3 Differential PECL Outputs VCC PECL VCC (+5.0V) VEE PECL Ground (0V) VCC 1 16 EIN EIN 2 15 TEN TIN 3 14 VEE Q3 4 Q3 5 Q2 6 11 Q1 Q2 7 10 VCCO 8 9 TOP VIEW SOIC Z16-1 13 Q0 12 Q0 Q1 VCCO Rev.: F 1 Amendment: /0 Issue Date: October, 1998 ClockWorks™ SY100S815 Micrel TRUTH TABLE TEN EIN TIN Q L L X L L H X H H X L L H X H H PECL DC ELECTRICAL CHARACTERISTICS VCC = VCCO = +5.0V ± 5% TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit IIH Input HIGH Current — — 150 — — 150 — — 150 µA IIL Input LOW Current VIH VIL VOH VOL ICC 0.5 — — 0.5 — — 0.5 — — µA Input HIGH Voltage(1) 3.835 — 4.120 3.835 — 4.120 3.835 — 4.120 V Input LOW Voltage(1) 3.190 — 3.525 3.190 — 3.525 3.190 — 3.525 V Output HIGH Voltage(2) VCC –1025 VCC –955 VCC –870 VCC –1025 VCC –955 VCC –870 VCC –1025 VCC –955 VCC –870 mV Output LOW Voltage(2) VCC –1890 VCC –1705 VCC –1620 VCC –1890 VCC –1705 VCC –1620 VCC –1890 VCC –1705VCC –1620 mV Supply(3) Power Current — 53 65 — 53 65 — 60 74 NOTES: 1. VCC = VCCO = 5.0V 2. VIN = VIH (Max.) or VIL (Min.) Loading with 50Ω to VCC –2V. 3. All inputs and outputs open. TTL DC ELECTRICAL CHARACTERISTICS VCC = VCCO = +5.0V ± 5% TA = 0°C Symbol Parameter Min. Typ. TA = +25°C Max. Min. Typ. TA = +85°C Max. Min. Typ. Max. Unit VIH Input HIGH Voltage 2.0 — — 2.0 — — 2.0 — — V VIL Input LOW Voltage — — 0.8 — — 0.8 — — 0.8 V IIH Input HIGH Current(1),(2) — — — — 20 100 — — — — 20 100 — — — — 20 100 µA IIL Input LOW Current(3) — — –0.6 — — –0.6 — — –0.6 mA — — –1.2 — — –1.2 — — –1.2 V VIK Input Clamp Voltage(4) NOTES: 1. VIN=2.7V 2. VIN=5.0V 3. VIN=0.5V 4. IIN=-18mA 2 Condition mA ClockWorks™ SY100S815 Micrel AC ELECTRICAL CHARACTERISTICS(1–6) VCC = VCCO = +5.0V ± 5% TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 430 330 350 — — — 630 730 950 430 330 350 — — — 630 730 950 430 330 350 — — — 630 730 950 Output(1) tPLH tPHL Propagation Delay to EIN (differential)(2) EIN (single-ended)(3) TIN tskew Within-Device skew(4) Unit ps — 25 50 — 25 50 — 25 50 ps VPP PECL(5) Minimum Input Swing 250 — — 250 — — 250 — — mV VCMR PECL Common(6) Mode Range –1.6 — –0.4 –1.6 — –0.4 –1.6 — –0.4 V tr tf Output Rise/Fall Times 20% to 80% 275 375 600 275 375 600 275 375 600 ps NOTES: 1. Part-to-part skew is defined as Max. — Min. value at the given temperature. 2. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 3. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 5. VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP (min.) is AC limited for the S815, as a differential input as low as 50mV will still produce full PECL levels at the output. 6. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.). PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY100S815ZC Z16-1 Commercial SY100S815ZCTR Z16-1 Commercial 3 ClockWorks™ SY100S815 Micrel 16 LEAD SOIC .300" WIDE (Z16-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4