IDT IDT70261S15PF

HIGH-SPEED
16K x 16 DUAL-PORT
STATIC RAM WITH INTERRUPT
Features
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial 20/25/35/55ns (max.)
Low-power operation
– IDT70261S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT70261L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
◆
◆
◆
◆
◆
◆
◆
◆
IDT70261S/L
IDT70261 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack
Industrial temperature range (-40OC to +85OC) is available
for selected speeds
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
LBR
CER
OER
I/O8L-I/O15L
I/O0L-I/O7L
BUSYL
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0R-I/O7R
(1,2)
A13L
A0L
BUSYR(1,2)
Address
Decoder
MEMORY
ARRAY
14
CEL
OEL
R/WL
SEML
INTL (2)
Address
Decoder
A13R
A0R
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
CER
OER
R/W R
SEMR
INTR(2)
3039 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
FEBRUARY 2000
1
©2000 Integrated Device Technology, Inc.
DSC 3039/8
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Description
The IDT70261 is a high-speed 16K x 16 Dual-Port Static RAM. The
IDT70261 is designed to be used as a stand-alone Dual-Port RAM or as
a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power.
The IDT70261 is packaged in a 100-pin TQFP.
A13L
A12L
A11L
A10L
A9L
A8L
A7L
SEML
CEL
UBL
LBL
VCC
R/WL
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
GND
I/O1L
I/O0L
1100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 7675
2
74
3
73
4
72
5
71
70
69
68
6
7
8
67
66
9
10
11
12
13
14
IDT70261PF
PN100-1(4)
65
64
63
100-Pin TQFP
Top View(5)
62
61
15
16
18
19
60
59
58
57
20
21
56
55
22
23
54
53
24
52
17
A13R
A12R
A11R
A10R
A9R
A8R
A7R
A6R
SEMR
CER
UBR
LBR
OER
R/WR
GND
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O7R
I/O8R
I/O9R
I/O10R
I/O11R
I/O12R
I/O13R
I/O14R
GND
I/O15R
N/C
N/C
N/C
N/C
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
N/C
N/C
N/C
N/C
OEL
Pin Configurations(1,2,3)
Index
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
N/C
N/C
N/C
A6L
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
N/C
N/C
N/C
3039 drw 02
,
Pin Names
Left Port
Right Port
Names
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A13L
A0R - A13R
Address
I/O0L - I/O15L
I/O0R - I/O15R
Data Input/Output
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select
LBL
LBR
Lower Byte Select
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
3039 tbl 01
6.42
2
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Maximum Operating Temperature
and Supply Voltage(1,2)
Grade
Commercial
Industrial
Recommended DC Operating
Conditions
Symbol
Ambient
Temperature
GND
Vcc
0OC to +70OC
0V
5.0V + 10%
-40OC to +85OC
0V
5.0V + 10%
Parameter
VCC
Supply Voltage
GND
Ground
V IH
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
Input High Voltage
(2)
6.0
V
3039 tbl 02
NOTES:
Input Low Voltage
V IL
(1)
-0.5
____
0.8
V
1. This is the parameter TA.
3039 tbl 03
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Truth Table I – Non-Contention Read/Write Control
Inputs(1)
Outputs
CE
R/W
OE
UB
LB
SEM
I/O8-15
I/O0-7
H
X
X
X
X
H
High-Z
High-Z
Deselected: Power-Down
X
X
X
H
H
H
High-Z
High-Z
Both Bytes Deselected
L
L
X
L
H
H
DATAIN
High-Z
Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATAIN
Write to Lower Byte Only
L
L
X
L
L
H
DATAIN
DATAIN
Write to Both Bytes
L
H
L
L
H
H
DATAOUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
DATAOUT
Read Lower Byte Only
L
H
L
L
L
H
DATAOUT
DATAOUT
Read Both Bytes
X
X
H
X
X
X
High-Z
High-Z
Outputs Disabled
Mode
3039 tbl 04
NOTE:
1. A0L — A13L ≠ A0R — A13R.
Truth Table II – Semaphore Read/Write Control(1)
Inputs
Outputs
CE
R/W
OE
UB
LB
SEM
I/O8-15
I/O0-7
H
H
L
X
X
L
DATAOUT
DATAOUT
Read Data in Semaphore Flag
X
H
L
H
H
L
DATAOUT
DATAOUT
Read Data in Semaphore Flag
H
↑
X
X
X
L
DATA IN
DATAIN
Write I/O0 into Semaphore Flag
X
↑
X
H
H
L
DATA IN
DATAIN
Write I/O0 into Semaphore Flag
L
X
X
L
X
L
______
______
Not Allowed
L
X
X
X
L
L
______
______
Not Allowed
Mode
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/O's(I/O0 - I/O15 ). These eight semaphores are addressed by A0 - A 2.
3
6.42
3039 tbl 05
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
VTERM(2)
Rating
Capacitance(1) (TA = +25°C, f = 1.0Mhz)
Commercial
& Industrial
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
TBIAS
Temperature
Under Bias
-55 to +125
o
TSTG
Storage
Temperature
-55 to +125
o
IOUT
DC Output
Current
Symbol
V
50
C
Parameter
CIN
Input Capacitance
COUT
Output
Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
3039 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
C
mA
3039 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
70261S
Symbol
Parameter
Test Conditions
70261L
Min.
Max.
Min.
Max.
Unit
|ILI|
Input Leakage Current(1)
VCC = 5.5V, VIN = 0V to V CC
___
10
___
5
µA
|ILO|
Output Leakage Current
CE = VIH, VOUT = 0V to VCC
___
10
___
5
µA
VOL
Output Low Voltage
IOL = 4mA
___
0.4
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
V
3039 tbl 08
NOTE:
1. At Vcc < 2.0V, input leakages are undefined.
AC Test Conditions
Input Pulse Levels
5V
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
5V
893Ω
DATAOUT
BUSY
INT
1.5V
893Ω
DATAOUT
347Ω
30pF
347Ω
5pF*
Figures 1 and 2
3039 tbl 09
,
3039 drw 03
Figure 1. AC Output Test Load
6.42
4
3039 drw 04
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
70261X15
Com'l Only
Symbol
ICC
Parameter
Dynamic Operating Current
(Both Ports Active)
Test Condition
CE = VIL, Outputs Open
SEM = VIH
f = fMAX
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL Level
Inputs)
Standby Current
(One Port - TTL Level Inputs)
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Full Standby Current
(One Port - All CMOS Level
Inputs)
Version
70261X25
Com'l & Ind
Typ.(2)
Max.
Typ.(2)
Max.
Typ. (2)
Max.
Unit
mA
COM'L
S
L
190
190
325
285
180
180
315
275
170
170
305
265
IND
S
L
____
____
____
____
180
180
355
315
170
170
345
305
COM'L
S
L
35
35
95
70
30
30
85
60
25
25
85
60
IND
S
L
____
____
____
____
30
30
100
80
25
25
100
80
COM'L
S
L
125
125
220
190
115
115
210
180
105
105
200
170
IND
S
L
____
____
____
____
115
115
245
210
105
105
230
200
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
IND
S
L
____
____
____
____
1.0
0.2
30
10
1.0
0.2
30
10
COM'L
S
L
120
120
195
170
110
110
185
160
100
100
170
145
IND
S
L
____
____
____
____
110
110
210
185
100
100
200
175
(3)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX
70261X20
Com'l & Ind
mA
(3)
CE"A" = VIL and CE"B" = VIH (5)
Active Port Outputs Open,
f=fMAX (3)
SEMR = SEML = VIH
Both Ports CEL and
CER > VCC - 0.2V
V IN > VCC - 0.2V or
V IN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
V IN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Open
f = fMAX(3)
mA
mA
mA
3039 tbl 10
70261X35
Com'l & Ind
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL Level
Inputs)
Standby Current
(One Port - TTL Level
Inputs)
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Full Standby Current
(One Port - All CMOS
Level Inputs)
Typ.(2)
Max.
Typ. (2)
Max.
Unit
COM'L
S
L
160
160
295
255
150
150
270
230
mA
IND
S
L
160
160
335
295
150
150
310
270
mA
COM'L
S
L
20
20
85
60
13
13
85
60
mA
IND
S
L
20
20
100
80
13
13
100
80
mA
COM'L
S
L
95
95
185
155
85
85
165
135
mA
IND
S
L
95
95
215
185
85
85
195
165
mA
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
mA
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
mA
COM'L
S
L
90
90
160
135
80
80
135
110
mA
IND
S
L
90
90
190
165
80
80
175
150
mA
Test Condition
CE = VIL, Outputs Open
SEM = VIH
70261X55
Com'l & Ind
Version
(3)
f = fMAX
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX(3)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Open,
f=fMAX(3)
SEMR = SEML = VIH
Both Ports CEL and
CER > VCC - 0.2V
V IN > VCC - 0.2V or
V IN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
V IN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Open
f=fMAX(3)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using
“AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5
6.42
3039 tbl 11
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70261X15
Com'l Only
Symbol
Parameter
70261X20
Com'l & Ind
70261X25
Com'l & Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
25
____
ns
tAA
Address Access Time
____
15
____
20
____
25
ns
Chip Enable Access Time
(3)
____
15
____
20
____
25
ns
tABE
Byte Enable Access Time
(3)
____
15
____
20
____
25
ns
tAOE
Output Enable Access Time
____
10
____
12
____
13
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time(1,2)
3
____
3
____
3
____
ns
tHZ
(1,2)
____
10
____
12
____
15
ns
0
____
0
____
0
____
ns
____
15
____
20
____
25
ns
____
10
____
12
____
ns
15
____
20
____
25
tACE
Output High-Z Time
tPU
Chip Enable to Power Up Time
(2)
(2)
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
Semaphore Address Access Time
____
tSAA
ns
3039 tbl 12a
70261X35
Com'l & Ind
Symbol
Parameter
70261X55
Com'l & Ind
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
____
55
____
ns
tAA
Address Access Time
____
35
____
55
ns
Chip Enable Access Time
(3)
____
35
____
55
ns
tABE
Byte Enable Access Time
(3)
____
35
____
55
ns
tAOE
Output Enable Access Time
____
20
____
30
ns
tOH
Output Hold from Address Change
3
____
3
____
ns
3
____
3
____
ns
____
15
____
25
ns
0
____
0
____
ns
____
35
____
50
ns
____
15
____
ns
35
____
55
tACE
tLZ
tHZ
tPU
Output Low-Z Time
(1,2)
Output High-Z Time
(1,2)
Chip Enable to Power Up Time
(2)
(2)
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
15
Semaphore Address Access Time
____
tSAA
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
6.42
6
ns
3039 tbl 12b
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
tAA (4)
(4)
tACE
CE
tAOE
OE
(4)
tABE
(4)
UB, LB
R/W
tOH
tLZ (1)
DATAOUT
VALID DATA
(4)
tHZ
(2)
BUSYOUT
tBDD (3, 4)
3039 drw 05
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD .
5. SEM = VIH.
Timing of Power-Up Power-Down
CE
ICC
tPU
tPD
50%
50%
ISB
3039 drw 06
7
6.42
,
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage (5)
70261X15
Com'l Only
Symbol
Parameter
70261X20
Com'l & Ind
70261X25
Com'l & Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15
____
20
____
25
____
ns
tEW
Chip Enable to End-of-Write
(3)
12
____
15
____
20
____
ns
tAW
Address Valid to End-of-Write
12
____
15
____
20
____
ns
tAS
Address Set-up Time (3)
0
____
0
____
0
____
ns
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
10
____
15
____
15
____
ns
____
10
____
12
____
15
ns
0
____
0
____
0
____
ns
WRITE CYCLE
tWC
tWP
tWR
tDW
Write Cycle Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
(1,2)
tHZ
Output High-Z Time
tDH
Data Hold Time (4)
tWZ
Write Enable to Output in High-Z(1,2)
____
10
____
12
____
15
ns
tOW
Output Active from End-of-Write (1,2,4)
0
____
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
3039 tbl 13a
70261X35
Com'l & Ind
Symbol
Parameter
70261X55
Com'l & Ind
Min.
Max.
Min.
Max.
Unit
35
____
55
____
ns
tEW
Chip Enable to End-of-Write
(3)
30
____
45
____
ns
tAW
Address Valid to End-of-Write
30
____
45
____
ns
tAS
Address Set-up Time (3)
0
____
0
____
ns
25
____
40
____
ns
0
____
0
____
ns
15
____
30
____
ns
____
15
____
25
ns
0
____
0
____
ns
WRITE CYCLE
tWC
tWP
tWR
tDW
Write Cycle Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
(1,2)
tHZ
Output High-Z Time
tDH
Data Hold Time (4)
tWZ
Write Enable to Output in High-Z(1,2)
____
15
____
25
ns
tOW
Output Active from End-of-Write (1,2,4)
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
ns
3039 tbl 13b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = V IL. Either condition must be valid for the entire t EW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
6.42
8
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
CE or SEM
(9)
UB or LB
(9)
tAS (6)
tWP
(2)
tWR
(3)
R/W
tWZ (7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
3039 drw 07
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE or SEM
(9)
tAS (6)
UB or LB
tWR (3)
tEW (2)
(9)
R/W
tDW
tDH
DATAIN
3039 drw 08
NOTES:
1. R/W or CE or UB and LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP ) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going VIH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = V IL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW . If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP .
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
9
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tOH
tSAA
VALID ADDRESS
A0-A2
tAW
VALID ADDRESS
tWR
tACE
tEW
SEM
tSOP
tDW
DATAIN
VALID
I/O0
tAS
tWP
DATAOUT
VALID(2)
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
3039 drw 09
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15 ) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
3039 drw 10
NOTES:
1. DOR = DOL = V IL, CE R = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
6.42
10
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
70261X15
Com'l Only
Symbol
Parameter
70261X20
Com'l & Ind
70261X25
Com'l & Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15
____
20
____
20
ns
20
____
20
ns
BUSY TIMING (M/ S=V IH)
tBAA
BUSY Access Time from Address Match
____
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
tBAC
BUSY Acce ss Time from Chip Enable Low
____
15
____
20
____
20
ns
tBDC
BUSY Acce ss Time from Chip Enable High
____
15
____
17
____
17
ns
tAPS
Arbitration Priority Set-up Time (2)
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data
____
18
____
30
____
30
ns
tWH
Write Hold After BUSY
12
____
15
____
17
____
ns
0
____
0
____
0
____
ns
12
____
15
____
17
____
ns
ns
(3)
(5)
BUSY TIMING (M/ S=V IL)
tWB
BUSY Input to Write (4)
tWH
Write Hold After BUSY
(5)
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay (1)
____
30
____
45
____
50
tDDD
Write Data Valid to Read Data Delay (1)
____
25
____
30
____
35
ns
3039 tbl 14a
70261X35
Com'l & Ind
Symbol
Parameter
70261X55
Com'l & Ind
Min.
Max.
Min.
Max.
Unit
20
____
45
ns
BUSY TIMING (M/ S=V IH)
tBAA
BUSY Access Time from Address Match
____
tBDA
BUSY Disable Time from Address Not Matched
____
20
____
40
ns
tBAC
BUSY Acce ss Time from Chip Enable Low
____
20
____
40
ns
tBDC
BUSY Acce ss Time from Chip Enable High
____
20
____
35
ns
tAPS
Arbitration Priority Set-up Time (2)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
35
____
40
ns
tWH
Write Hold After BUSY
25
____
25
____
ns
0
____
0
____
ns
25
____
25
____
ns
(5)
BUSY TIMING (M/ S=V IL)
tWB
BUSY Input to Write (4)
tWH
Write Hold After BUSY
(5)
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay (1)
____
60
____
80
ns
tDDD
Write Data Valid to Read Data Delay (1)
____
45
____
65
ns
3039 tbl 14b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wave form of Write with Port-to-Port Read and BUSY (M/S = V IH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
11
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDW
tDH
VALID
DATAIN "A"
tAPS
(1)
MATCH
ADDR"B"
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
tDDD
(3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = V IL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
3039 drw 11
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
tWB
(3)
BUSY"B"
R/W"B"
tWH
(1)
(2)
,
3039 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH.
3. tWB is only for the “SLAVE” version.
6.42
12
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)
ADDR"A"
and "B"
ADDRESSES MATCH
+-"A"
tAPS (2)
+-"B"
tBAC
tBDC
*75;"B"
3039 drw 13
Waveform of BUSY Arbitration Cycle Controlled by
Address Match Timing (M/S = VIH)(1)
ADDR"A"
ADDRESS "N"
tAPS
(2)
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
3039 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
70261X15
Com'l Only
Symbol
Parameter
70261X20
Com'l & Ind
70261X25
Com'l & Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tINS
Interrupt Set Time
____
15
____
20
____
20
ns
Interrupt Reset Time
____
15
____
20
____
20
tINR
ns
3039 tbl 15a
70261X35
Com'l & Ind
Symbol
Parameter
70261X55
Com'l & Ind
Min.
Max.
Min.
Max.
Unit
0
____
0
____
ns
0
____
0
____
ns
25
____
40
ns
25
____
40
ns
INTERRUPT TIMING
tAS
tWR
tINS
tINR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
____
Interrupt Reset Time
____
3039 tbl 15b
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
13
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
ADDR"A"
INTERRUPT SET ADDRESS
(2)
tAS (3)
tWR
(4)
CE"A"
R/W"A"
tINS (3)
INT"B"
3039 drw 15
tRC
INTERRUPT CLEAR ADDRESS
ADDR"B"
(2)
tAS (3)
CE"B"
OE"B"
tINR (3)
INT"B"
3039 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Tables
Truth Table III — Interrupt Flag(1)
Left Port
R/W L
L
X
X
X
CEL
L
X
X
L
OE L
X
X
X
L
Right Port
A13L-A0L
3FFF
X
X
3FFE
INTL
X
R/W R
X
CER
X
OE R
X
A13R-A0R
X
INTR
Function
(2)
Set Right INT R Flag
(3)
L
X
L
L
3FFF
H
Reset Right INT R Flag
(3)
L
L
X
3FFE
X
Set Left INTL Flag
(2)
X
X
X
X
X
Reset Left INTL Flag
X
L
H
3039 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = V IL, then no change.
3. If BUSYR = VIL, then no change.
6.42
14
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Truth Table IV —
Address BUSY Arbitration
Inputs
Outputs
CEL
CER
AOL-A13L
AOR-A13R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
3039 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70261 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
1
Semaphore free
Le ft Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Rig ht Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Le ft Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Le ft Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Rig ht Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Le ft Port Writes "1" to Semaphore
1
1
Semaphore free
Rig ht Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Rig ht Port Writes "1" to Semaphore
1
1
Semaphore free
Le ft Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Le ft Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70261.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15 ). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
3039 tbl 18
Functional Description
The IDT70261 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT70261 has an automatic power down feature
controlled by CE. The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when not selected
(CE = VIH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 3FFE
(HEX), where a write is defined as CER = R/WR = VIL per Truth Table
III. The left port clears the interrupt through access of address location
3FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right
port interrupt flag (INTR) is asserted when the left port writes to memory
location 3FFF (HEX) and to clear the interrupt flag (INTR), the right port
must read the memory location 3FFF. The message (16 bits) at 3FFE or
3FFF is user-defined since it is an addressable SRAM location. If the
interrupt function is not used, address locations 3FFE and 3FFF are not
used as mail boxes, but as part of the random access memory. Refer to
Truth Table III for the interrupt operation.
15
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Busy Logic
MASTER
Dual Port
RAM
BUSYL
BUSYL
MASTER
Dual Port
RAM
BUSYL
CE
BUSYR
CE
BUSYR
SLAVE
Dual Port
RAM
BUSYL
SLAVE
Dual Port
RAM
BUSYL
CE
BUSYR
DECODER
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins high. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port low.
The BUSY outputs on the IDT 70261 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
CE
BUSYR
BUSYR
3039 drw 17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70261 RAMs.
Width Expansion with Busy Logic
Master/Salve Arrays
When expanding an IDT70261 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAM array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use the
BUSY signal as a write inhibit signal. Thus on the IDT70261 RAM the BUSY
pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY
pin is an input if the part used as a slave (M/S pin = VIL) as shown in
Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Semaphores
The IDT70261 is an extremely fast Dual-Port 16K x 16 CMOS Static
RAM with an additional 8 address locations dedicated to binary semaphore
flags. These flags allow either processor on the left or right side of the DualPort RAM to claim a privilege over the other processor for functions defined
by the system designer’s software. As an example, the semaphore can
be used by one processor to inhibit the other from accessing a portion of
the Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table V where CE and SEM are both HIGH.
Systems which can best use the IDT70261 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT70261's hardware semaphores, which provide a lockout mechanism without requiring complex
programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT70261 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very highspeed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
6.42
16
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
that semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of the
token via the set and test sequence. Once the right side has relinquished
the token, the left side should succeed in gaining control.
The semaphore flags are active low. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT70261 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a low input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none
of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Table V). That semaphore
can now only be modified by the side showing the zero. When a one is
written into the same location from the same side, the flag will be set to a
one for both sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Table
V). As an example, assume a processor writes a zero to the left port at a
free semaphore location. On a subsequent read, the processor will verify
that it has written successfully to that location and will assume control over
the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
Q
SEMAPHORE
REQUEST FLIP FLOP
Q
D
WRITE
SEMAPHORE
READ
D0
WRITE
SEMAPHORE
READ
,
3039 drw 18
Figure 4. IDT70261 Semaphore Logic
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay low until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time.
The semaphore logic is specially designed to resolve this problem.
If simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making the
request, the first side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be arbitrarily made
to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT70261’s Dual-Port RAM. Say the 16K x 16
RAM was to be divided into two 8K x 16 blocks which were to be dedicated
at any one time to servicing either the left or right port. Semaphore 0 could
be used to indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator for the upper
section of memory.
To take a resource, in this example the lower 8K of Dual-Port RAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 8K. Meanwhile the right processor was attempting to gain control
17
6.42
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
of the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 8K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
8K blocks of Dual-Port RAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during
a transfer and the I/O device cannot tolerate any wait states. With the use
of semaphores, once the two devices has determined which memory area
was “off-limits” to the CPU, both the CPU and the I/O devices could access
their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory “WAIT”
state is available on one or both sides. Once a semaphore handshake has
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one processor
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
processor reads an incomplete data structure, a major error condition may
exist. Therefore, some sort of arbitration must be used between the two
different processors. The building processor arbitrates for the block, locks
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
6.42
18
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
100-pin TQFP (PN100-1)
15
20
25
35
55
Commercial
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
S
L
Standard Power
Low Power
70261
256K (16K x 16) Dual-Port RAM with Interrupt
Speed
in nanoseconds
3039 drw 19
Datasheet Document History
1/14/99:
6/4/99:
2/18/00:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 Added additional notes to pin configurations
Changed drawing format
Page 1 Corrected DSC number
Added Industrial Temperature Ranges and removed related notes
Replaced IDT logo
Changed ±200mV in table and waveform notes to 0mV
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19
6.42
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