Revised February 2005
74AC125 • 74ACT125
Quad Buffer with 3-STATE Outputs
General Description
Features
The AC/ACT125 contains four independent non-inverting
buffers with 3-STATE outputs.
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT125 has TTL-compatible outputs
Ordering Code:
Order Number
Package
Package Description
Number
74AC125SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC125SCX_NL
(Note 1)
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC125SJ
74AC125MTC
M14D
MTC14
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC125PC
N14A
74ACT125SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC125SCX_NL
(Note 1)
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT125SJ
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT125MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT125MTCX_NL
(Note 1)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT125PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC 4-STD-020B). Device available in Tape and Reel only.
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS010692
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74AC125 • 74ACT125 Quad Buffer with 3-STATE Outputs
March 1990
74AC125 • 74ACT125
Connection Diagram
Logic Symbol
IEEE/IEC
Function Table
Pin Descriptions
Pin Names
Inputs
Description
An, Bn
Inputs
On
Outputs
Bn
L
L
L
L
H
H
H
X
Z
H HIGH Voltage Level
L LOW Voltage Level
Z HIGH Impedance
X Immaterial
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2
Output
An
On
Recommended Operating
Conditions
0.5V to 7.0V
Supply Voltage (VCC)
DC Input Diode Current (IK)
VI
VI
0.5V
VCC 0.5V
Supply Voltage (VCC)
20 mA
20 mA
0.5V to VCC 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO
VO
0.5V
VCC 0.5V
DC Output Voltage (VO)
20 mA
20 mA
0.5V to VCC 0.5V
0V to VCC
40qC to 85qC
125 mV/ns
Minimum Input Edge Rate ('V/'t)
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
r50 mA
65qC to 150qC
Junction Temperature (TJ)
125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.
140qC
PDIP
0V to VCC
Output Voltage (VO)
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
DC VCC or Ground Current
Storage Temperature (TSTG)
4.5V to 5.5V
Input Voltage (VI)
Operating Temperature (TA)
r50 mA
per Output Pin (ICC or IGND)
2.0V to 6.0V
ACT
Minimum Input Edge Rate ('V/'t)
DC Output Source
or Sink Current (IO)
AC
DC Electrical Characteristics for AC
Symbol
VIH
VIL
VOH
VOL
Parameter
VCC
25qC
TA
TA
40qC to 85qC
(V)
Typ
Guaranteed Limits
Minimum HIGH Level
3.0
1.5
2.1
2.1
Input Voltage
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
1.65
5.5
2.75
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
0.1
0.1
Maximum LOW Level
Output Voltage
IIN (Note 5)
Maximum Input Leakage Current
IOZ
Maximum 3-STATE Current
3.0
0.002
Units
Conditions
VOUT
V
0.1V
or VCC 0.1V
VOUT
0.1V
V
or VCC 0.1V
V
IOUT
50 PA
V
V
VIN
VIL or VIH
IOH
12 mA
IOH
24 mA
IOH
24 mA (Note 3)
50 PA
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
5.5
r 0.1
r 1.0
PA
VI
5.5
r 0.25
r 2.5
PA
VI
VCC, VGND
VO
VCC, GND
V
IOUT
VIN
VIL or VIH
IOL
12 mA
IOL 24 mA
IOL
24 mA (Note 3)
VCC, GND
VI (OE)
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 4)
5.5
75
mA
VOHD
ICC (Note 5) Maximum Quiescent Supply Current
5.5
40.0
PA
VIN
4.0
V IL, VIH
1.65V Max
3.85V Min
VCC or GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Note: IIN and ICC@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
3
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74AC125 • 74ACT125
Absolute Maximum Ratings(Note 2)
74AC125 • 74ACT125
DC Electrical Characteristics for ACT
Symbol
VIH
VIL
VOH
Parameter
VCC
TA
40qC to 85qC
4.5
1.5
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
3.86
3.76
Minimum HIGH Level
5.5
IIN
TA
Typ
4.5
VOL
25qC
(V)
Guaranteed Limits
2.0
2.0
Units
Conditions
V
VOUT
V
VOUT
0.1V
or VCC 0.1V
0.1V
or VCC 0.1V
50 PA
V
IOUT
VIN
VIL or VIH
V
IOH
24 mA
IOH
24 mA (Note 6)
V
IOUT
VIN
VIL or VIH
V
IOL
24 mA
4.86
4.76
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
5.5
r0.1
r1.0
PA
VI
VCC, GND
5.5
r0.5
r5.0
PA
VI
VIL, VIH
Maximum Input
50 PA
IOL
24 mA (Note 6)
Leakage Current
IOZ
Maximum 3-STATE
Current
ICCT
VO
Maximum ICC/Input
5.5
IOLD
Minimum Dynamic
IOHD
Output Current (Note 7)
ICC
Maximum Quiescent
5.5
0.6
mA
VI
5.5
75
mA
VOLD
5.5
75
mA
VOHD
40.0
PA
VIN
4.0
Supply Current
1.65V Max
3.85V Min
VCC
or GND
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
Note 8: May be measured per the JEDEC Alternate Method.
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VCC, GND
VCC 2.1V (Note 8)
1.5
4
Symbol
tPLH
tPHL
tPZH
tPZL
Parameter
25qC
CL
50 pF
TA
40qC to 85qC
CL
50 pF
Min
Typ
Max
Min
Max
Propagation Delay
3.3
1.0
6.5
9.0
1.0
10.0
Data to Output
5.0
1.0
5.5
7.0
1.0
7.5
Propagation Delay
3.3
1.0
6.5
9.0
1.0
10.0
Data to Output
5.0
1.0
5.0
7.0
1.0
7.5
Output Enable Time
3.3
1.0
6.0
10.5
1.0
11.0
5.0
1.0
5.0
7.0
1.0
8.0
3.3
1.0
7.5
10.0
1.0
11.0
5.0
1.0
5.5
8.0
1.0
8.5
3.3
1.0
7.5
10.0
1.0
10.5
5.0
1.0
6.5
9.0
1.0
9.5
Output Disable Time
tPLZ
TA
(V)
(Note 9)
Output Enable Time
tPHZ
VCC
Output Disable Time
3.3
1.0
7.5
10.5
1.0
11.5
5.0
1.0
6.5
9.0
1.0
9.5
Units
ns
ns
ns
ns
ns
ns
Note 9: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V
AC Electrical Characteristics for ACT
Symbol
tPLH
Parameter
Propagation Delay
VCC
TA
25qC
(V)
CL
50 pF
TA
40qC to 85qC
CL
50 pF
Units
(Note 10)
Min
Typ
Max
Min
Max
5.0
1.0
6.5
9.0
1.0
10.0
ns
5.0
1.0
7.0
9.0
1.0
10.0
ns
Data to Output
tPHL
Propagation Delay
Data to Output
tPZH
Output Enable Time
5.0
1.0
6.0
8.5
1.0
9.5
ns
tPZL
Output Enable Time
5.0
1.0
7.0
9.5
1.0
10.5
ns
tPHZ
Output Disable Time
5.0
1.0
7.0
9.5
1.0
10.5
ns
tPLZ
Output Disable Time
5.0
1.0
7.5
10.0
1.0
10.5
ns
Note 10: Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
Symbol
Parameter
AC/ACT
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
VCC
OPEN
CPD
Power Dissipation Capacitance
45.0
pF
VCC
5.0V
5
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74AC125 • 74ACT125
AC Electrical Characteristics for AC
74AC125 • 74ACT125
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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6
74AC125 • 74ACT125
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
7
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74AC125 • 74ACT125
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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8
74AC125 • 74ACT125 Quad Buffer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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