Revised November 1999 74AC251 • 74ACT251 8-Input Multiplexer with 3-STATE Output General Description Features The AC/ACT251 is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as universal function generator to generate any logic function of four variables. Both true and complementary outputs are provided. ■ ICC reduced by 50% ■ Multifunctional capability ■ On-chip select logic decoding ■ Inverting and noninverting 3-STATE outputs ■ Outputs source/sink 24 mA ■ ACT251 has TTL-compatible inputs Ordering Code: Order Number 74AC251SC 74AC251SJ 74AC251MTC Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 74AC251PC 74ACT251SC 74ACT251MTC 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body MTC16 74ACT251PC N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description S0–S2 Select Inputs OE 3-STATE Output Enable Input I0–I7 Multiplexer Inputs Z 3-STATE Multiplexer Output Z Complementary 3-STATE Multiplexer Output FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009945 www.fairchildsemi.com 74AC251 • 74ACT251 8-Input Multiplexer with 3-STATE Output November 1988 74AC251 • 74ACT251 Functional Description Truth Table This device is a logical implementation of a single-pole, 8position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both true and complementary outputs are provided. The Output Enable input (OE) is active LOW. When it is activated, the logic function provided at the output is: Inputs Outputs OE S2 S1 S0 H X X X Z Z L L L L I0 I0 L L L H I1 I1 I4 • S0 • S1 • S2 + I5 • S0 • S1 • S2 + L L H L I2 I2 I6 • S0 • S1 • S2 + I7 • S0 • S1 • S2) L L H H I3 I3 When the Output Enable is HIGH, both outputs are in the high impedance (High Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. When the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active-LOW portion of the enable voltages. L H L L I4 I4 L H L H I5 I5 L H H L I6 I6 L H H H I7 I7 Z = OE • (I0 • S0 • S1 • S2 + I1• S0 • S1 • S2 + I2 • S0 • S1 • S2 + I3 • S0 • S1 • S2 + Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Z Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 4.5V to 5.5V Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) −0.5V to VCC + 0.5V AC Devices VIN from 30% to 70% of VCC ±50 mA VCC @ 3.3V, 4.5V, 5.5V DC VCC or Ground Current 125 mV/ns Minimum Input Edge Rate (∆V/∆t) ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 2.0V to 6.0V ACT Operating Temperature (TA) DC Output Source or Sink Current (IO) AC ACT Devices −65°C to +150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V PDIP 140°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH TA = +25°C VCC (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.25 ±2.5 µA V IOUT = 50 µA VIN = VIL or VIH IIN (Note 4) Maximum Input Leakage Current IOZ Maximum 3-STATE Current IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, VGND VO = VCC, GND IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min 40.0 µA VIN = VCC or GND ICC (Note 4) Maximum Quiescent Supply Curent 5.5 4.0 Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC251 • 74ACT251 Absolute Maximum Ratings(Note 1) 74AC251 • 74ACT251 DC Electrical Characteristics for ACT VIH VIL VOH TA = +25°C Parameter VCC (V) Typ Minimum HIGH Level 4.5 1.5 Symbol TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 4.5 3.86 3.76 5.5 4.86 4.76 Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V VIN = VIL or VIH VOL IOH = −24 mA V IOH = −24 mA (Note 5) Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.5 ±5.0 µA IOUT = 50 µA V VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Current ICCT Maximum 5.5 IOL = 24 mA IOL = 24 mA (Note 5) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V 1.5 mA IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 40.0 µA ICC/Input Supply Current 0.6 V 5.5 4.0 VIN = VCC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 7) Min Typ Max Min Max Propagation Delay 3.3 1.5 11.5 17.5 1.5 19.0 Sn to Z or Z 5.0 1.5 8.5 12.5 1.5 13.5 Propagation Delay 3.3 1.5 11.0 17.5 1.5 19.0 Sn to Z or Z 5.0 1.5 8.0 12.5 1.5 13.5 Propagation Delay 3.3 1.5 10.0 14.0 1.5 15.5 In to Z or Z 5.0 1.5 7.0 10.0 1.5 11.0 Propagation Delay 3.3 1.5 9.0 14.0 1.5 15.5 In to Z or Z 5.0 1.5 6.5 10.0 1.5 11.0 Output Enable Time 3.3 1.5 7.5 11.0 1.5 12.0 OE to Z or Z 5.0 1.5 5.5 8.0 1.5 9.0 Output Enable Time 3.3 1.5 7.5 11.0 1.5 12.0 OE to Z or Z 5.0 1.5 5.5 8.0 1.5 9.0 Output Disable Time 3.3 1.5 8.5 11.5 1.5 13.0 OE to Z or Z 5.0 1.5 7.0 9.5 1.5 10.0 Output Disable Time 3.3 1.5 7.0 11.0 1.5 12.0 OE to Z or Z 5.0 1.5 5.5 8.0 1.5 8.5 Note 7: Voltage Range 3.3 is 3.3V ± 0.3V. Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 4 Units ns ns ns ns ns ns ns ns Symbol tPLH Parameter Propagation Delay Sn to Z or Z tPHL Propagation Delay Sn to Z or Z tPLH Propagation Delay In to Z or Z tPHL Propagation Delay In to Z or Z tPZH Output Enable Time OE to Z or Z tPZL Output Enable Time OE to Z or Z tPHZ Output Disable Time OE to Z or Z tPLZ Output Disable Time OE to Z or Z V CC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 8) Min Typ Max Min Max 5.0 2.5 7.0 15.5 2.0 17.0 ns 5.0 2.5 7.5 16.5 2.5 18.5 ns 5.0 2.5 5.5 12.0 2.0 13.0 ns 5.0 2.5 6.5 12.5 2.5 14.0 ns 5.0 1.5 5.0 8.5 1.5 9.0 ns 5.0 1.5 4.5 8.5 1.5 9.5 ns 5.0 2.0 6.0 12.0 2.0 13.0 ns 5.0 1.5 4.5 8.5 1.5 9.0 ns Note 8: Voltage Range 5.0 is 5.0V ±0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF V CC = OPEN CPD Power Dissipation Capacitance 70.0 pF V CC = 5.0V 5 Conditions www.fairchildsemi.com 74AC251 • 74ACT251 AC Electrical Characteristics for ACT 74AC251 • 74ACT251 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A www.fairchildsemi.com 6 74AC251 • 74ACT251 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ Type II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com 74AC251 • 74ACT251 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Packge (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 8 74AC251 • 74ACT251 8-Input Multiplexer with 3-STATE Output Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com