MITSUBISHI LSIs M5M5V4R01J-12,-15 1997.11.20 Rev.F 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM DESCRIPTION The M5M5V4R01J is a family of 4194304-word by 1-bit static PIN CONFIGURATION (TOP VIEW) RAMs, fabricated with the high performance CMOS silicon gate process and designed for high speed application. 1 32 2 31 lead package(SOJ). 3 30 4 These device operate on a single 3.3V supply, and are directly 29 5 TTL compatible. They include a power down feature as well. 28 (3.3V) VCC (0V) GND 8 address inputs chip select input FEATURES • Fast access time M5M5V4R01J-12 •••• 12ns(max) M5M5V4R01J-15 •••• 15ns(max) • Low power dissipation Active •••••••••• 297mW(typ) Stand by •••••••••• 3.3mW(typ) • Single +3.3V power supply • Fully static operation : No clocks, No refresh • Test mode is available • Easy memory expansion by S • Three-state outputs : OR-tie capability • OE prevents data contention in the I/O bus • Directly TTL compatible : All inputs and outputs data inputs write control input address inputs 6 7 9 D W A6 A7 A8 A9 A10 10 11 12 PACKAGE High-speed memory units 32pin 400mil SOJ 27 26 25 24 23 22 21 13 20 14 19 15 18 16 17 Outline APPLICATION M5M5V4R01J A0 A1 A2 A3 A4 A5 S The M5M5V4R01J is offered in a 32-pin plastic small outline J- A21 A20 A19 address inputs A18 A17 A16 output enable OE input GND (0V) VCC (3.3V) data outputs Q A15 A14 address A13 inputs A12 A11 control B1/B4 byte input 32P0K A3 4 A4 A5 5 3 6 A6 12 A7 13 A8 14 S W 7 11 MEMORY ARRAY 512 ROWS 8192 COLUMNS COLUMN I/O CIRCUITS COLUMN ADDRESS COLUMN ADDRESS DECODERS DECODERS COLUMN INPUT BUFFERS OE 26 OUTPUT BUFFERS 2 23 Q outputs DATA INPUT BUFFERS 1 A1 A2 ROW ADDRESS DECODERS address inputs A0 ROW INPUT BUFFERS BLOCK DIAGRAM 10 D inputs/ data data 8 24 9 25 B1/B4 17 VCC (3.3V) GND (0V) 15 16 18 19 20 21 22 27 28 29 30 31 32 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 address inputs MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M5V4R01J-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM FUNCTION The operation mode of the M5M5V4R01J is determined by a combination of the device control inputs S, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S. The address must be set-up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while S are in an active state (S=L). When setting S at high level, the chip is in a non-selectable mode in which both reading and writing are disable. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. The RAM works with an organization of 4194304-word by 1 bit,when B1/B4 is low of floating. And an organization of 10485 76-word by 4bit is also obtained for reducing the test time, when B1/B4 is high. FUNCTION TABLE S H W OE Mode X X Non selection D High-impedance L L X Write L H L Read L H H Q High-impedance Icc Stand by Din High-impedance Active High-impedance Dout Active High-impedance High-impedance Active ABSOLUTE MAXIMUM RATINGS Symbol Parameter V cc Supply voltage VI Input voltage VO Output voltage Pd Power dissipation T opr Operating temperature Conditions Ratings Unit -2.0 ~ 4.6 V -2.0 * ~ VCC+0.5 V * With respect to GND * -2.0 ~ VCC+0.5 V 1000 mW Ta=25 C 0 ~ 70 C Tstg(bias) Storage temperature (bias) -10 ~ 85 C T stg -65 ~ 150 C Storage temperature *Pulse width ≤ 20ns, In case of DC:-0.5V DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3V Symbol VIH VIL VOH VOL II unless otherwise noted) Limits Condition Parameter Min High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current I OZ IOH =-4mA IOL= 8mA V I = 0~Vcc VI (S)= VIH Output current in off-state VO= 0~Vcc I CC1 Active supply current (TTL level) I CC2 +10% -5% Typ Stand by current (TTL level) VI (S)= VIH Stand by current VI (S)= Vcc≥0.2V other inputs V I≤0.2V or VI≥Vcc-0.2V AC AC 10 µA 160 15ns cycle 150 90 mA 100 12ns cycle 75 15ns cycle 70 DC I CC3 0.4 2 12ns cycle DC Unit V V V V µA Vcc+0.3 0.8 2.2 -0.3 2.0 VI (S)= VIL other inputs V IH or VIL Output-open(duty 100%) Max mA 50 1 10 mA MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs M5M5V4R01J-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM CAPACITANCE (Ta=0 ~ 70 C, Vcc=3.3V Symbol +10% -5% unless otherwise noted) Parameter Test Condition Min Limit Typ Max Unit CI Input capacitance V I =GND, V I =25mVrms,f=1MHz 8 pF CO Output capacitance V O=GND, VO =25mVrms,f=1MHz 8 pF Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc=5V,Ta=25 C 3: CI,CO are periodically sampled and are not 100% tested. AC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3V +10% -5% unless otherwise noted) (1)MEASUREMENT CONDITION Input pulse levels •••••••••••••••••••••••• V IH =3.0V, V IL =0.0V Input rise and fall time •••••••••••••••••••••••••••••••••••••• 3ns Input timing reference levels •••••••••••• V IH =1.5V, V IL=1.5V Output timing reference levels •••••••••• V OH=1.5V, V OL =1.5V Output loads •••••••••••••••••••••••••••••••••••••••••• Fig1 ,Fig2 Vcc OUTPUT Z0=50Ω 480Ω DQ 255Ω RL=50Ω 5pF (including scope and JIG) VL=1.5V Fig.1 Output load Fig.2 Output load for t en, t MITSUBISHI ELECTRIC dis 3 MITSUBISHI LSIs M5M5V4R01J-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM (2)READ CYCLE Limits M5M5V4R01J -12 Parameter Symbol Min Max M5M5V4R01J -15 Min Unit Max tCR Read cycle time ta (A) Address access time 12 15 ns ta(S) Chip select access time 12 15 ns ta (OE) Output enable access time 6 8 ns tdis(S) Output disable time after S high 0 6 0 7 ns tdis (OE) Output disable time after OE high 0 6 0 7 ns ten (S) Output enable time after S low 0 0 ns ten (OE) Output enable time after OE low 0 0 ns tv(A) Data valid time after address change 3 3 ns tPU Power-up time after chip selection 0 0 ns tPD Power-down time after chip selection 15 12 12 ns 15 ns (3)WRITE CYCLE Limits M5M5V4R01J -12 Parameter Symbol Min Max M5M5V4R01J -15 Min Unit Max tCW Write cycle time 12 15 ns tw(W) Write pulse width 10 12 ns tsu (A)1 Address setup time(W) 0 0 ns tsu (A)2 Address setup time(S) 0 0 ns tsu (S) Chip select setup time 10 12 ns tsu (D) Data setup time 6 7 ns th (D) Data hold time 0 0 ns trec(W) Write recovery time 1 1 ns tdis (W) Output disable time after W low 0 6 0 7 ns tdis Output disable time after OE high 0 6 0 7 ns ten (W) Output enable time after W high 0 0 ns ten (OE) Output enable time after OE low 0 0 ns tsu(A-WH) Address to W High 10 12 ns (OE) MITSUBISHI ELECTRIC 4 MITSUBISHI LSIs M5M5V4R01J-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle 1 A 0~21 t CR VIH VIL ta (A) tv (A) tv (A) Q VOH PREVIOUS DATA VALID VOL UNKNOWN DATA VALID W=H S=L OE=L Read cycle 2 (Note 4) t CR S VIH VIL tdis (S) ta(S) (Note 5) ten (S) Q (Note 5) VOH UNKNOWN DATA VALID VOL tPU Icc tPD ICC1 50% ICC2 50% W=H OE=L Note 4. Addresses valid prior to or coincident with S transition low. 5. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2. Read cycle 3 (Note 6) OE t CR VIH VIL ta (OE) (Note 5) Q VOH tdis (OE) (Note 5) ten (OE) UNKNOWN DATA VALID VOL W=H S=L Note 6. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE)) MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs M5M5V4R01J-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM Write cycle ( W control mode ) t CW A 0~21 S VIH VIL tsu (S) VIH VIL (Note7) (Note7) tsu (A-WH) OE VIH VIL tsu (A) W tw (W) trec (W) VIH VIL tsu (D) th(D) D VIH DATA STABLE VIL tdis(W) (Note 5) ten (OE) (Note 5) ten (W) tdis(OE) Q VOH VOL Hi-Z Write cycle (S control mode ) t CW A 0~21 VIH VIL tsu (A) tsu (S) trec (W) VIH S VIL tw(W) VIH W VIL (Note7) (Note7) tsu (D) D VIH th (D) DATA STABLE VIL tdis (W) ten (S) Q VOH (Note5) (Note5) Hi-Z VOL (Note8) Note 7: Hatching indicates the state is don't care. 8: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance. 9: t en,tdis are periodically sampled and are not 100% tested. MITSUBISHI ELECTRIC 6