2000.11.22 MITSUBISHI LSIs Ver. 1.0 M5M5W416CWG -85HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Those are summarized in the part name table below. FEATURES DESCRIPTION The M5M5W416C is a f amily of low v oltage 4-Mbit static RAMs organized as 262144-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.18µm CMOS technology . The M5M5W416C is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5W416CWG is packaged in a CSP (chip scale package), with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball) and ball pitch of 0.75mm. It giv es the best solution f or a compaction of mounting area as well as f lexibility of wiring pattern of printed circuit boards. Version, Operating temperature I-version -40 ~ +85°C Power Supply Part name - Single 1.65~2.3V power supply Small stand-by current: 0.2µA (2.0V, ty p.) No clocks, No ref resh Data retention supply v oltage =1.5V All inputs and outputs are TTL compatible. Easy memory expansion by S1, S2, BC1 and BC2 Common Data I/O Three-state outputs: OR-tie capability OE prev ents data contention in the I/O bus Process technology : 0.18µm CMOS Package: 48ball 7.0mm x 8.5mm CSP Activ e current Ratings (max.) * Ty pical Icc1 25°C 40°C 25°C 40°C 70°C 85°C (2.3V, max) Stand-by c urrent Access time max. 85ns M5M5W416CWG -85HI 1.65 ~ 2.3V 0.2 0.4 1 2 8 15 30mA (10MHz) 3mA (1MHz) * Typical parameter indicates the value for the center of distribution at 2.0V, and not 100% tested. PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 A BC1 OE A0 A1 A2 S2 B DQ16 BC2 A3 A4 S1 DQ1 Pin A0 ~ A17 Function Address input DQ1 ~ DQ16 Data input / output C DQ14 DQ15 A5 A6 DQ2 DQ3 D GND DQ13 A17 A7 DQ4 VCC E VCC DQ12 GND A16 DQ5 GND W OE DQ6 BC1 Lower By te (DQ1 ~ 8) BC2 Upper By te (DQ9 ~ 16) F DQ11 DQ10 A14 A15 DQ7 G DQ9 N.C. A12 A13 W DQ8 H NC A8 A9 A10 A11 N.C. S1 S2 Chip select input 1 Chip select input 2 Write control input Output enable input Vcc Power supply GND Ground supply Outline: 48FJA NC: No Connection MITSUBISHI ELECTRIC 1 2000.11.22 MITSUBISHI LSIs Ver. 1.0 M5M5W416CWG -85HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION The M5M5W416CWG is organized as 262144-words by 16-bit. These dev ices operate on a single +1.65~2.3V power supply , and are directly TTL compatible to both input and output. Its f ully static circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of t he dev ice control inputs BC1 , BC2 , S1, S2 , W and OE. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W ov erlaps with the low lev el BC1 and/or BC2 and the low lev el S1 and the high lev el S2. The address(A0~A17) must be set up bef ore the write cycle and must be stable during the entire cy c le. A read operation is executed by s etting W at a high lev el and OE at a low lev el while BC1 and/or BC2 and S1 and S2 are in an activ e state(S1=L,S2=H). When setting BC1 at the high lev el and other pins are in an activ e stage , upper-by te are in a selectable mode in which both reading and writing are enabled, and lowerby t e are in a non-selectable mode. And when setting BC2 at a high lev el and other pins are in an activ e stage, lower-by te are in a selectable mode and upperby t e are in a non-selectable mode. BLOCK DIAGRAM When setting BC1 and BC2 at a high lev el or S1 at a high lev el or S2 at a low lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S1, S2. The power supply current is reduced as low as 0.2µA(25°C, ty pical), and the memory data can be held at +1.5V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. FUNCTION TABLE S1 H L H X L L L L L L L L L S2 BC1 BC2 L X X L X X H X X X H H H L H H L H H L H H H L H H L H H L H L L H L L H L L W OE X X X X X X X X L X H L H H L X H L H H L X H L H H Mode Non selection Non selection Non selection Non selection Write Read Write Read Write Read A0 A1 DQ9~16 High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Din Dout High-Z Din Dout High-Z Icc Standby Standby Standby Standby Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e Activ e DQ 1 MEMORY ARRAY DQ 8 262144 WORDS x 16 BITS A 16 - DQ 9 A 17 S1 DQ1~8 CLOCK GENERATOR DQ 16 S2 BC1 Vcc BC2 W GND OE MITSUBISHI ELECTRIC 2 2000.11.22 MITSUBISHI LSIs Ver. 1.0 M5M5W416CWG -85HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Parameter With respect to GND Output v oltage With respect to GND Operating temperature Storage temperature T stg Units Ratings Supply v oltage Input v oltage Power dissipation Ta Conditions With respect to GND Ta=25°C -0.5 * ~ +2.7 -0.2 * ~ Vcc + 0.2 (max. 2.7V) 0 ~ Vcc 700 I-v ersion V mW - 40 ~ +85 °C - 65 ~ +150 °C * -0.7V in case of AC (Pulse< = width DC ELECTRICAL CHARACTERISTICS Symbol V IH V IL V OH V OL II IO ( Vcc=1.65~ 2.3V, unless otherwise noted) Parameter Limits Conditions Min High-lev el input v oltage Low-lev el input v oltage High-level output voltage Low-lev el output v oltage Input leakage current Output leakage current I OH= -0.1mA I OL=0.1mA V I =0 ~ Vcc -0.2 * 1.3 0.4 ~ +25°C - 1.5 0.2 3 1 ~ +40°C - 0.4 2 ~ +70°C - - 8 - - 15 - - 0.5 BC1 and BC2=V IL , S1=V IL ,S2=V IH other pins =V IH or V IL Output - open (duty 100%) f = 10MHz (1) S1 => Vcc - 0.2V, Icc 4 Stand by s upply current ( AC,TTL lev el ) Vcc+0.2V 18 1.5 18 Activ e supply c urrent Icc 2 ( AC,TTL lev el ) ( AC,MOS lev el ) 0.7 x Vcc - f = 10MHz > Vcc - 0.2V, S2 = other inputs = 0 ~ Vcc (2) S2 <= 0.2V, other inputs = 0 ~ Vcc (3) BC1 and BC2 => Vcc - 0.2V > S1 < = 0.2V, S2= Vcc - 0.2V other inputs = 0 ~ Vcc f = 1MHz f = 1MHz ~ +85°C BC1 and BC2=VIH or S1=VIH or S2=VIL Other inputs= 0 ~ Vcc Note 1: Direction for current flowing into IC is indicated as positive (no mark) Units Max BC1 and BC2=VIH or S1=VIH or S2=VIL or OE=VIH, VI/O=0 ~ Vcc BC1 and BC2< = 0.2V, S1< = 0.2V, S2 Vcc-0.2V > other inputs < = 0.2V or = Vcc-0.2V Output - open (duty 100%) Icc 3 Stand by s upply current Ty p 0.2 ±1 ±1 30 3 30 Icc 1 Activ e supply c urrent ( AC,MOS lev el ) 30ns) V µA mA µA mA * -0.7V in case of AC (Pulse< = width 30ns) Note 2: Typical parameter indicates the value for the center of distribution at 2.0V, and not 100% tested. CAPACITANCE Symbol Parameter (Vcc=1.65 ~ 2.3V, unless otherwise noted) Conditions Min CI CO Input capacitance V I =GND, VI =25mVrms, f =1MHz Output capacitance V O = GND,VO =25mVrms, f =1MHz MITSUBISHI ELECTRIC Limits Ty p Max 10 10 Units pF 3 2000.11.22 MITSUBISHI LSIs Ver. 1.0 M5M5W416CWG -85HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS (Vcc=1.65 ~ 2.3V, unless otherwise noted) 1.65~2.3V V IH=0.7 x Vcc+0.2V, V IL=0.2V Input rise time and f all time 5ns Supply v oltage Ref erence lev el V OH=V OL=0.9V CL Transition is measured ±200mV from steady state voltage.(for ten,tdis) Including scope and jig capacitance Fig.1,CL=30pF CL=5pF (for ten,tdis) Output loads 1TTL DQ Input pulse Fig.1 Output load (2) READ CYCLE Limits Parameter Symbol t CR t a(A) t a(S1) t a(S2) t a(BC1) t a(BC2) t a(OE) t dis (S1) t dis (S2) t dis (BC1) t dis (BC2) t dis (OE) t en(S1) t en(S2) t dis (BC1) t dis (BC2) t en(OE) t V(A) 85HI Read cy cle time Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S1 high Output disable time af t er S2 low Output disable time af t er BC1 high Output disable time af t er BC2 high Output disable time af t er OE high Output enable time af ter S1 low Output enable time af ter S2 high Output enable time af ter BC1 low Output enable time af ter BC2 low Output enable time af ter OE low Data v alid time after address Min 85 Units Max 85 85 85 85 85 45 30 30 30 30 30 10 10 10 10 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol t CW t w(W) t su(A) t su(A-WH) t su(BC1) t su(BC2) t su(S1) t su(S2) t su(D) t h(D) t rec (W) t dis (W) t dis (OE) t en(W) t en(OE) Units 85HI Parameter Write cy cle time Write pulse width Address setup time Address setup time with respect to W By te control 1 setup time By te control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recov ery time Output disable time f rom W low Output disable time f rom OE high Output enable time f rom W high Output enable time f rom OE low Min 85 60 0 70 70 70 70 70 35 0 0 Max 30 30 5 5 MITSUBISHI ELECTRIC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 2000.11.22 MITSUBISHI LSIs Ver. 1.0 M5M5W416CWG -85HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle t CR A 0~18 t v (A) t a(A) t a(BC1) or t a(BC2) BC1,BC2 (Note3) t dis (BC1) or t dis (BC1) (Note3) t a(S1) S1 (Note3) t dis (S1) (Note3) t dis (S2) (Note3) t a(S2) S2 (Note3) t a (OE) OE (Note3) t en (OE) W = "H" lev el DQ 1~16 Write cycle ( W control mode ) t dis (OE) t en (BC1) t en (BC2) t en (S1) t en (S2) (Note3) VALID DATA t CW A 0~18 t su (BC1) or t su (BC2) BC1,BC2 (Note3) (Note3) t su (S1) S1 (Note3) (Note3) S2 t su (S2) (Note3) (Note3) OE t su (A) t su (A-WH) t w (W) t rec (W) t dis (W) W t en (OE) t en (W) t dis (OE) DQ 1~16 DATA IN STABLE t su (D) t h (D) MITSUBISHI ELECTRIC 5 2000.11.22 MITSUBISHI LSIs Ver. 1.0 M5M5W416CWG -85HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (BC control mode) t CW A 0~18 t su (A) t su (BC1) or t su (BC2) t rec (W) BC1,BC2 S1 (Note3) (Note3) S2 (Note3) W (Note3) (Note5) (Note4) (Note3) (Note3) t su (D) DQ 1~16 t h (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1 low, S2 high ov erlaps BC1 and/or BC2 low and W low. Note 5: When the f alling edge of W is simultaneously or prior to the f alling edge of BC1 and/or BC2 or the f alling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode. MITSUBISHI ELECTRIC 6 2000.11.22 MITSUBISHI LSIs Ver. 1.0 M5M5W416CWG -85HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (S1 control mode) t CW A 0~18 BC1,BC2 (Note3) t su (S1) t su (A) t rec (W) (Note3) S1 S2 (Note3) (Note3) (Note5) W (Note4) (Note3) t su (D) t h (D) (Note3) DATA IN STABLE DQ 1~16 Write cycle (S2 control mode) t CW A 0~18 BC1,BC2 (Note3) t su (A) t su (S2) t rec (W) (Note3) S1 S2 (Note3) (Note3) (Note5) W (Note4) (Note3) DQ 1~16 t su (D) t h (D) (Note3) DATA IN STABLE MITSUBISHI ELECTRIC 7 2000.11.22 MITSUBISHI LSIs Ver. 1.0 M5M5W416CWG -85HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Vcc Parameter Test conditions (PD) Power down supply voltage V I (BC) Byte control input BC1 & BC2 V I (S2) 1.5V other inputs = 0 ~ Vcc (2) S2 <= 0.2V, other inputs = 0 ~ Vcc (3) BC1 and BC2 => Vcc - 0.2V > Vcc - 0.2V S1 < = 0.2V, S2= other inputs = 0 ~ Vcc t su (PD) t rec (PD) ~ +25°C - 0.1 0.2 0.7 ~ +40°C - 0.2 1.5 ~ +70°C - - 5 ~ +85°C - - 10 Limits Parameter µA Note 2: Typical parameter of Icc(PD) indicates the value for the center of distribution at 1.5V, and not 100% tested. (2) TIMING REQUIREMENTS Symbol V Vcc(PD) Chip select input S2 Power down supply c urrent V 0.7xVcc Vcc(PD) 1.65V (1) S1 => Vcc - 0.2V, (PD) V Vcc(PD) Vcc=1.5V Icc Units 0.7xVcc Vcc(PD) 1.65V 1.65V Vcc(PD) Chip select input S1 Max 1.5 1.65V Vcc(PD) 1.5V V I (S1) Limits Ty p Min Test conditions Min Ty p Max 0 5 Power down set up time Power down recov ery t ime Units ns ms (3) TIMING DIAGRAM BC control mode Vcc t su (PD) 1.65V 1.65V t rec (PD) 0.7 x Vcc 0.7 x Vcc BC1 BC2 BC1 , BC2> = Vcc-0.2V S1 control mode Vcc t su (PD) 1.65V 1.65V t rec (PD) 0.7 x Vcc 0.7 x Vcc S1 > = Vcc-0.2V S1 S2 control mode Vcc S2 t su (PD) 1.65V 1.65V t rec (PD) 0.2V 0.2 S2 0.2V MITSUBISHI ELECTRIC 8 2000.11.22 MITSUBISHI LSIs Ver. 1.0 M5M5W416CWG -85HI 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Revision History Ver. 0.1 / Oct.24.2000 Initial (-85HI) Ver. 0.2 / Oct.26.2000 min.1.8V ---> 85ns min.1.7V ---> 100ns (-85HI) Ver. 0.3 / Oct.26.2000 min.1.65V ---> Ver. 1.0 / Nov.22.2000 tsu(D)35ns ---> 45ns 85ns MITSUBISHI ELECTRIC Keep safety first in your circuit designs! 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