To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI LSIs revision-2.0e, Feb.12, 2002 M5M5408BFP/TP/RT 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION FEATURES The M5M5408B is a f amily of 4-Mbit static RAMs organized as 524,288-words by 8-bit, f abricated by Mitsubishi's highperf ormance 0.25µm CMOS technology . The M5M5408B is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5408B is packaged in 32-pin plastic SOP, 32-pin plastic TSOP. Two ty pes of TSOPs are av ailable, M5M5408BTP (normal-lead-bend TSOP) , M5M5408BRT (rev erse-lead-bend TSOP). These two ty pes TSOPs are suitable f or a surf ace mounting on double-sided printed circuit boards. From the point of operating temperature, the f amily is div ided into two v ersions; "Standard" and "I-v ersion". Those are · · · · · · · · · · · Single +5V power supply Small stand-by current: 0.4µA(3V,ty p.) No clocks, No ref resh Data retention supply v oltage=2.0V to 5.5V All inputs and outputs are TTL compatible. Easy memory expansion by S# Common Data I/O Three-state outputs: OR-tie capability OE# prev ents data contention in the I/O bus Process technology : 0.25µm CMOS Package: M5M5408BFP: 32 pin 525 mil SOP M5M5408BTP/RT: 32 pin 400 mil TSOP(ll) PART NAME TABLE Version, Operating temperature Standard 0 ~ +70°C I-v ersion -40 ~ +85°C Part name (## stands f or "FP","TP",and "RT") Power Supply M5M5408B## -55H ty pical * max. 25°C 25°C 70°C 85°C 0.4µA 1µA 15µA --- 0.4µA 1µA 15µA 30µA 55ns 5.0V M5M5408B## -70H 70ns 55ns M5M5408B## -55HI 5.0V M5M5408B## -70HI Stand-by c urrent Icc (PD), Vcc=3.0V Access time Limit s (max.) 70ns Activ e current Icc1 (5.0V, ty p.*) 50mA (10MHz) 25mA (1MHz) *Ty pical v alues are sampled, and are not 100% tested. PIN CONFIGURATION (TOP VIEW) A 18 A 16 A 14 A 12 A7 A6 A5 A4 A3 A2 A1 A0 DQ 1 DQ 2 DQ 3 GND 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 Outline 32P2M-A (FP) 32P3Y-H (TP) V CC A 15 A 17 W# A 13 A8 A9 A 11 OE# A 10 S# DQ 8 DQ 7 DQ 6 DQ 5 DQ 4 V CC A 15 A 17 W# A 13 A8 A9 A 11 OE# A 10 S# DQ 8 DQ 7 DQ 6 DQ 5 DQ 4 32 1 31 2 30 3 29 4 28 5 27 6 26 7 25 8 24 9 23 10 22 11 21 12 20 13 19 14 18 15 17 16 Outline A 18 A 16 A 14 A 12 A7 A6 A5 A4 A3 A2 A1 A0 DQ 1 DQ 2 DQ 3 Pin A0 ~ A18 Function Address input DQ1 ~ DQ8 Data input / output S# ( S ) Chip select input W# ( W ) Write control input OE# (OE) Vcc Output inable input GND Power supply Ground supply GND 32P3Y-J (RT) 1 MITSUBISHI LSIs revision-2.0e, Feb.12, 2002 M5M5408BFP/TP/RT 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The M5M5408BFP,TP,RT is organized as 524,288-words by 8-bit. These dev ices operate on a single +5.0V power supply , and are directly TTL compatible to both input and output. Its f ully s t atic circuit needs no clocks and no ref resh, and makes it usef ul. A write operation is executed during the S# low and W# low ov erlap time. The address(A0~A18) must be set up bef ore the write cy c le A read operation is executed by s etting W# at a high lev el and OE# at a low lev el while S# are in an activ e state (S#=L). When setting S# at a high lev el, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips. Setting the OE# at a high lev el,the output stage is in a highimpedance state, and the data bus contention problem in the write cy c le is eliminated. The power supply c urrent is reduced as low as 0.4µA (25°C, ty pical), and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. FUNCTION TABLE Pin Mode S# W# H X OE# X Non selection L L X L H L DQ H Address input High-impedance Icc Standby Write Data input (D) Activ e S# ( S ) Chip select input Read Data output (Q) Activ e Activ e W# ( W ) Write control input OE# (OE) Vcc Output inable input High-impedance Read note: "H" and "L" in this table mean VIH and VIL, respectiv ely . "X" in this table should be "H" or "L". L A0 ~ A18 Function H DQ1 ~ DQ8 Data input / output GND Power supply Ground supply BLOCK DIAGRAM A4 A5 8 7 13 A6 A7 6 14 A 12 4 A 14 A 16 3 A 17 A 18 30 20 1 21 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 29 W# 22 S# 24 OE# 5 2 A 15 31 A 10 23 A 11 25 A9 A8 26 A 13 28 15 MEMORY ARRAY 524288 WORDS x 8 BITS 17 18 19 CLOCK GENERATOR 27 A0 12 A1 11 A2 A3 10 32 9 16 V CC (5V) GND (0V) 2 MITSUBISHI LSIs revision-2.0e, Feb.12, 2002 M5M5408BFP/TP/RT 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Ta T stg Parameter Conditions Supply v oltage With respect to GND Input v oltage With respect to GND Output v oltage With respect to GND Power dissipation Ta=25°C Operating temperature Standard Ratings Units -0.3 * ~ +7 -0.3 * ~ Vcc + 0.3 0 ~ Vcc 700 0 ~ +70 -40 ~ +85 -65 ~ +150 I-v ersion Storage temperature V mW °C °C * -3.0V in case of AC (Pulse width _ < 30ns) DC ELECTRICAL CHARACTERISTICS Symbol V IH V IL V OH1 V OH2 V OL II ( Vcc= 5V ±10%, unless otherwise noted) Limits Parameter Conditions Min High-lev el input v oltage High-level output voltage 1 2.2 -0.3 * 2.4 High-level output voltage 2 Vcc-0.5V Low-lev el input v oltage I OH= -1mA I OH= -0.1mA Low-lev el output v oltage I OL=2mA V I =0 ~ Vcc Input leakage current Output leakage current S# = VIH or OE# =V IH, V I/O = 0 ~ Vcc Icc 1 Activ e supply c urrent (CMOS-lev el input) S# _ < 0.2V, output-open Other inputs <_ 0.2V or _> Vcc-0.2V f =10MHz Activ e supply c urrent S# =V IL , output-open Other inputs= VIH or VIL (TTL-lev el input) Stand by s upply current Vcc =5.5V, max. (CMOS-lev el input) _ Vcc-0.2V,other inputs=0~Vcc S# > f =10MHz Icc 3 Icc 4 Stand by s upply current (TTL-lev el input) f =1MHz f =1MHz Standard I-v ersion S# =V IH , other inputs= 0 ~ Vcc Note 1: Direction f or current f lowing into IC is indicated as positiv e (no mark). Note 2: Ty pical v alues are sampled at Vcc=5.0V and Ta=25°C, and are not 100% tested. CAPACITANCE Symbol Parameter CI Input capacitance CO Output capacitance Max - Units Vcc+0.3V 0.8 V 0.4 ±1 ±1 IO Icc 2 Ty p. 50 25 80 30 - 60 30 1.0 1.0 90 40 30 60 - - 3 µA mA µA mA _ * -3.0V in case of AC (Pulse width <30ns) (Vcc=5.0V±10%, unless otherwise noted) Limits Conditions V I =GND, VI =25mVrms, f =1MHz V O = GND,VO =25mVrms, f =1MHz Min Ty p. Max Units 8 10 pF 3 MITSUBISHI LSIs revision-2.0e, Feb.12, 2002 M5M5408BFP/TP/RT 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (Vcc=5.0V±10%, unless otherwise noted) (1) TEST CONDITIONS Supply v oltage 5.0V Input pulse VIH=2.4V,VIL=0.6V (-70H, -70HI) VIH=3.0V,VIL=0V (-55H, -55HI ) Input rise time and f all time 5ns Ref erence lev el VOH=VOL=1.5V Transition is measured ±500mV f rom steady state voltage f or ten and t dis . Fig.1, CL=100pF (-70H, -70HI) CL=30pF (-55H, -55HI ) CL=5pF (f or ten ,t dis ) Output loads 1.8kΩ DQ CL 990Ω C L Includes scope and jig capacitance Fig.1 Output load (2) READ CYCLE Limits Parameter Symbol -55H, -55HI Min t CR t a(A) t a(S) t a(OE) t dis (S) t dis (OE) t en(S) t en(OE) t V(A) Read cy cle time -70H, -70HI Max Min 55 Output enable access time Output disable time af t er S# high Output disable time af t er OE# high 70 70 35 25 25 Output enable time af ter S# low 10 10 Output enable time af ter OE# low 5 10 5 10 Data v alid time after address Max 70 55 55 25 20 20 Address access time Chip select access time Units ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol Parameter -55H, -55HI Min t CW t w(W) t su(A) t su(A-WH) t su(S) t su(D) t h(D) t rec (W) t dis (W) t dis (OE) t en(W) t en(OE) Write cy cle time Write pulse width Address set up time Address set up time with respect to W# high Chip select set up time Data set up time Data hold time Write recov ery time 70 50 0 50 50 25 0 60 60 30 0 0 0 20 20 Output disable time af t er OE# high Output enable time af ter OE# low Min 55 40 0 Output disable time af t er W# low Output enable time af ter W# high Max -70H, -70HI 5 5 Max 25 25 5 5 Units ns ns ns ns ns ns ns ns ns ns ns ns 4 MITSUBISHI LSIs revision-2.0e, Feb.12, 2002 M5M5408BFP/TP/RT 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle t CR A 0~18 t a(A) t v (A) t a(S) S# t dis (S) (Note3) (Note3) t a (OE) OE# t en (OE) (Note3) W# = "H" lev el (Note3) t en (S) t dis (OE) DQ 1~8 VALID DATA Write cycle ( W# control mode ) t CW A 0~18 t su (S) S# (Note4) (Note3) (Note3) t su (A-WH) OE# t w (W) t su (A) W# t rec (W) (Note4) t dis (W) t en (OE) t dis (OE) t en (W) DATA IN STABLE DQ 1~8 (Note 6) t su (D) t h (D) 5 MITSUBISHI LSIs revision-2.0e, Feb.12, 2002 M5M5408BFP/TP/RT 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM Write cycle (S# control mode) t CW A 0~18 t su (S) t su (A) S# t rec (W) (Note4) (Note5) W# (Note4) (Note3) (Note3) t su (D) DQ 1~8 Note Note Note Note (Note 6) t h (D) DATA IN STABLE 3: Hatching indicates the state is "don't care". 4: A Write occurs during the ov erlap of a low S# and a low W#. 5: If W goes low simultaneously with or prior to S#, the output remains in the high impedance state. 6: Don't apply inv erted phase signal externally when DQ pin is in output mode. 6 MITSUBISHI LSIs revision-2.0e, Feb.12, 2002 M5M5408BFP/TP/RT 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Vcc (PD) V I (S#) Icc (PD) Limits Parameter Test conditions Power down supply v oltage Vcc(PD) >_ 2.2V Chip select input S# _ Vcc(PD) >_ 2.0V 2.2V > Power down supply c urrent I-version Vcc=3.0V, Standard, S# _> Vcc-0.2V, I-version Other input Standard =0 ~ Vcc I-version 85°C 70°C 40°C 0~ 25°C -40~ 25°C Min Ty pical 2 - 2.2 - Max Units - Vcc(PD) 1* 0.4* 30 15 3 1 0.4* V µA 1 *Ty pical v alues are sampled, and are not 100% tested. (2) TIMING REQUIREMENTS Symbol t su (PD) t rec (PD) Limits Parameter Test conditions Power down set up time Power down recov ery t ime Min Ty p 0 5 Max Units ns ms (3) TIMING DIAGRAM S# control mode Vcc t su (PD) 4.5V 4.5V 2.2V 2.2V S# t rec (PD) S# >_ Vcc - 0.2V 7 MITSUBISHI LSIs revision-2.0e, Feb.12, 2002 M5M5408BFP/TP/RT 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM Revision History Revision No. K0.1e K0.2e History The first edition 1) Icc3 limit revised 2) Icc(PD) limit revised 3) Icc1,Icc2 conditions revised 1) Vcc Level in the Block Diagram rev ised 2) Icc3 limit (typ) revised Date Jul.30, '98 Jun. 3, '99 K1.0e K1.1e The first product version Product lineup revised Oct.12, '99 Oct.21, '99 ----- 2.0e 1) Product lineup revised 2) Symbol notations revised: S -> S#, W-> W#, OE -> OE# 3) Icc(PD) conditions revised Feb.12, '02 --- K0.3e Preliminary Preliminary Jun.28, '99 Preliminary 8 Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. 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