MITSUBISHI MH64D64AKQH-75

Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
The MH64D64AKQH is 67108864 - word x 64-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 16 industry standard 32M x 8 DDR
Sy nchronous DRAMs in Small TSOP with SSTL_2 interf ace
which achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
FEATURES
Max.
Frequency
Type name
CLK
Access Time
[component level]
MH64D64AKQH-75
133MHz
+ 0.75ns
MH64D64AKQH-10
100MHz
+ 0.8ns
- Utilizes industry standard 32M X 8 DDR Synchronous DRAMs
in Smal TSOP package , industry standard EEPROM(SPD) in
TSSOP package
- 200pin SO-DIMM
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per
clock cy c le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transition edges of DQS
- Commands entered on each positiv e CLK edge
- Data and data mask ref erenced to both edges of DQS
- 4bank operation concontrolled by BA0,BA1(Bank Address
,discrete)
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst Ty pe - sequential/interleav e(programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 ref resh cy c les /64ms
- Auto ref resh and Self ref resh
- Row address A0-12 / Column address A0-9
- SSTL_2 Interf ace
- Module 2bank Conf igration
APPLICATION
Main memory unit for Note PC, Mobile etc.
PCB Outline
(Front)
(Back)
MIT-DS-0418-0.1
1
2
199
200
MITSUBISHI
ELECTRIC
17.May.2001
1
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
PIN CONFIGURATION
PIN
NO.
PIN
NAME
Vref
PIN
NO.
85
PIN
NO.
PIN
NO.
PIN
NO.
1
86
PIN
NAME
NC
169
PIN
NAME
DQS6
170
PIN
NAME
DM6
3
Vss
4
Vss
87
Vss
88
Vss
171
DQ50
172
DQ54
5
DQ0
6
DQ4
89
CK2
90
Vss
173
Vss
174
Vss
7
DQ1
8
DQ5
91
/CK2
92
Vdd
175
DQ51
176
DQ55
9
Vdd
10
Vdd
93
Vdd
94
Vdd
177
DQ56
178
DQ60
11
DQS0
12
DM0
95
CKE1
96
CKE0
179
Vdd
180
Vdd
13
DQ2
14
DQ6
97
NC
98
NC
181
DQ57
182
DQ61
15
Vss
16
Vss
99
A12
100
A11
183
DQS7
184
DM7
17
DQ3
18
DQ7
101
A9
102
A8
185
Vss
186
Vss
19
DQ8
20
DQ12
103
Vss
104
Vss
187
DQ58
188
DQ62
21
Vdd
22
Vdd
105
A7
106
A6
189
DQ59
190
DQ63
23
DQ9
24
DQ13
107
A5
108
A4
191
Vdd
192
Vdd
25
DQS1
26
DM1
109
A3
110
A2
193
SDA
194
SA0
27
Vss
28
Vss
111
A1
112
A0
195
SCL
196
SA1
29
DQ10
30
DQ14
113
Vdd
114
Vdd
197
VddSPD
198
SA2
31
DQ11
32
DQ15
115
A10/AP
116
BA1
199
VddID
200
NC
33
Vdd
34
Vdd
117
BA0
118
/RAS
35
CK0
36
Vdd
119
/WE
120
/CAS
37
/CK0
38
Vss
121
/S0
122
/S1
39
Vss
40
Vss
123
NC
124
NC
41
DQ16
42
DQ20
125
Vss
126
Vss
43
DQ17
44
DQ21
127
DQ32
128
DQ36
45
Vdd
46
Vdd
129
DQ33
130
DQ37
47
DQS2
48
DM2
131
Vdd
132
Vdd
49
DQ18
50
DQ22
133
DQS4
134
DM4
51
Vss
52
Vss
135
DQ34
136
DQ38
53
DQ19
54
DQ23
137
Vss
138
Vss
55
DQ24
56
DQ28
139
DQ35
140
DQ39
57
Vdd
58
Vdd
141
DQ40
142
DQ44
59
DQ25
60
DQ29
143
Vdd
144
Vdd
61
DQS3
62
DM3
145
DQ41
146
DQ45
63
Vss
64
Vss
147
DQS5
148
DM5
65
DQ26
66
DQ30
149
Vss
150
Vss
67
DQ27
68
DQ31
151
DQ42
152
DQ46
69
Vdd
70
Vdd
153
DQ43
154
DQ47
71
NC
72
NC
155
Vdd
156
Vdd
73
NC
74
NC
157
Vdd
158
/CK1
75
Vss
76
Vss
159
Vss
160
CK1
77
NC
78
NC
161
Vss
162
Vss
79
NC
80
NC
163
DQ48
164
DQ52
81
Vdd
82
Vdd
165
DQ49
166
DQ53
83
NC
84
NC
167
Vdd
168
Vdd
MIT-DS-0418-0.1
PIN
NO.
2
PIN
NAME
NC
PIN
NAME
Vref
MITSUBISHI
ELECTRIC
NC: No Connect
17.May.2001
2
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Block Diagram
/S0
/S1
DQS4
DQS0
DM0
DQ0
DQ1
DM
/S
DQS
DM
/S
DM4
DQ32
DQS
DM
/S
DQS
DM
/S
DQS
DQ33
DQ34
DQ35
DQ2
DQ3
D0
DQ4
DQ5
D4
DQ36
DQ37
D8
D12
DQ38
DQ39
DQ6
DQ7
DQS1
DQS5
DM1
DM5
DQ8
DQ9
DQ10
DQ11
DM
/S
DQS
DM
DQ40
DQ41
DQS
/S
DM
/S
DQS
DM
/S
DQS
DQ42
DQ43
D1
DQ12
DQ13
DQ14
DQ15
DQ44
DQ45
D9
D5
D13
DQ46
DQ47
DQS2
DQS6
DM2
DM6
DQ17
DQ48
DQ49
DQ18
DQ19
DQ50
DQ51
DQ16
DM
/S
DQS
DM
D2
DQ20
DQ21
/S
DQS
DM
DQS
DM
D6
DQ52
DQ53
D10
/S
/S DQS
D14
DQ54
DQ55
DQ22
DQ23
DQS7
DQS3
DM3
DM7
DQ24
DQ25
DM
/S
DQS
DM
/S
DQ56
DQ57
DQS
DM
/S
DQS
DM
/S DQS
DQ58
DQ59
DQ26
DQ27
DQ28
DQ29
D3
DQ60
DQ61
D11
D7
D15
DQ62
DQ63
DQ30
DQ31
22Ω
SERIAL PD
CKE0
D0 - D7
CKE1
D8-D15
D0 - D15
/RAS
/CAS
/WE
BA0,BA1,
A<12:0>
CK0
/CK0
CK1
D0 - D15
D0 - D15
/CK1
D0 - D15
/CK2
CK2
8loads
SCL
SA0
SA1
SA2
A0
A1
A2
8loads
0loads
VddSPD
Vdd
Vref
Vss
VddID
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
SDA
WP
NOTE: DQ wiring may differ from that
described in this drawing; however
SPD
DQ/DM/DQS relationships are
D0 - D15 maintained as shown.
D0 - D15 Vdd ID strap connections:
(for memory device Vdd, VddQ)
D0 - D15 Strap out (open): Vdd=VddQ
Strap in (closed): Vdd=VddQ
17.May.2001
3
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
PIN FUNCTION
SYMBOL
TYPE
DESCRIPTION
Input
Clock: CK0-2 and /CK0-2 are dif f erential clock inputs. All address and control
input signals are sampled on the crossing of the positiv e edge of CK0-2 and
negativ e edge of /CK0-2. Output (read) data is ref erenced to the crossings of
CK0-2 and /CK0-2 (both directions of c rossing).
CKE0-1
Input
Clock Enable: CKE0-1 controls internal clock. When CKE0-1 is low, internal
clock f or the f ollowing cy c le is ceased. CKE0-1 is also used to select auto /
self ref resh. After self ref resh mode is started, CKE0-1 becomes
asy nchronous input. Self ref resh is maintained as long as CKE is low.
/S0-1
Input
Chip Select: When /S0-1 is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
CK0-2,/CK0-2
A0-12
Input
A0-12 specif y the Row / Column Address in conjunction with BA0,1. The Row
Address is specif ied by A0-12. The Column Address is specif ied by A0-9.
A10 is also used to indicate precharge option. When A10 is high at a read / write
command, an auto precharge is perf ormed. When A10 is high at a precharge
command, all banks are precharged.
BA0-1
Input
Bank Address: BA0-1 specif ies one of f our banks in SDRAM to which a command
is applied. BA0-1 must be set with ACT, PRE, READ, WRITE commands.
DQ 0-63
Input / Output Data Input/Output: Data bus
DQS0-7
Input / Output
DM0-7
Vdd, Vss
Vddspd
Vref
Input
Data Strobe: Output with read data, input with write data. Edge-aligned with read
data, centered in write data. Used to capture write data.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM0-7 is
sampled HIGH along with that input data during a WRITE access. DM0-7 is sampled on both
edges of DQS0-7. Although DM pins are input only, the DM0-7 loading matches the DQ0-63 and
DQS0-7 loading.
Power Supply Power Supply for the memory array and peripheral circuitry.
Power Supply
Input
Power Supply for SPD
SSTL_2 reference voltage.
This is a bidirectional pin used to transf er data into or out of the SPD EEPROM.
SDA
Input / Output A resistor must be connected to Vdd to act as a pullup.
SCL
Input / Output may be connected f rom the SCL to Vdd to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor
SA0-2
Input
VddID
Output
MIT-DS-0418-0.1
Address pins used to select the Serial Presence Detect.
Vdd identif ication f lag
MITSUBISHI
ELECTRIC
17.May.2001
4
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
BASIC FUNCTIONS
The MH64D64AKQH provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CK0
CK0
/S0
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE0
A10
def ine basic commands
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the
burst read (auto-precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be
written is set by burst length. When A10 =H at this command, the bank is deactivated after
the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates
burst read /write operation. When A10 =H at this command, all banks are deactivated
(precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE0 =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
5
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
COM M AND TRUTH TABLE
COMMAND
MNEMONIC
CKE
n-1
CKE
n
Deselect
DESEL
H
X
NOP
H
Row Address Entry &
Bank Activate
ACT
Single Bank Precharge
Precharge All Banks
A0-9,
note
11-12
/RAS
/CAS
/WE
BA0,1
A10
/AP
H
X
X
X
X
X
X
X
L
H
H
H
X
X
X
H
H
L
L
H
H
V
V
V
PRE
H
H
L
L
H
L
V
L
X
PREA
H
H
L
L
H
L
X
H
X
WRIT E
H
H
L
H
L
L
V
L
V
WRITEA
H
H
L
H
L
L
V
H
V
READ
H
H
L
H
L
H
V
L
V
READA
H
H
L
H
L
H
V
H
V
REFA
H
H
L
L
L
H
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
Burst Terminate
TERM
H
H
L
H
H
L
X
X
X
1
Mode Register Set
MRS
H
H
L
L
L
L
L
L
V
2
No Operation
Column Address Entry
& Write
Column Address Entry
& Write with
Auto-Precharge
Column Address Entry
& Read
Column Address Entry
& Read with
Auto-Precharge
Auto-Refresh
/S
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should
not be used) for read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode
Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are
reserved; A0-A12 provide the op-code to be written to the selected Mode Register.
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
6
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE
Current State
/S
IDLE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
ILLEGAL
2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
2
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
NOP
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
Terminate Burst
ROW ACTIVE
READ
(AutoPrecharge
Disabled)
/RAS /CAS /WE
Address
Command
Op-Code,
Mode-Add
Action
Notes
Bank Active, Latch RA
NOP
4
REFA
Auto-Refresh
5
MRS
Mode Register Set
5
READ / READA
Begin Read, Latch CA,
Determine Auto-Precharge
WRITE /
Begin Write, Latch CA,
WRITEA
Determine Auto-Precharge
Op-Code,
Mode-Add
2
Bank Active / ILLEGAL
Precharge / Precharge All
REFA
ILLEGAL
MRS
ILLEGAL
Terminate Burst, Latch CA,
L
H
L
H
BA, CA, A10
READ / READA Begin New Read, Determine
3
Auto-Precharge
MIT-DS-0418-0.1
WRITE
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
L
L
L
L
WRITEA
Op-Code,
Mode-Add
MITSUBISHI
ELECTRIC
ILLEGAL
2
Bank Active / ILLEGAL
Terminate Burst, Precharge
REFA
ILLEGAL
MRS
ILLEGAL
17.May.2001
7
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State
/S
WRIT E
(AutoPrecharge
Disabled)
H
X
X
X
L
H
H
L
H
H
/RAS /CAS /WE
Address
Command
Action
Notes
X
DESEL
NOP (Continue Burst to END)
H
X
NOP
NOP (Continue Burst to END)
L
BA
TERM
ILLEGAL
Terminate Burst, Latch CA,
L
H
L
H
BA, CA, A10
READ / READA Begin Read, Determine AutoPrecharge
WRITE /
3
Terminate Burst, Latch CA,
Begin Write, Determine AutoPrecharge
3
Bank Active / ILLEGAL
2
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
L
L
L
L
READ with
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
AUTO
PRECHARGE
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
2
L
L
H
L
BA, A10
PRE / PREA
PRECHARGE/ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE with
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
AUTO
PRECHARGE
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
2
L
L
H
L
BA, A10
PRE / PREA
PRECHARGE/ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MIT-DS-0418-0.1
WRITEA
Op-Code,
Mode-Add
Terminate Burst, Precharge
REFA
ILLEGAL
MRS
ILLEGAL
READ / READA ILLEGAL
WRITE /
WRITEA
ILLEGAL
READ / READA ILLEGAL
WRITE /
WRITEA
MITSUBISHI
ELECTRIC
ILLEGAL
17.May.2001
8
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State
/S
PRE -
H
X
X
X
X
DESEL
NOP (Idle after tRP)
CHARGING
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
BA
TERM
ILLEGAL
2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
2
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP (Row Active after tRCD)
L
H
H
H
X
NOP
NOP (Row Active after tRCD)
L
H
H
L
BA
TERM
ILLEGAL
2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
2
L
L
H
H
BA, RA
ACT
ILLEGAL
2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
WRITE RE-
H
X
X
X
X
DESEL
NOP
COVERING
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL
2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
ROW
ACTIVATING
MIT-DS-0418-0.1
/RAS /CAS /WE
Address
Command
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Action
Notes
ILLEGAL
2
NOP (Idle after tRP)
4
REFA
ILLEGAL
MRS
ILLEGAL
2
2
READ / WRITE ILLEGAL
Op-Code,
Mode-Add
MITSUBISHI
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17.May.2001
9
Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State
/S
/RAS /CAS /WE
Address
Command
Action
RE-
H
X
X
X
X
DESEL
NOP (Idle after tRC)
FRESHING
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
MODE
H
X
X
X
X
DESEL
NOP (Idle after tRSC)
REGISTER
L
H
H
H
X
NOP
NOP (Idle after tRSC)
SETTING
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
Notes
READ / WRITE ILLEGAL
Op-Code,
Mode-Add
READ / WRITE ILLEGAL
Op-Code,
Mode-Add
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
10
Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE for CKE
Current State
CKE0 CKE0
/S0 /RAS /CAS /WE
n
n-1
Add
Action
Notes
H
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
Exit Self-Refresh (Idle after tRC)
1
L
H
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
1
L
H
L
H
H
L
X
ILLEGAL
1
L
H
L
H
L
X
X
ILLEGAL
1
L
H
L
L
X
X
X
ILLEGAL
1
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
1
POWER
H
X
X
X
X
X
X
INVALID
DOWN
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
H
X
X
X
X
X
Refer to Function Truth Table
2
H
L
L
L
L
H
X
Enter Self-Refresh
2
H
L
H
X
X
X
X
Enter Power Down
2
H
L
L
H
H
H
X
Enter Power Down
2
H
L
L
H
H
L
X
ILLEGAL
2
H
L
L
H
L
X
X
ILLEGAL
2
H
L
L
L
X
X
X
ILLEGAL
2
L
X
X
X
X
X
X
Refer to Current State =Power Down
2
ANY STATE
H
H
X
X
X
X
X
Refer to Function Truth Table
other than
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle
3
listed above
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle
3
L
L
X
X
X
X
X
Maintain CLK Suspend
SELFREFRESH
ALL BANKS
IDLE
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK0 and other inputs asynchronously
. A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MIT-DS-0418-0.1
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17.May.2001
11
Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
SIMPLIFIED STATE DIAGRAM
POWER
APPLIED
POWER
ON
PRE
CHARGE
ALL
PREA
SELF
REFRESH
REFS
MRS
MODE
REGISTER
SET
REFSX
MRS
REFA
AUTO
REFRESH
IDLE
CKEL
CKEH
Active
Power
Down
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
WRITE
BURST
STOP
READ
WRITE
READ
WRITEA
READA
READ
WRIT E
WRITEA
READ
TERM
READA
READA
PRE
WRITEA
PRE
READA
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
MIT-DS-0418-0.1
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Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM
from damaged or multifunctioning.
1. Apply VDD before or the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS
6. Issue MRS for the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable condition for 200 cycle
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
CK0
Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data until
/CK0
the next MRS command, which may be issued when all banks in discrete
/S0
are in idle state. After tMRD from a MRS command, the DDR DIMM is
/RAS
ready for new command.
/CAS
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
/WE
A1 A0
BA0
0
0
0
0
0
0
DR
0
LTMODE
BT
BL
BA1
V
A12-A0
BL
CL
Latency
Mode
DLL
Reset
MIT-DS-0418-0.1
000
001
010
011
100
101
110
111
0
NO
1
YES
/CAS Latency
R
R
2
R
R
R
Burst
Length
2.5
R
Burst
Type
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
BT= 0
0
1
0
1
0
1
0
1
R
2
4
8
R
R
R
R
BT= 1
R
2
4
8
R
R
R
R
Sequential
Interleaved
R: Reserved for Future Use
MITSUBISHI
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17.May.2001
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Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
EXTENDED MODE REGISTER
DLL disable / enable mode can be programmed by setting the extended
mode register (EMRS). The extended mode register stores these data
until the next EMRS command, which may be issued when all banks in
discrete are in idle state. After tRSC from a EMRS command, the DDR DIMM
is ready for new command.
CK0
/CK0
/S0
/RAS
/CAS
/WE
BA1 BA0 A12 A11 A10 A9
0
1
0
0
0
0
A8
A7
A6
A5
A4
A3
0
0
0
0
0
0
A2
A1
A0
BA0
BA1
QFC DS DD
A12-A0
DLL
Disable
Drive
Strength
QFC
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
0
1
V
0
1
DLL enable
DLL disable
0
1
Normal
Weak
Disable
Enable
17.May.2001
14
Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
/CLK
CLK
Command
Read
Write
Y
Y
Address
DQS
Q0 Q1 Q2 Q3
DQ
Initial Address
Burst
Length
Burst
Length
/CAS
Latency
CL= 2
BL= 4
D0 D1 D2 D3
BL
Column Addressing
A2
A1
A0
Sequential
Interleaved
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
-
-
1
MIT-DS-0418-0.1
2
MITSUBISHI
ELECTRIC
17.May.2001
15
Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
ABSOLUTE M AXIMUM RATINGS
Symbol
Parameter
Conditions
Vdd
Supply Voltage
with respect to Vss
VI
Input Voltage
with respect to Vss
VO
Output Voltage
IO
Output Current
Pd
Power Dissipation
with respect to Vss
Ratings
Unit
-0.5 ~ 3.7
V
-0.5 ~ Vdd+0.5
V
-0.5 ~ Vdd+0.5
V
50
mA
16
W
Ta = 25°C
Topr
Operating Temperature
0 ~ 70
°C
Tstg
Storage Temperature
-45 ~ 100
°C
DC OPERATING CONDITIONS
(Ta=0 ~ 70°C
, unless otherwise noted)
Limits
Symbol
Parameter
Min.
Typ.
Max.
2.7
Vdd
Supply Voltage
2.3
2.5
Vref
Input Reference Voltage
0.49*Vdd
0.5*Vdd
VIH(DC)
High-Level Input Voltage
Vref + 0.18
VIL(DC)
Low-Level Input Voltage
VIN(DC)
Input Voltage Level, CK0 and /CK0
VID(DC) Input Differential Voltage, CK0 and /CK0
VTT
I/O Termination Voltage
0.51*Vdd
Unit Notes
V
V
5
Vdd+0.3
V
-0.3
Vref - 0.18
V
-0.3
Vdd + 0.3
V
0.36
Vdd + 0.6
V
7
Vref + 0.04
V
6
Vref - 0.04
CAPACITANCE
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
Parameter
CI(A)
Input Capacitance, address pin
CI(C)
Input Capacitance, control pin
CI(K)
Input Capacitance, CK0 pin
CI/O
MIT-DS-0418-0.1
Test Condition
VI - 1.25V
f =100MHz
Limits(max.)
80
pF
11
80
pF
11
45
pF
11
20
pF
11
VI = 25mVrm
Input Capacitance, I/O pin
MITSUBISHI
ELECTRIC
Unit Notes
17.May.2001
16
Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Sy m bol
Limits(max)
Parameter/Test Conditions
Unit Notes
-75
-10
IDD0
OPERATING CURRENT: One Bank(Discrete); Activ e-Precharge;
t RC = t RC MIN; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cy c le; address and control inputs changing once per
clock cy c le
1480
1400
mA
IDD1
OPERATING CURRENT: One Bank(Discrete); Activ e-Read-Precharge;
Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0
mA;Address and control inputs changing once per clock cy c le
1520
1440
mA
IDD2P
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
320
320
mA
IDD2N
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs
changing once per clock cy c le
640
640
mA
IDD3P
ACTIVE POWER-DOWN STANDBY CURRENT: One bank activ e;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
480
480
mA
IDD3N
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN);
One bank; Activ e-Precharge; t RC = t RAS MAX; t CK = t CK MIN;
DQ,DM and DQS inputs changing twice per clock cy c le; address and
other control inputs changing once per clock cy c le
1040
960
mA
IDD4R
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One
bank activ e(Discrete); Address and control inputs changing once per
clock cy c le; CL = 2.5; t CK = t CK MIN; IOUT = 0 mA
1960
1840
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
bank activ e(Discrete); Address and control inputs changing once per
IDD4W
clock cy c le; CL = 2.5; t CK = t CK MIN; DQ, DM and DQS inputs
changing twice per clock cy c le
1920
1800
mA
IDD5
AUTO REFRESH CURRENT: t RC = t RFC (MIN)
2960
2800
mA
IDD6
SELF REFRESH CURRENT: CKE
48
48
mA
0.2V
9
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C
Symbol
, Vdd = VddQ = 2.5 ± 0.2V, Vss =VssQ= 0V, unless otherwise noted)
Parameter/Test Conditions
VIH(AC) High-Level Input Voltage (AC)
Limits
Min.
Vref + 0.35
VIL(AC) Low-Level Input Voltage (AC)
VIX(AC) Input Crossing Point Voltage, CLK and /CLK
Ii
0.7
V
Vdd + 0.6
V
7
0.5*Vdd+0.2
8
Off-state Output Current /Q floating Vo=0~V DDQ
-10
10
V
µA
Input Current / VIN=0 ~ VddQ
-32
32
µA
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
0.5*Vdd-0.2
Unit Notes
V
Vref - 0.35
VID(AC) Input Differential Voltage, CLK and /CLK
IOZ
Max.
17.May.2001
17
Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
AC TIMING REQUIREMENTS (Component Level)
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
AC Characteristics
Sy m bol
-75
-10
Min.
Max.
Min.
Max.
Unit
DQ Output Valid data delay time f rom CLK//CLK
-0.75
+0.75
-0.8
+0.8
ns
tDQSCK DQ Output Valid data delay time f rom CLK//CLK
-0.75
+0.75
-0.8
+0.8
ns
tAC
Parameter
tCH
CLK High lev el width
0.45
0.55
0.45
0.55
tCK
tCL
CLK Low lev el width
0.45
0.55
0.45
0.55
tCK
CL=2.5
7.5
15
8
15
ns
tCK
CLK cy c le time
CL=2
10
15
10
15
ns
Notes
tDS
Input Setup time (DQ,DM)
0.5
0.6
ns
tDH
Input Hold time(DQ,DM)
0.5
0.6
ns
tDIPW
DQ and DM input pulse width (f or each input)
1.75
2
ns
tHZ
Data-out-high impedance time f rom CLK//CLK
-0.75
+0.75
-0.8
+0.8
ns
14
tLZ
Data-out-low impedance time f rom CLK//CLK
-0.75
+0.75
-0.8
+0.8
ns
14
+0.6
ns
tDQSQ
DQ Valid data delay time f rom DQS
+0.5
tCLmin
or
tCHmin
tCLmin
or
tCHmin
ns
Output DQS v alid window
tHP0.75
tHP-1.0
ns
tDQSS
Write command to f irst DQS latching transition
0.75
tDQSH
DQS input High lev el width
0.35
0.35
tCK
tDQSL
DQS input Low lev el width
0.35
0.35
tCK
tDSS
DQS f alling edge to CLK setup time
0.2
0.2
tCK
tDSH
DQS f alling edge hold time f rom CLK
0.2
0.2
tCK
tMRD
Mode Register Set command cy c le time
15
15
ns
0
0
ns
16
tCK
15
tHP
Clock half period
tQH
tWPRES Write preamble setup time
1.25
0.75
1.25
tCK
tWPST
Write postamble
0.4
tWPRE
Write preamble
0.25
0.25
tCK
tIS
Input Setup time (address and control)
0.9
1.1
ns
19
tIH
Input Hold time (address and control)
0.9
1.1
ns
19
tRPST
Read postamble
0.4
0.6
0.4
0.6
tCK
tRPRE
Read preamble
0.9
1.1
0.9
1.1
tCK
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
0.6
0.4
0.6
17.May.2001
18
Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
AC TIMING REQUIREMENTS(Continues)
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
AC Characteristics
-75
Parameter
Symbol
-10
Min.
Max.
Min.
Max.
120,000
50
120,000
Unit Notes
tRAS
Row Active time
45
tRC
Row Cycle time(operation)
65
70
ns
tRFC
Auto Ref. to Active/Auto Ref. command period
75
80
ns
tRCD
Row to Column Delay
20
20
ns
tRP
Row Precharge time
20
20
ns
tRRD
Act to Act Delay time
15
15
ns
tWR
Write Recovery time
15
15
ns
tDAL
Auto Precharge write recovery + precharge time
35
35
ns
tWT R
Internal Write to Read Command Delay
1
1
tCK
tXSNR
Exit Self Ref. to non-Read command
75
80
ns
tXSRD
Exit Self Ref. to -Read command
200
200
tCK
tXPNR
Exit Power down to command
1
1
tCK
tXPRD
Exit Power down to -Read command
1
1
tCK
18
tREFI
Average Periodic Refresh interval
7.8
7.8
us
17
ns
Output Load Condition
(f or component measurement)
VREF
DQS
V TT =V REF
DQ
VREF
50ohm
VO U
Zo=50 ohm
30pF
MIT-DS-0418-0.1
V REF
Output Timing
Measurement
Reference
Point
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ELECTRIC
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Notes
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified
AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range
between VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch
as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back
above (below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed +/-2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level of
the same.
9. Enables on-chip refresh and address counters.
10. IDD specification are tested after the device is properly initialized.
11. This parameter is sampled. VddQ = +2.5V+/-0.2V, Vdd = +2.5V+/-0.2V, f =100MHz, Ta = 25 C , VOUT(DC)=
VddQ/2, VOUT(PEAK TO PEAK) = 25mV, DM inputs are grouped with I/O pins - reflecting the fact that they are
matched in laoding (to faciliate trace matching at the board level).
12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK cross;
the input reference level for signals other than CLK//CLK, is VREF.
13. Inputs are not recognized as valid until VREF stabilized. Exception: during the period before VREF stabilizes, CKE=<
0.3VddQ is recognized as LOW.
14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving
(LZ).
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this
CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When
no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous
write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
tDQSS.
17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.
19. For command/address and CLK & /CLK slew rate >1.0V/ns.
O
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
(Component Level)
Read Operation
tCK
tCH
tCL
/CLK
CLK
tIS
Cmd &
Add.
tIH
Valid Data
tDQSCK
VREF
tRPST
tRPRE
DQS
tDQSQ
tQH
tAC
DQ
Write Operation / tDQSS=max.
/CLK
CLK
tDQSS
DQS
tWPST
tDSS
tWPRES
tDQSL
tWPRE
tDQSH
tDS
tDH
DQ
Write Operation / tDQSS=min.
/CLK
CLK
DQS
tDSH
tDQSS
tWPST
tWPRES
tWPRE
tDQSL
tDS
tDQSH
tDH
DQ
MIT-DS-0418-0.1
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
OPERATIONAL DESCRIPTION (Component Level)
BANK ACTIVATE
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command
with the bank addresses (BA0,1). A row is indicated by the row address A12-0. The minimum
activation interval between one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active,
the precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same
time. After tRP from the precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=8, CL=2)
/CLK
CLK
2 ACT command / tRCmin
Command
ACT
tRRD
A0-9,11-12
Xa
tRCmin
ACT READ
PRE
tRAS
Xb
ACT
tRP
Xb
Y
tRCD
BL/2
A10
Xa
Xb
0
BA0,1
00
01
00
Xb
1
01
DQS
DQ
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Precharge all
A precharge command can be issued at BL/2 from a read command without data loss.
MIT-DS-0418-0.1
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
READ
After tRCD from the bank activation, a READ command can be issued. 1st Output data is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the
Burst Length is BL. The start address is specified by A9-A0, and the address sequence of burst data is
defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge
time (tRP) can be hidden behind continuous output data by interleaving the
multiple banks. When A10 is high at a READ command, the auto-precharge(READA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at BL/2 after READA. The next ACT
command can be issued after (BL/2+tRP) from the previous READA.
Multi Bank Interleaving READ (BL=8, CL=2)
/CLK
CLK
Command
ACT
READ ACT
READ PRE
tRCD
A0-9,11-12
Xa
Y
Xb
Y
A10
Xa
0
Xb
0
0
BA0,1
00
00
10
10
00
DQS
DQ
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qb
Qb
Qb
Qb
Qb
Qb
Qb
Qb
Burst Length
/CAS latency
MIT-DS-0418-0.1
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Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
READ with Auto-Precharge (BL=8, CL=2)
/CLK
CLK
Command
BL/2 + tRP
ACT
READ
ACT
BL/2
tRCD
A0-9,11-12
tRP
Xa
Y
Xb
A10
Xa
1
Xb
BA0,1
00
00
00
DQS
Qa
DQ
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Internal precharge
start
READ Auto-Precharge Timing (BL=8)
/CLK
CLK
Command
ACT
READ
BL/2
CL=2.5 DQ
CL=2
DQ
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Internal Precharge Start
Timing
MIT-DS-0418-0.1
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the
WRITE command with data strobe input, following (BL-1) data are written into RAM , when the Burst
Length is BL. The start address is specified by A9-A0, and the address sequence of burst data is defined
by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time
(tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last data to
the PRE command, the write recovery time (tWRP) is required. When A10 is high at a WRITE command,
the auto-precharge(WRITEA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank
is inhibited till the internal precharge is complete. The next ACT command can be issued after tDAL from
the last input data cycle.
Multi Bank Interleaving WRITE (BL=8)
/CLK
CLK
Command
ACT
WRITE
WRITE ACT
PRE
PRE
tRCD
tRCD
Xa
Ya
Xb
Yb
A10
Xa
Xa
0
Xb
0
0
0
BA0,1
00
00
10
10
00
10
A0-9,11-12
DQS
Da0 Da1 Da2 Da3 Da4 Da5
DQ
Da6 Da7 Db0 Db1 Db2 Db3
Db4 Db5 Db6 Db7
WRITE with Auto-Precharge (BL=8)
/CLK
CLK
Command
ACT
WRITE
ACT
tDAL
tRCD
A0-9,11-12
Xa
Y
Xb
A10
Xa
1
Xb
BA0,1
00
00
00
DQS
DQ
MIT-DS-0418-0.1
Da0 Da1 Da2 Da3 Da4 Da5
Da6 Da7
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
Read Interrupted by Read (BL=8, CL=2)
/CLK
CLK
Command
READ READ
A0-9,11-12
A10
BA0,1
READ
READ
Yi
Yj
Yk
Yl
0
0
0
0
00
00
10
01
DQS
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Q a k Q a k Q a k
DQ
Q a k Q a k Q a k Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As
a result, READ to PRE interval determines valid data length to be output. The figure below shows
examples of BL=8.
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
DQ
Command
CL=2.5
READ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4
Q5
PRE
DQS
DQ
Command
READ PRE
DQS
DQ
MIT-DS-0418-0.1
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
Q0
DQ
Command
CL=2.0
READ
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4
Q5
PRE
DQS
DQ
Command
READ PRE
DQS
DQ
MIT-DS-0418-0.1
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted by Burst Stop]
Burst read operation can be interrupted by a burst stop command(TERM ). READ to TERM
interval is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS
Latency. As a result, READ to TERM interval determines valid data length to be output. The figure
below shows examples of BL=8.
Read Interrupted by TERM (BL=8)
/CLK
CLK
Command
READ
TERM
DQS
DQ
Command
CL=2.5
READ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4
Q4
Q5
TERM
DQS
DQ
Command
READ TERM
DQS
DQ
Command
READ
TERM
DQS
Q0
DQ
Command
CL=2.0
READ
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q5
TERM
DQS
DQ
Command
READ TERM
DQS
DQ
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted by Write with TERM]
Read Interrupted by TERM (BL=8)
/CLK
CLK
Command
CL=2.5
READ
TERM
DQS
Q0
DQ
Command
CL=2.0
READ
Q1
TERM
Q2
Q3
D0
D1
D2
D3
D4
D5
D2
D3
D4
D5
D6
D7
WRITE
DQS
DQ
MIT-DS-0418-0.1
WRITE
Q0
Q1
MITSUBISHI
ELECTRIC
Q2
Q3
D0
D1
17.May.2001
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted by Write]
Burst write operation can be interrupted by write of any bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=8)
/CLK
CLK
Command
A0-9,11-12
A10
BA0,1
WRITE WRITE
WRITE
WRITE
Yi
Yj
Yk
Yl
0
0
0
0
00
00
10
00
DQS
Dai0
DQ
Dai1 Daj0 Daj1 Daj2 Daj3 D a k 0 D a k 1 D a k 2 D a k 3 D a k 4 D a k 5 Dal0
Dal1 Dal2 Dal3 Dal4 Dal5
Dal6 Dal7
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The input data on DQ
at the interrupting READ cycle is "don't care". tWTR is referenced from the first positive edge after the
last data input.
Write Interrupted by Read (BL=8, CL=2.5)
/CLK
CLK
Command
WRITE
READ
A0-9,11-12
Yi
Yj
A10
0
0
BA0,1
00
00
DM
tWT R
QS
DQ
MIT-DS-0418-0.1
Dai0
Dai1
Qaj0 Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6 Qaj7
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted by Precharge]
Burst write operation can be interrupted by precharge of the same or all bank. Random column access is
allowed. tWR is referenced from the first positive CLK edge after the last data input.
Write Interrupted by Precharge (BL=8, CL=2.5)
/CLK
CLK
Command
A0-9,11-12
WRITE
PRE
Yi
A10
0
BA0,1
00
00
tWR
DM
QS
DQ
MIT-DS-0418-0.1
Dai0
Dai1
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Initialize and Mode Register sets]
/CLK
CLK
Command
NOP
PRE
A0-9,11-12
A10
1
BA0,1
EMRS
MRS
Code
Code
Code
Code
10
00
PRE
AR
AR
MRS
ACT
Xa
1
Code
Xa
00
Xa
DQS
DQ
tMRD
Extended Mode
Register Set
tMRD
tRP
tRFC
tRFC
tMRD
Mode Register Set,
Reset DLL
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The
refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256M bits memory cells.
The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command must not be
supplied to the device before tRFC from the REFA command.
Auto-Refresh
/CLK
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
tRFC
A0-12
BA0,1
Auto Refresh on All Banks
MIT-DS-0418-0.1
Auto Refresh on All Banks
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[S ELF REFRESH]
Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). Once
the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE
is asynchronous and the only enable input, all other inputs including CLK are disabled and ignored, so that
power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK
inputs, asserting DESEL or NOP command and then asserting CKE for longer than tXSNR/tXSRD.
Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-12
X
Y
BA0,1
X
Y
tXSRD
tXSNR
Self Refresh Exit
MIT-DS-0418-0.1
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Read
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Asynchronous S ELF REFRESH]
Asynchronous Self -refresh mode is entered by CKE=L within 2 tCLK after issuing a REFA command
(/CS=/RAS=/CAS=L,/WE=H). Once the self-refresh is initiated, it is maintained as long as CKE is kept
low. During the self-refresh mode, CKE is asynchronous and the only enable input, all other inputs
including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved.
To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then
asserting CKE for longer than tXSNR/tXSRD.
Asynchronous Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
max 2 tCLK
A0-12
BA0,1
tXSNR
Self Refresh Exit
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh
mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time is NOT
required in the condition of the stable CLK operation during the power down mode.
Power Down by CKE
/CLK
CLK
Standby Power
Down
CKE
Command
PRE
NOP
NOP
tXPNR/
tXPRD
Active Power
Down
CKE
Command
Valid
ACT
NOP
Valid
NOP
[DM CONTROL]
DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM to
write mask latency is 0.
DM Function(BL=8,CL=2)
/CLK
CLK
Command
Write
READ
Don't Care
DM
DQS
DQ
D0
D1
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
masked by DM=H
MIT-DS-0418-0.1
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Preliminary Spec.
MITSUBISHI LSIs
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table I
Byte
Function described
0
Number of Serial PD Bytes Written during Production
SPD enrty data
128
256 Bytes
SPD DATA(hex)
80
1
Total # bytes of SPD memory device
2
Fundamental memory type
3
# Row Addresses on this assembly
4
# Column Addresses on this assembly
5
# Module Banks on this assembly
2BANK
02
6
Data Width of this assembly...
x64
40
7
... Data Width continuation
0
00
Voltage interface standard of this assembly
SSTL2.5V
04
7.5ns
75
-10
8.0ns
80
-75
+0.75ns
75
-10
+0.8 ns
80
8
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=2.5
10
SDRAM Access from Clock
tAC for CL=2.5
11
SDRAM DDR
-75
0D
10
0A
12
Refresh Rate/Type
7.8uS/SR
13
SDRAM width,Primary DRAM
x8
14
15
16
17
Error Checking SDRAM data width
MIimum Clock Delay, Random Column Access
Burst Lengths Supported
Number of Device Banks
07
13
None-parity,Non-ECC
DIMM Configuration type (Non-parity,Parity,ECC)
08
00
82
08
N/A
00
1 clock
01
2, 4, 8
0E
4bank
2.0, 2.5
04
0C
18
CAS# Latency
19
CS# Latency
0
01
WE Latency
1
02
20
21
SDRAM Module Attributes
22
SDRAM Device Attributes:General
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24
25
26
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
Differential Clock
20
VDD + 0.2V
00
-75
10ns
A0
-10
10ns
A0
-75
+0.75ns
75
-10
+0.8ns
80
-75
Undefined
00
-10
Undefined
00
-75
Undefined
00
-10
Undefined
00
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
27
Minimum Row Precharge Time (tRP)
20ns
50
28
Minimum Row Active to Row Active Delay (tRRD)
15ns
3C
29
RAS to CAS Delay Minv (tRCD)
30
Active to Precharge Min (tRAS)
MIT-DS-0418-0.1
20ns
50
-75
45ns
2D
-10
50ns
32
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table II
31
32
33
34
35
Density of each bank on module
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
Data signal input hold time
36-61
Superset Information (may be used in future)
62
SPD Revision
63
Checksum for bytes 0-62
64-71
Manufactures Jedec ID code per JEP-108E
40
0.9nS
90
-10
1.1nS
B0
-75
0.9nS
90
-10
1.1nS
B0
-75
0.5nS
50
-10
0.6nS
60
-75
0.5nS
50
-10
0.6nS
60
option
00
0
00
Check sum for -75
C0
Check sum for -10
46
MITSUBISHI
1CFFFFFFFFFFFFFF
Manufacturing location
Manufacturing Location
Manufactures Part Number
MH64D64AKQH-75
4D483634443634414B51482D373520202020
MH64D64AKQH-10
4D483634443634414B51482D313020202020
72
73-90
256MByte
-75
XX
91-92
Revision Code
PCB revision
rrrr
93-94
Manufacturing date
year/week code
yyww
serial number
ssssssss
Undefined
00
Undefined
00
95-98
99-127
128-255
MIT-DS-0418-0.1
Assembly Serial Number
Reserved
Open for Customer Use
MITSUBISHI
ELECTRIC
17.May.2001
37
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
EEPROM Components A.C. and D.C. Characteristics
Symbol
VCC
VSS
VIH
Parameter
Supply Voltage
Supply Voltage
VIL
Input High Voltage
Input Low Voltage
VOL
Output Low Voltage
Limits
Typ.
Min.
2.2
0
Vccx0.7
-1
0
Max.
5.5
Units
0
Vcc+0.5
Vccx0.3
V
V
V
V
0.4
V
EEPROM A.C.Timing Parameters (Ta=0 to 70°C )
Symbol
Parameter
SCL Clock Frequency
fSCL
TI
TAA
Limits
Min.
Max.
100
Units
200
3.5
ns
us
Noise Supression Time Constant at SCL, SDA inputs
SCL Low to SDA Data Out Valid
TBUF
Time the Bus Must Be Free before a New
Transmission Can Start
KHz
4.7
us
THD:STA
Start Condition Hold Time
4.0
us
TLOW
Clock Low Time
4.7
us
THIGH
Clock High Time
4.0
us
TSU:STA
Start Condition Setup Time
4.7
us
THD:DAT
Data In Hold Time
0
us
TSU:DAT
Data In Setup Time
250
TR
SDA and SCL Rise Time
1
us
TF
SDA and SCL Fall Time
300
ns
TSU:STO
Stop Condition Setup Time
4.0
TDH
Data Out Hold Time
100
TWR
Write Cycle Time
ns
us
ns
10
ms
tWR is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle.
TF
T HIGH
TR
T LOW
SCL
T SU:STO
T SU:STA
T HD:DAT
T HD:STA
T SU:DAT
SDA
IN
T AA
T DH
T BUF
SDA
OUT
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
38
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
OUTLINE
31.75
20.00
4.00
6.00
4.00
0.25Max
2.55
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
Unit.mm
17.May.2001
39
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3.All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of
these materials, and are subject to change by Mitsubishi Electric Corporation without notice
due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
various means, including the Mitsubishi Semiconductor hom e page
(http://www.mitsubishichips.com).
4.When using any or all of the information contained in these materials, including product
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Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other
loss resulting from the information contained herein.
5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in
a device or system that is used under circumstances in which human life is potentially at stake.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein for any specific
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6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or
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8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
40