Order this document by MC44824/D The MC44824/25 are tuning circuits for TV and VCR tuner applications. They contain on one chip all the functions required for PLL control of a VCO. The integrated circuits also contain a high frequency prescaler and thus can handle frequencies up to 1.3 GHz. The MC44824/25 are manufactured on a single silicon chip using Motorola’s high density bipolar process, MOSAIC (Motorola Oxide Self Aligned Implanted Circuits). • • • • • • • • • • • TV AND VCR PLL TUNING CIRCUITS WITH 1.3 GHz PRESCALER AND I2C BUS 14 Complete Single Chip System for MPU Control (I2C Bus). Data and Clock Inputs are 3–Wire Bus Compatible Divide–by–8 Prescaler Accepts Frequencies up to 1.3 GHz 1 D SUFFIX PLASTIC PACKAGE CASE 751A (SO–14) 15 Bit Programmable Divider Reference Divider: Programmable for Division Ratios 512 and 1024 3–State Phase/Frequency Comparator 4 Programmable Chip Addresses 16 3 Output Buffers (MC44824) respectively 5 Output Buffers (MC44825) for 10 mA/15 V Operational Amplifier for use with External NPN Transistor 1 D SUFFIX PLASTIC PACKAGE CASE 751B (SO–16) SO–14 Package for MC44824 and SO–16 for MC44825 High Sensitivity Preamplifier Fully ESD Protected PIN CONNECTIONS MC44824 MOSAIC is a trademark of Motorola, Inc. PD 1 14 UD XTAL1 2 13 GND XTAL2 3 12 HF2 SDA 4 11 HF1 SCL 5 B7 6 10 V CC 9 B1 CA 7 8 B2 (Top View) MC44825 ORDERING INFORMATION Device Operating Temperature Range MC44824D MC44825D Package SO–14 TA = – 20° to + 80°C SO–16 PD 1 XTAL1 2 16 UD 15 GND XTAL2 3 14 HF2 SDA 4 13 HF1 SCL 5 B7 B4 6 7 12 VCC 11 B 0 10 B1 CA 8 9 B2 (Top View) Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA Rev 1 1 MC44824/25 Representative Block Diagram VCC 5.0 V UD 10 (12) 6 (6) Fout B7 Test Logic Fref B4 B2 Buffers 9 (10) 14 (16) (11) B1 1 (1) B0 PD 2.7 V Operational Amplifier Latches DTB1 Gnd 8 (9) (7) 13 (15) T8 DTB2 P–On Reset Phase Comp T9, T12, T14 T13 T10, T11 Latches Fout Fref POR CA SDA SCL 7 (8) 4 CL I2C Bus Receiver 4 (4) 5 (5) Data RL DTF 512/1024 7 Shift Register 15 Bit Ref Divider Latches A 2 (2) 3.2 or 4.0 MHz Osc Latches B 11 (13) HF Input1 12 (14) HF Input2 3 (3) XTAL1 XTAL2 Gnd TDI Preamp ÷8 Prescaler Program Divider 15 Bit Fout Latch Control DTS, EN MC44825 Pin Numbers ( ) This device contains 3,204 active transistors. PIN FUNCTION DESCRIPTION Pin 2 MC44824 MC44825 1 1 PD Input of tuning voltage amplifier 2 2 XTAL1 First crystal input is the active pin at the oscillators 3 3 XTAL2 Second crystal input is the internal ground 4 4 SDA Data input 5 5 SCL Clock input of the I2C bus 6, 8, 9 – B7, B2, B1 Band buffer (open collector) outputs for up to 10 mA – 6, 7, 9, 10, 11 B7, B4, B2, B1, B0 Band buffer (open collector) outputs for up to 10 mA 7 8 CA Chip address selection pin 10 12 VCC Supply voltage, typical 5.0 V 11, 12 13, 14 HF1/HF2 Symmetric HF inputs from local oscillator 13 15 GND Ground 14 16 UD Output of the tuning voltage amplifier. Needs an external NPN with pull–up resistor to drive the varicaps S b l Symbol D Description i i MOTOROLA ANALOG IC DEVICE DATA MC44824/25 MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.) Pin R i Rating MC44824 MC44825 V l Value U i Unit 10 12 6.0 V Band Buffer “Off” Voltage 6, 8, 9 6, 7, 9, 10, 11 15 V Band Buffer “On” Current 6, 8, 9 6, 7, 9, 10, 11 15 mA Storage Temperature – – – 65 to +150 °C Operating Temperature Range – – – 20 to +80 °C RF Input Level (10 MHz to 1.3 GHz) 11, 12 13, 14 1.5 Vrms Power Supply Voltage (VCC) ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C, unless otherwise noted.) Pin MC44824 MC44825 Mi Min T Typ M Max VCC Supply Voltage Range 10 12 4.5 5.0 5.5 V VCC Supply Current (VCC = 5.0 V) 10 12 – 40 55 mA Band Buffer Leakage Current when “Off” at 12 V 6, 8, 9 6, 7, 9, 10, 11 – 0.01 1.0 µA Band Buffer Saturation Voltage when “On” at 10 mA 6, 8, 9 6, 7, 9, 10, 11 – 1.6 1.8 V Data Saturation Voltage at 15 mA Acknowledge “On” 4 4 – – 1.0 V Data/Clock/Enable Current at 0 V 4, 5 4, 5 –10 – 0 µA Data/Clock/Enable Current at 5.0 V 4, 5 4, 5 0 – 1.0 µA Data/Clock/Enable Input Voltage Low 4, 5 4, 5 – – 1.5 V Data/Clock/Enable Input Voltage High 4, 5 4, 5 3.0 – – V 5 5 – – 100 kHz 2, 3 2, 3 3.15 3.2 4.05 MHz Operational Amplifier Input Current 1 1 –15 0 15 nA Phase Detector Current in High Impedance State 1 1 –15 0 15 nA Charge Pump Current of Phase Comparator, T14 = 0 1 1 30 40 60 µA Charge Pump Current of Phase Comparator, T14 = 1 1 1 100 125 200 µA MC44824 MC44825 Mi Min T Typ M Max U i Unit DC Bias 11, 12 13, 14 – 1.6 – V Input Voltage Range 80–150 MHz 150–600 MHz 600–950 MHz 950–1300 MHz 11, 12 11, 12 11, 12 11, 12 13, 14 13, 14 13, 14 13, 14 10 5.0 10 50 – – – – 315 315 315 315 Ch Characteristic i i Clock Frequency Range Oscillator Frequency Range U i Unit HF CHARACTERISTICS (See Figure NO TAG) Pin Ch Characteristic i i MOTOROLA ANALOG IC DEVICE DATA mVrms 3 MC44824/25 Figure 1. HF Sensitivity Test Circuit ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ I2C Bus Bus Controller VCC 5.0 V SDA, SCL VCC MC44824/25 HF 1.0 nF Gnd HF B7 B2 Frequency Counter HF Generator HF Out Gnd In 1.0 nF 50 Ω Cable 470 470 50 Ω VCC Device is in test mode. B2 and B7 are “On”. Sensitivity is level of HF generator on 50 Ω load. Figure 2. Typical HF Input Impedance –j +j 0 0.5 0.5 0.5 ZO = 50 Ω 1.3 GHz 1 1 1 1.0 GHz 2 2 2 500 MHz 50 MHz Data Format and Bus Receiver The circuit receives the information for tuning and control via the I2C bus. The incoming information, consisting of a chip address byte followed by two or four data bytes, is treated in the I2C bus receiver. The definition of the permissible bus protocol is shown below: 1_STA 2_STA 3_STA 4 CA CA CA CO FM CO BA FL BA STO STO FM FL STO 4_STA CA FM FL CO BA STO STA = Start Condition STO = Stop Condition CA = Chip Address Byte CO = Data Byte for Control Information BA = Band Information FM = Data Byte for Frequency Information (MSB’s) FL = Data Byte for Frequency Information (LSB’s) MOTOROLA ANALOG IC DEVICE DATA MC44824/25 Figure 3. Complete Data Transfer Process SDA SCL 1–7 8 9 1–7 8 9 1–7 8 9 S STA P ADDRESS CA R/W ACK DATA ACK DATA ACK STO The first and the third data bytes contain a function bit which allows the IC to distinguish between frequency information and control plus band information. Frequency information is preceded by a Logic “0”. If the function bit is Logic “1” the two following bytes contain control and band information. The first data byte, shifted after the chip address, may be byte CO or byte FM. The two permissible bus protocols with five bytes are shown in Figure 4. Figure 4 shows the five bytes of information that are needed for circuit operation: there is the chip address, two bytes of control and band information and two bytes of frequency information. After the chip address, two or four data bytes may be received: if three data bytes are received, the third data byte is ignored. If five or more data bytes are received, the fifth and following data bytes are ignored and the last acknowledge pulse is sent at the end of the fourth data byte. Figure 4. Definition of Bytes CA_Chip Address CO_Information BA_Band Information FM_Frequency Information ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ FL_Frequency Information CA_Chip Address FM_Frequency Information FL_Frequency Information CO_Information 1 1 0 0 0 0/1 0/1 0 ACK 1 T14 T13 T12 T11 T10 T9 T8 ACK B7 X X B4* X B2 B1 B0* ACK 0 N14 N13 N12 N11 N10 N9 N8 ACK N7 N6 N5 N4 N3 N2 N1 N0 ACK ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ BA_Band Information 1 1 0 0 0 0/1 0/1 0 ACK 0 N14 N13 N12 N11 N10 N9 N8 ACK N7 N6 N5 N4 N3 N2 N1 N0 ACK 1 T14 T13 T12 T11 T10 T9 T8 ACK B7 X X B4* X B2 B1 B0* ACK * B0 and B4 are only available on MC44825. On MC44824 this data is random. Chip Address The chip address is programmable by Pin 7 (8), CA. CA – Pin 7 (8) Address (HEX.) Gnd to 0.1 VCC1 C0 Open or 0.2 VCC1 to 0.3 VCC1 C2 0.4 VCC1 to 0.7 VCC1 C4 0.8 VCC1 to 1.1 VCC1 C6 Bits B0, B1, B2, B4, B7: Control the Band Buffers B0, B1, B2, B4, B7 = 0 B0, B1, B2, B4, B7 = 1 Buffer “Off” Buffer “On” MOTOROLA ANALOG IC DEVICE DATA Bit T8: Controls the Output of the Operational Amplifier T8 = 0 Normal Operation Operational Amplifier Active T8 = 1 Output State of Operational Amplifier Switched “Off”, Output Pulls High Through an External Pull–Up Resistor Bits T9, T12: Control the Phase Comparator T9 T12 1 1 0 0 0 1 0 1 Function Normal Operation High Impedance Upper Source “On” Only Lower Source “On” Only 5 MC44824/25 Bits T10, T11: Control the Reference Ratio T10 T11 0 0 1 1 0 1 0 1 Division Ratio 512 1024 1024 512 Bit T13: Switches the Internal Signals Fref and FBY2 to Bit T13: the Band Buffer Outputs (Test) T13 = 0 T13 = 1 Normal Operation Test Mode Fref Output at B7 FBY2 Output at B2 Bits B2 and B7 have to be “Off”, B2 = B7 = 0 in the test mode. Fref is the reference frequency. FBY2 is the output frequency of the programmable divider, divided by two. Bit T14: Controls the Charge Pump Current of the Bit T14: Phase Comparator Pump Current 125 µA Typical The Band Buffers BA_Band Information MC44824 14 Pin version B7 X X X X B2 B1 X ACK X B2 B1 B0 ACK MC44825 16 Pin version B7 X X B4 The band buffers are open collector buffers and are active “low” at Bn = 1. They are designed for 10 mA with a typical “On” resistance of 160 Ω. These buffers are designed to withstand relative high output voltage in the “Off” state. B2 and B7 buffers may also be used to output internal IC signals (reference frequency and programmable divider output frequency divided by 2) for test purposes. The bit B2 and/or B7 have to be zero if the buffers are used for these additional functions. The Programmable Divider The programmable divider is a presettable down counter. When it has counted to zero it takes its required division ratio out of the latches B. Latches B are loaded from latches A by means of signal TDI which is synchronous to the programmable divider output signal. Since latches A receive the data asynchronously with the programmable divider, this double latch scheme is needed to assure correct data transfer to the counter. 6 The Prescaler The prescaler has a preamplifier which guarantees high input sensitivity. The Phase Comparator The phase comparator is phase and frequency sensitive and has very low output leakage current in the high impedance state. Pump Current 40 µA Typical T14 = 0 T13 = 1 The division ratio definition is given by: N = 16384 x N14 + 8192 x N13 + … + 4 x N2 + 2 x N1 + N0 Maximum Ratio 32767 Minimum Ratio 17 Where N0 … N14 are the different bits for frequency information. The counter may be used for any ratio between 17 and 32767 and reloads correctly as long as its output frequency does not exceed 1.0 MHz. The data transfer between latches A and B (signal TDI) is also initiated by any start condition on the I2C bus. At power–on, the whole bus receiver is reset and the programmable divider is set to a counting ration of N = 256 or higher. The first I2C message must be sent only when the POWER ON RESET is completed. The Tuning Voltage Amplifier The amplifier is designed for very low noise, low input bias current and high power supply rejection. The positive input is biased internally. The tuning voltage amplifier needs an external NPN with a pull–up resistor to generate the tuning voltage. The amplifier can be switched “Off” through bit T8. When bit T8 is “One”, the amplifier is “Off”. The tuning voltage is then pulled high by the external pull–up resistor. Figure 5 shows a possible filter arrangement. The component values depend very much on the application (tuner characteristic, reference frequency, etc.). As a starting point for optimization, the component values in Figure 5 may be used for 7.8125 kHz reference frequency in a multiband TV tuner. The Oscillator The oscillator uses a 4.0 MHz crystal tied to ground “or between Pins 2 and 3” through a series capacitor. The crystal oscillates in its series resonance mode. The voltage at Pin 13 XTAL1, has low amplitude and low harmonic distortion. Pin XTAL2 is the internal ground of the oscillator; it is connected internally to ground Pin 13 (15). MOTOROLA ANALOG IC DEVICE DATA MC44824/25 Figure 5. Typical Tuner Applications UHF VHF B III 6 IF 5.0 V 10 Antenna Filter 8 B7 9 B2 B1 Mixer B. P. Filter 1.0 nF 12 11 5 4 7 Bus Rec MC44824 ÷8 Pres Program Divider Osc & 2 Ref Div Fosc 1.0 nF Gnd 13 Oscillator Phase Comp 2.7 V 16 3 SCL SDA CA 12 pF 3.2/4.0 MHz 1 33 V AGC 22 k VTUN 47 k 47 nF 330 p (See Note) 22 nF External Switching UHF VHF B III 7 IF 5.0 V 12 Antenna Filter B4 9 B2 10 B1 11 B0 6 B7 Mixer B. P. Filter 1.0 nF 14 13 5 4 8 Bus Rec MC44825 ÷8 Pres Program Divider Osc & 2 Ref Div Fosc 1.0 nF Gnd 15 Oscillator 2.7 V 16 Phase Comp 3 SCL SDA CA 12 pF 3.2/4.0 MHz 1 33 V AGC VTUN 22 k 47 k 330 p (See Note) 47 nF 22 nF NOTE: C2 = 330 pF minimum is required for stability. MOTOROLA ANALOG IC DEVICE DATA 7 MC44824/25 OUTLINE DIMENSIONS D SUFFIX PLASTIC PACKAGE CASE 751A–03 (SO–14) ISSUE F –A– 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 –B– 1 P 7 PL 0.25 (0.010) 7 G B M M R X 45 _ C F –T– 0.25 (0.010) M T B J M K D 14 PL SEATING PLANE A S S D SUFFIX PLASTIC PACKAGE CASE 751B–05 (SO–16) ISSUE J –A– 16 9 1 8 –B– P 0.25 (0.010) M B S R K F X 45 _ C SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL G –T– DIM A B C D F G J K M P R J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 8 ◊ *MC44824/D* MOTOROLA ANALOG IC DEVICE DATA MC44824/D