Order this document by MC44829/D The MC44829 is a tuning circuit for TV and VCR tuner applications. It contains, on one chip, all the functions required for PLL control of a VCO. This integrated circuit also contains a high frequency prescaler and thus can handle frequencies up to 1.3 GHz. The circuit has a band decoder that provides the band switching signal for the mixer/oscillator circuit. The decoder is controlled by the buffer bits. The MC44829 has programmable 512/1024 reference dividers and is manufactured on a single silicon chip using Motorola’s high density bipolar process, MOSAIC (Motorola Oxide Self Aligned Implanted Circuits). • • • • • • • • • • TV AND VCR I2C PLL TUNING CIRCUIT WITH 1.3 GHz PRESCALER AND MIX/OSC DECODER SEMICONDUCTOR TECHNICAL DATA Complete Single Chip System for MPU Control (I2C Bus) Divide–by–8 Prescaler Accepts Frequencies up to 1.3 GHz 15 Bit Programmable Divider Reference Divider: Programmable for Division Ratios 512 and 1024 3–State Phase/Frequency Comparator 14 Operational Amplifier for Direct Tuning Voltage Output (30 V) 1 Four Programmable Chip Addresses D SUFFIX PLASTIC PACKAGE CASE 751A (SO–14) Integrated Band Decoder for the Mixer/Oscillator Circuit Band Buffers with Low “On” Voltage (0.4 V Maximum at 5.0 mA) Fully ESD Protected to MIL–STD–883C, Method 3015.7 (2000 V, 1.5 kΩ, 150 pF) PIN CONNECTIONS MOSAIC is a trademark of Motorola, Inc. MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.) Rating Pin Value Unit 5 6.0 V Band Buffer “Off” Voltage 6, 7, 8 15 V Band Buffer “On” Current 6, 7, 8 10 mA 1 40 V Power Supply Voltage (VCC1) Operational Amplifier Power Supply (VCC2) RF Input Level 10 MHz to 1.3 GHz 3, 4 1.5 Vrms Storage Temperature – –65 to +150 °C Operating Temperature Range – –20 to +80 °C Bus Input Voltage (Positive) 10, 11 7.0 V Bus Input Voltage (Negative) 10, 11 –0.5 V VTUN 1 14 PHO Gnd 2 13 Xtal HF1 3 12 DEC HF2 4 11 SDA VCC1 5 10 SCL B4 6 9 CA B5 7 8 B6 (Top View) ORDERING INFORMATION Device Operating Temperature Range Package MC44829D TA = –20° to +80°C SO–14 Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA Rev 1 1 MC44829 Representative Block Diagram VTUN VCC2 RL CL Bands Out VCC1 5.0 V DEC 5 12 8 Mixer/Oscillator Band Decoder Fout Fref Test Logic DTB1 Gnd B6 7 6 B5 Buffers 14 B4 PHO 2.7 V Operational Amplifier Latches T8 T13 2 1 Phase Comp T9, T12, T14 T10, T11 DTB2 P–On Reset Latches Fout Fref POR CA SDA SCL 9 I2C Bus Receiver 11 10 CL Data RL DTF 3 Shift Register 15 Bit 512/1024 7 Ref Divider Latches A Osc 12 pF Latches B HF1 HF2 3 4 13 Xtal TDI 3.2/4.0 MHz Preamp ÷8 Prescaler Program Divider 15 Bit Fout Latch Control DTS, EN This device contains 3,204 active transistors. 2 MOTOROLA ANALOG IC DEVICE DATA MC44829 ELECTRICAL CHARACTERISTICS (VCC1 = 5.0 V, VCC2 = 33 V, TA = 25°C, unless otherwise noted.) Characteristic Pin Min Typ Max Unit VCC1 Supply Voltage Range 5 4.5 5.0 5.5 V VCC1 Supply Current (VCC1 = 5.0 V) 5 25 35 50 mA Band Buffer Leakage Current when “Off” at 12 V 6, 7, 8 – 0.01 1.0 µA Band Buffer Saturation Voltage when “On” at 5.0 mA 6, 7, 8 – 0.16 0.4 V Data/Clock Current at 0 V (Acknowledge “Off”) 10, 11 –10 – 0 µA Data/Clock Current at 5.0 V (Acknowledge “Off”) 10, 11 0 – 1.0 µA Data/Clock Input Voltage Low 10, 11 – – 1.5 V Data/Clock Input Voltage High 10, 11 3.0 – – V Data Saturation Voltage at 3.0 mA (Acknowledge “On”) 11 – 0.25 0.4 V Decoder “High” Level Sourcing 100 µA 12 3.4 – VCC1 V Decoder “Medium” Level Sourcing 15 µA 12 1.8 – 2.1 V Decoder “Low” Level Sinking 20 µA 12 0 – 0.8 V Clock Frequency Range 10 – – 100 kHz Oscillator Frequency Range 13 3.15 3.2 4.05 MHz Operational Amplifier Internal Reference Voltage – 2.0 2.75 3.2 V Operational Amplifier Input Current 14 –15 0 15 nA DC Open Loop Gain (RL = 22 kΩ) 14, 1 100 250 1000 V/V Gain Bandwidth Product (CL = 0.5 nF) 14, 1 0.3 – – MHz Vout Low (RL = 22 kΩ) 1 – 0.45 0.65 V Phase Detector Tri–State Current 14 –15 0 15 nA Charge Pump Current of Phase Comparator (T14 = 0) 14 30 40 50 µA Charge Pump Current of Phase Comparator (T14 = 1) 14 90 125 150 µA VCC2 Supply Voltage Range 1 25 33 36 V PIN FUNCTION DESCRIPTION Pin Function Description 1 VTUN/VCC2 2 Gnd 3, 4 HF1/ HF2 5 VCC1 6, 7, 8 B4, B5, B6 9 CA Chip address selection pin 10 SCL Clock input of the I2C bus 11 SDA Data input 12 DEC Band decoder output for the mixer/oscillator circuit 13 Xtal Crystal input 14 PHO Input of tuning voltage amplifier Output of the tuning voltage amplifier. Needs an external pull–up resistor to drive the varicaps Ground Symmetric HF inputs from local oscillator Supply voltage. Typical 5.0 V Band buffer outputs MOTOROLA ANALOG IC DEVICE DATA 3 MC44829 Figure 1. Typical Prescaler Input Sensitivity 5.0 RF Level (dBm) –5.0 Guaranteed Operating Area –15 –25 –35 –45 0 200 600 400 800 1000 1200 1400 RF In (MHz) NOTE: VCC = 4.5 to 5.5 V, TA = – 20° to +80°C HF CHARACTERISTICS (See Figure 1) Pin Min Typ Max Unit DC Bias 3, 4 – 1.6 – V Input Voltage Range 50–950 MHz 950–1300 MHz 3, 4 3, 4 10 50 – – 315 315 Characteristic mVrms Figure 2. RF Sensitivity Test Circuit I2C Bus Controller ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ 10, 11 +5.0 V VCC1 2 MC44829 5 3 4 B5 4.0 k B6 HF In RF Generator (50 Ω) 7 8 1.0 nF 1.0 nF +12 V 4.0 kΩ 50 Ω Frequency Counter Device is in test mode, B5 and B6 are “On”, B4 is “Off”. Sensitivity is the level of the HF generator of 50 Ω load. 4 MOTOROLA ANALOG IC DEVICE DATA MC44829 Figure 3. Typical HF Input Impedance –j +j 0 0.5 0.5 0.5 ZO = 50 Ω 1.3 GHz 1 1 1 1.0 GHz 2 2 2 500 MHz 50 MHz Data Format and Bus Receiver The circuit receives the information for tuning and control via the I2C bus. The incoming information, consisting of a chip address byte followed by two or four data bytes, is treated in the I2C bus receiver. The definition of the permissible bus protocol is shown below: 1_STA 2_STA 3_STA 4_STA CA CA CA CA CO FM CO FM BA FL BA FL STO STO FM FL CO BA STA = Start Condition STO = Stop Condition CA = Chip Address Byte CO = Data Byte for Control Information BA = Band Information FM = Data Byte for Frequency Information (MSB’s) FL = Data Byte for Frequency Information (LSB’s) STO STO Figure 4. Complete Data Transfer Process SDA SCL 1–7 8 9 R/W ACK 1–7 8 9 1–7 8 9 S STA P ADDRESS CA MOTOROLA ANALOG IC DEVICE DATA DATA ACK DATA ACK STO 5 MC44829 The two permissible bus protocols with five bytes are shown in Figure 5. The Data and Clock inputs (Pins 10 and 11) are high impedance when the supply voltage VCC1 is between 0 and 5.5 V. Figure 5 shows the five bytes of information that are needed for circuit operation: there is the chip address, two bytes of control and band information and two bytes of frequency information. After the chip address, two or four data bytes may be received: if three data bytes are received the third data byte is ignored. If five or more data bytes are received the fifth and following data bytes are ignored and the last acknowledge pulse is sent at the end of the fourth data byte. The first and the third data bytes contain a function bit which allows the IC to distinguish between frequency information and control plus band information. Frequency information is preceded by a Logic “0”. If the function bit is Logic “1” the two following bytes contain control and band information. The first data byte, shifted after the chip address, may be byte CO or byte FM. Chip Address The chip address is programmable by Pin 9 (CA – Address Select). CA – Pin 9 Address (HEX.) –0.04 VCC1 to 0.1 VCC1 C0 Open or 0.2 VCC1 to 0.3 VCC1 C2 0.42 VCC1 to 0.75 VCC1 C4 0.9 VCC1 to 1.2 VCC1 C6 Figure 5. Definition of Bytes CA_Chip Address CO_Information BA_Band Information FM_Frequency Information FL_Frequency Information CA_Chip Address FM_Frequency Information FL_Frequency Information CO_Information BA_Band Information 6 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 1 1 0 0 0 0/1 0/1 0 ACK 1 T14 T13 T12 T11 T10 T9 T8 ACK X B6 B5 B4 X X X X ACK 0 N14 N13 N12 N11 N10 N9 N8 ACK N7 N6 N5 N4 N3 N2 N1 N0 ACK ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 1 1 0 0 0 0/1 0/1 0 ACK 0 N14 N13 N12 N11 N10 N9 N8 ACK N7 N6 N5 N4 N3 N2 N1 N0 ACK 1 T14 T13 T12 T11 T10 T9 T8 ACK X B6 B5 B4 X X X X ACK MOTOROLA ANALOG IC DEVICE DATA MC44829 Figure 6. Typical Tuner Application IF UHF VHF B III PNP Current Buffers M/O 12 Antenna Filter 8 5.0 V 5 Band Decoder Mixer 7 B6 6 B5 B4 1.0 nF Fosc 3 ÷8 Pres 4 Oscillator MC44829 Gnd 2 2.7 V 1 VTUN NOTE: C2 = 330 pF minimum is required for stability. Bits B4, B5, B6: Control the Band Buffers Buffer “Off” Buffer “On” Bit T8: Controls the Output of the Operational Amplifier T8 = 0 Normal Operation Operational Amplifier Active T8 = 1 Output State of Operational Amplifier Switched “Off”, Output Pulls High Through the External Pull–Up Resistor RL Bits T9, T12: Control the Phase Comparator T9 T12 1 1 0 0 0 1 0 1 Function Normal Operation High Impedance (Tri–State) Upper Source “On” Only Lower Source “On” Only 12 pF 3.2/4.0 MHz Phase Comp 14 RL 33 V AGC SDA SCL CA Osc & 13 Ref Div Program Divider 1.0 nF B4, B5, B6 = 0 B0, B1, B3 = 1 11 10 9 Bus Rec B. P. Filter 47 k 47 nF 22 nF 330 p (Note) Bit T14: Controls the Charge Pump Current of the Bit T14: Phase Comparator T14 = 0 T13 = 1 Pump Current 40 µA Typical Normal Operation. Pump Current 125 µA Typical Mixer/Oscillator Band Decoder The band decoder provides the band switching signal for the mixer/oscillator circuit. The buffer bits B4 and B6 control the decoder output. B5 is not decoded. The decoder is controlled by the buffer bits as per the table below. B6 B5 B4 0 0 X X 0 1 1 1 X X 0 1 Decoder Output DEC Undefined 3.4 V to VCC1 (VCC1 = 4.5 to 5.5 V) 0 to 0.8 V 1.8 to 2.1 V BA_Band Information Bits T10, T11: Control the Reference Divider T10 T11 0 0 1 1 0 1 0 1 Division Ratio 512 1024 1024 512 Bit T13: Switches the Internal Signals Fref and FBY2 to Bit T13: the Band Buffer Outputs (Test) T13 = 0 T13 = 1 Normal Operation Test Mode Fref Output at B5 (Pin 7) FBY2 Output at B6 (Pin 8) Bits B5 and B6 have to be “On”, B5 = B6 = 1 in the test mode. Fref is the reference frequency. FBY2 is the output frequency of the programmable divider, divided by two. MOTOROLA ANALOG IC DEVICE DATA X B6 B5 B4 X X X X ACK The band buffers are open collector buffers and are active “low” at Bn = 1. They are designed for 5.0 mA with a typical “on” voltage of 160 mV. These buffers are designed to withstand relative high output voltage in the “off” state. B5 and B6 buffers may also be used to output internal IC signals (reference frequency and programmable divider output frequency divided by 2) for test purposes. The bit B5 and/or B6 have to be one if the buffers are used for these additional functions. The Programmable Divider The programmable divider is a presettable down counter. When it has counted to zero it takes its required division ratio out of the latches B. Latches B are loaded from latches A by means of signal TDI which is synchronous to the programmable divider output signal. 7 MC44829 Since latches A receive the data asynchronously with the programmable divider, this double latch scheme is needed to assure correct data transfer to the counter. The division ratio definition is given by: N = 16384 x N14 + 8132 x N13 + … + 4 x N2 + 2 x N1 + N0 Maximum Ratio 32767 Minimum Ratio 256 Where N0 … N14 are the different bits for frequency information. The counter may be used for any ratio between 256 and 32767 and reloads correctly as long as its output frequency does not exceed 1.0 MHz. The data transfer between latches A and B (signal TDI) is also initiated by any start condition on the I2C bus. At power “on” the whole bus receiver is reset and the bit N8 of the programmable divider is set to N8 = 1. Thus the programmable divider starts with a division ratio of 256 or higher. The first I2C message must be sent only when the POWER ON RESET is completed. Division ratios of N < 256 are not allowed. The Prescaler The prescaler has a preamplifier which guarantees high input sensitivity. 8 The Phase Comparator The phase comparator is phase and frequency sensitive and has very low output leakage current in the high impedance state. The Tuning Voltage Amplifier The amplifier is designed for very low noise, low input bias current and high power supply rejection. The positive input is biased internally. The tuning voltage amplifier needs an external pull–up resistor to generate the tuning voltage. The amplifier can be switched “off” through bit T8. When bit T8 is “One”, the amplifier is “Off”. The tuning voltage is then pulled high by the external pull–up resistor. Figure NO TAG shows a possible filter arrangement. The component values depend very much on the application (tuner characteristic, reference frequency, etc.). The Oscillator The oscillator uses a 3.2 or 4.0 MHz crystal tied to ground in series with a capacitor. The crystal operates in its series resonance mode. The voltage at Pin 13, has low amplitude and low harmonic distortion. The negative impedance of the crystal input (Pin 13) is about 3.0 kΩ. MOTOROLA ANALOG IC DEVICE DATA MC44829 OUTLINE DIMENSIONS D SUFFIX PLASTIC PACKAGE CASE 751A–03 (SO–14) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 14 8 –B– 1 P 7 PL 0.25 (0.010) 7 G M F –T– D 14 PL 0.25 (0.010) M K M T B MOTOROLA ANALOG IC DEVICE DATA S M R X 45 _ C SEATING PLANE B A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 9 MC44829 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 10 ◊ *MC44829/D* MOTOROLA ANALOG IC DEVICE DATA MC44829/D