MC54/74F253 DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS The MC54/74F253 is a Dual 4-Input Multiplexer with 3-State Outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high-impedance state with a HIGH on the respective Output Enable (OE) inputs, allowing the outputs to interface directly with bus-oriented systems. DUAL 4-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS FAST SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) VCC OEb S0 I3b I2b I1b I0b Zb 16 15 14 13 12 11 10 9 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 1 2 3 4 5 6 7 8 OEa S1 I3a I2a I1a I0a Za GND D SUFFIX SOIC CASE 751B-03 16 1 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA Parameter Supply Voltage Min Typ Max Unit 54, 74 4.5 5.0 5.5 V 54 –55 25 125 °C 74 0 25 70 Operating Ambient Temperature Range IOH Output Current — High 54, 74 –3.0 mA IOL Output Current — Low 54, 74 24 mA FAST AND LS TTL DATA 4-120 MC54/74F253 LOGIC DIAGRAM OEb 15 13b 12b 13 11b 12 10b 11 S0 S1 10 14 13a 2 12a 3 11a 4 OEa 10a 5 6 1 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Zb Za 9 7 FUNCTIONAL DESCRIPTION The F253 contains two identical 4-input Multiplexers with 3-State Outputs. They select two bits from four sources selected by common Select Inputs (S0, S1). The 4-input multiplexers have individual Output Enable (OEa, OEb) inputs which, when HIGH, force the outputs to a high impedance (high Z) state. The F253 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown below: Za = OEa • (I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + 13a • S1 • S0) Zb = OEb • (I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0) If the outputs of 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap. FUNCTION TABLE Select Inputs Data Inputs Output Enable Output S0 S1 I0 I1 I2 I3 OE Z X X X X X X H Z L L L X X X L L L L H X X X L H H L X L X X L L H L X H X X L H L H X X L X L L L H X X H X L H H H X X X L L L H H X X X H L H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance (off) Address inputs S0 and S1 are common to both sections. FAST AND LS TTL DATA 4-121 MC54/74F253 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage Min Typ Max Unit 2.0 Test Conditions V Guaranteed Input HIGH Voltage 0.8 V Guaranteed Input LOW Voltage –1.2 V IIN = –18 mA VCC = MIN 54, 74 2.4 V IOH = –3.0 mA VCC = 4.50 V 74 2.7 V IOH = –3.0 mA VCC = 4.75 V 0.5 V IOL = 24 mA VCC = MIN VOL Output LOW Voltage IOZH Output Off Current — HIGH 50 µA VOUT = 2.7 V VCC = MAX IOZL Output Off Current — LOW –50 µA VOUT = 0.5 V VCC = MAX IIH Input HIGH Current 20 µA VIN = 2.7 V VCC = MAX 100 µA VIN = 7.0 V –0.6 mA VIN = 0.5 V VCC = MAX –150 mA VOUT = 0 V VCC = MAX IIL Input LOW Current IOS Output Short Circuit Current (Note 2) –60 Power Supply Current ICC OEn = GND Total, Output HIGH 16 Total, Output LOW 23 Total at HIGH-Z 23 IO = 4.5 V; Sn, I1 – I3 = GND mA In, Sn, OEn = GND VCC = MAX OEn = 4.5 V, VCC = MAX In, Sn = GND AC CHARACTERISTICS Symbol Parameter 54/74F 54F 74F TA = +25°C TA = -55°C to +125°C TA = 0°C to +70°C VCC = +5.0 V VCC = 5.0 V ± 10% VCC = 5.0 V ± 10% CL = 50 pF CL = 50 pF CL = 50 pF Min Max Min Max Min Max Unit ns tPLH Propagation Delay 4.5 11.5 3.5 15 4.5 13.5 tPHL Sn to Zn 3.0 9.0 2.5 11 3.0 10 tPLH Propagation Delay 3.0 7.0 2.5 9.0 3.0 8.0 tPHL In to Zn 2.5 6.0 2.5 8.0 2.5 7.0 tPZH Output Enable Time 3.0 8.0 2.5 10 3.0 9.0 3.0 8.0 2.5 10 3.0 9.0 2.0 5.0 2.0 6.5 2.0 6.0 2.0 6.0 2.0 8.0 2.0 7.0 tPZL tPHZ tPLZ Output Disable Time FAST AND LS TTL DATA 4-122 ns ns ns