MOTOROLA MC74F85

MC54/74F85
4-BIT MAGNITUDE COMPARATOR
The MC54/74F85 is a 4-Bit Magnitude Comparator which compares two
4-Bit words (A0-A3, B0-B3), A3, B3 being the most significant inputs. Operation
is not restricted to binary codes; the device will work with any monotonic code.
Three Outputs are provided: “A greater than B” (0A > B), “A less than B” (0A
< B), “A equal to B” (0A = B). Three Expander Inputs, IA > B, IA < B, IA = B, allow
cascading without external gates. For proper compare operation, the Expander Inputs to the least significant position must be connected as follows: IA <
B = IA > B = L, IA = B = H. For serial (ripple) expansion the 0A > B, 0A < B Outputs
are connected respectively to the IA > B and IA = B inputs of the next most significant comparator, as shown in Figure 1. Refer to applications section of
data sheet for high speed method of comparing large words.
4-BIT MAGNITUDE COMPARATOR
FAST SCHOTTKY TTL
• High Impedance NPN Base Inputs for Reduced Loading (20 µA in
J SUFFIX
CERAMIC
CASE 620-09
HIGH and LOW States)
• Magnitude Comparison of any Binary Words
• Serial or Parallel Expansion Without Extra Gating
• ESD > 4000 Volts
16
1
CONNECTION DIAGRAM
VCC
A3
B2
A2
A1
B1
A0
B0
16
15
14
13
12
11
10
9
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
16
1
2
3
4
5
6
7
8
B3
IA<B
IA=B
IA>B
A>B
A=B
A<B
GND
1
ORDERING INFORMATION
MC74FXXJ
MC74FXXN
MC74FXXD
Ceramic
Plastic
SOIC
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA
Operating Ambient Temperature Range
Min
Typ
Max
Unit
54, 74
4.5
5.0
5.5
V
54
–55
25
125
°C
74
0
25
70
IOH
Output Current  High
54, 74
–1.0
mA
IOL
Output Current  Low
54, 74
20
mA
FAST AND LS TTL DATA
4-36
MC54/74F85
FUNCTION TABLE
Comparing Inputs
Expansion Inputs
Outputs
A3, B3
A2, B2
A1, B1
A0, B0
IA > B
IA < B
IA = B
A>B
A<B
A=B
A3 > B3
X
X
X
X
X
X
H
L
L
A3 < B3
X
X
X
X
X
X
L
H
L
A3 = B3
A2 > B2
X
X
X
X
X
H
L
L
A3 = B3
A2 < B2
X
X
X
X
X
L
H
L
A3 = B3
A2 = B2
A1 > B1
X
X
X
X
H
L
L
A3 = B3
A2 = B2
A1 < B1
X
X
X
X
L
H
L
A3 = B3
A2 = B2
A1 = B1
A0 > B0
X
X
X
H
L
L
A3 = B3
A2 = B2
A1 = B1
A0 < B0
X
X
X
L
H
L
A3 = B3
A2 = B2
A1 = B1
A0 = B0
H
L
L
H
L
L
A3 = B3
A2 = B2
A1 = B1
A0 = B0
L
H
L
L
H
L
A3 = B3
A2 = B2
A1 = B1
A0 = B0
L
L
H
L
L
H
A3 = B3
A2 = B2
A1 = B1
A0 = B0
X
X
H
L
L
H
A3 = B3
A2 = B2
A1 = B1
A0 = B0
H
H
L
L
L
L
A3 = B3
A2 = B2
A1 = B1
A0 = B0
L
L
L
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min
Typ
Max
2.0
Unit
Test Conditions
VIH
Input HIGH Voltage
V
Guaranteed Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage
VIK
Input Clamp Diode Voltage
–1.2
V
VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
V
IOH = –1.0 mA
54, 74
2.5
74
2.7
VCC = 4.50 V
VCC = 4.75 V
VOL
Output LOW Voltage
0.5
V
IOL = 20 mA, VCC = MIN
IIH
Input HIGH Current
20
µA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = 0 V, VIN = 7.0 V
–20
µA
VCC = MAX, VIN = 0.5 V
–150
mA
VCC = MAX, VOUT = 0 V
HIGH VIN = HIGH
50
mA
VCC = MAX
LOW An = Bn = IA-B = GND: IA>B = IA<B = 4.5 V
54
IIL
Input LOW Current
IOS
Output Short Circuit Current (Note 2)
–60
Total Supply Current
ICC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
4-37
MC54/74F85
(MSB) B23
A23
B3
A3
B22
B2
A22
A2
B21
A21
B1
A1
A<B
A=B
B20
B0
A>B
A20
B19
A0
A19
IA < B
IA = B
IA > B
B18
A18
B3
A3
B17
A17
B2
B16
A16
B1
A1
A<B
A=B
B15
A15
B0
A>B
L
The parallel expansion scheme shown in Figure 1 demonstrates the most efficient general use of these comparators.
In the parallel expansion scheme, the expansion inputs can
be used as a fifth input bit position except on the least significant device which must be connected as in the Serial
Scheme. The expansion inputs are used by labelling IA>B
as an “A” input, IA<B as a “B” input and setting IA=B low. The
‘F85 can be used as a 5-bit comparator only when the outputs are used to drive the (A0-A3) and (B0-B3) inputs of
another ‘F85 device. The parallel technique can be expanded to any number of bits as shown in Table 1.
NC
A2
NC
A0
A14
IA < B
IA = B
IA > B
B13
A13
B3
A3
B3
A3
B12
A12
B2
B2
B11
A11
B1
A1
A<B
A=B
B10
A10
B0
A>B
B14
L
A2
A2
NC
A0
A9
B8
A8
B3
A3
B7
A7
B2
B6
A6
B1
A1
A<B
A=B
B5
A5
B0
A>B
L
A<B
A=B
B0
A>B
OUTPUTS
A0
IA < B
IA = B
IA > B
B9
B1
A1
A<B
A=B
A>B
A2
NC
Table 1
A0
B4
L
A4
IA < B
IA = B
IA > B
B3
A3
B3
A3
B2
A2
B2
B1
A1
B1
A1
A<B
A=B
(LSB) B0
A0
B0
A>B
Word
Length
Number of
Packages
Typical Speeds
74F
1–4 Bits
1
12 ns
5–25 Bits
2–6
22 ns
25–120 Bits
8–31
34 ns
A2
A0
L
H
L
IA < B
IA = B
IA > B
Figure 1. Comparison of Two 24-Bit Words
FAST AND LS TTL DATA
4-38
MC54/74F85
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
54/74F
54F
74F
TA = +25°C
VCC = +5.0 V
CL = 50 pF
TA = –55°C to +125°C
VCC = 5.0 V ± 10%
CL = 50 pF
TA = 0°C to + 70°C
VCC = 5.0 V ± 10%
CL = 50 pF
Min
Max
Min
Max
Min
Max
tPLH
A or B Input to
6.0
11
5.5
14
5.5
13
tPHL
A < B, A > B Output
6.0
14
5.5
16.5
5.5
15.5
tPLH
A or B Input to
5.5
11.5
5.0
15
5.0
14
tPHL
A = B Output
7.0
14
6.5
15.5
6.5
14.5
tPLH
IA<B and IA=B Input
3.0
7.5
2.5
10
2.5
9.0
tPHL
to A>B Output
3.0
9.0
2.5
11
2.5
10
tPLH
IA=B Input to
2.5
7.0
2.0
10
2.0
9.0
tPHL
A = B Output
3.5
10
2.5
13
2.5
12
tPLH
IA>B and IA=B Input
3.0
8.0
3.0
10.5
3.0
9.5
tPHL
to A<B Output
3.0
9.0
2.0
10.5
2.0
9.5
Unit
ns
ns
ns
ns
ns
The expansion inputs IA>B, IA=B, and IA<B are the least significant bit positions. When used for series expansion, the
A>B, A=B, and A<B outputs of the least significant word are
connected to the corresponding IA>B, IA=B, and IA<B inputs of
the next higher stage. Stages can be added in this manner
to any length, but a propagation delay penalty of about 15 ns
is added with each additional stage. For proper operation the
expansion inputs of the least significant word should be tied
as follows: IA>B = LOW, IA=B = HIGH, and IA<B = LOW.
A3 (15)
B3
(1)
(5)
A>B
A2 (13)
B2 (14)
(2)
IA < B
IA = B (3)
(6)
A=B
IA > B
(4)
A1 (12)
B1 (11)
(7)
A<B
A0 (10)
B0
(9)
NOTE:
This diagram is provided only for the understanding of logic operations and should not be used
to estimate propagation delays.
Figure 2. Logic Diagram
FAST AND LS TTL DATA
4-39