MOTOROLA MC74HC151D

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC74HC151 is identical in pinout to the LS151. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device selects one of the eight binary Data Inputs, as determined by
the Address Inputs. The Strobe pin must be at a low level for the selected
data to appear at the outputs. If Strobe is high, the Y output is forced to a low
level and the Y output is forced to a high level.
The HC151 is similar in function to the HC251 which has 3–state outputs.
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 132 FETs or 33 Equivalent Gates
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
DATA
INPUTS
4
D1
3
D2
2
D3
1
5 Y
6 Y
1
16
D2
2
15
VCC
D4
D1
3
14
D5
D0
4
13
D6
Y
5
12
D7
Y
6
11
A0
STROBE
7
10
A1
GND
8
9
A2
FUNCTION TABLE
Inputs
Outputs
A2
A1
A0
Strobe
Y
Y
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
L
D0
D1
D2
D3
D4
D5
D6
D7
H
D0
D1
D2
D3
D4
D5
D6
D7
A0 11
10
A1
A2 9
STROBE
D3
DATA
OUTPUTS
D4 15
D5 14
D6 13
D7 12
ADDRESS
INPUTS
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
D0
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
7
PIN 16 = VCC
PIN 8 = GND
D0, D1, …, D7 = the level of the respective
D input.
10/95
 Motorola, Inc. 1995
1
REV 6
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MC74HC151
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
VOH
Vin = VIH
VOL
Maximum Low–Level Output
Voltage
|Iout|
|Iout|
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Iin
ICC
4.0 mA
5.2 mA
4.0 mA
5.2 mA
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC74HC151
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tPLH,
tPHL
Maximum Propagation Delay, Input D to Output Y or Y
(Figures 1, 3 and 6)
2.0
4.5
6.0
185
37
31
230
46
39
280
56
48
ns
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y or Y
(Figures 2 and 6)
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
ns
tPLH,
tPHL
Maximum Propagation Delay, Strobe to Output Y or Y
(Figures 4, 5 and 6)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Symbol
Cin
Parameter
Unit
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
36
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
Strobe (Pin 7)
D0, D1, … , D7 (Pins 4, 3, 2, 1, 15, 14, 13, 12)
Data inputs. Data on any one of these eight binary inputs
may be selected to appear on the output.
Strobe. This input pin must be at a low level for the selected data to appear at the outputs. If the Strobe pin is high,
the Y output is forced to a low level and the Y output is forced
to a high level.
CONTROL INPUTS
OUTPUTS
A0, A1, A2 (Pins 11, 10, 9)
Y, Y (Pins 5, 6)
Address inputs. The data on these pins are the binary address of the selected input (see the Function Table).
Data outputs. The selected data is presented at these pins
in both true (Y output) and complemented (Y output) forms.
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC74HC151
SWITCHING WAVEFORMS
tr
tf
VALID
90%
50%
10%
INPUT D
VCC
50%
INPUT A
GND
GND
tPLH
tPLH
tPHL
90%
50%
10%
OUTPUT Y
tPHL
OUTPUT
Y OR Y
50%
tTHL
tTLH
Figure 1.
Figure 2.
tr
tf
tf
VCC
90%
50%
10%
INPUT D
VALID
VCC
GND
tPLH
tPLH
90%
50%
10%
OUTPUT Y
VCC
90%
STROBE 50%
10%
GND
tPHL
tPHL
90%
50%
10%
Y
tTHL
tr
tTLH
tTLH
tTHL
Figure 4.
Figure 3.
TEST POINT
tr
tf
VCC
90%
50%
STROBE 10%
GND
tPHL
Y
OUTPUT
DEVICE
UNDER
TEST
tPLH
90%
50%
10%
tTHL
CL*
tTLH
* Includes all probe and jig capacitance
Figure 5.
MOTOROLA
Figure 6. Test Circuit
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC151
EXPANDED LOGIC DIAGRAM
D0
D1
4
3
D2 2
D3 1
DATA
INPUTS
5 Y
D4 15
6 Y
D5 14
DATA
OUTPUTS
D6 13
D7 12
A0 11
ADDRESS
INPUTS
A1 10
A2
STROBE
9
7
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
MC74HC151
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
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and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
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CODELINE
6
*MC74HC151/D*
MC74HC151/D
High–Speed CMOS Logic Data
DL129 — Rev 6