MOTOROLA MC74HC242

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC74HC242 is identical in pinout to the LS242. The device inputs
are compatible with Standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
This quad bus transceiver is designed for asynchronous two–way
communications between data buses. The states of the Output Enables
(A–to–B Enable and B–to–A Enable) determine both the direction of data
flow (from A to B or from B to A) and the modes of the Data Ports (input,
output, or high–impedance).
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N SUFFIX
PLASTIC PACKAGE
CASE 646–06
14
1
ORDERING INFORMATION
MC74HCXXXN
Plastic
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
FUNCTION TABLE
Operating Voltage Range: 2 to 6V
Control Inputs
Low Input Current: 1µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
A–to–B
Enable
B–to–A
Enable
A
B
H
L
H
L
H
H
L
L
O
Z
Z
I
I
Z
Z
O
Chip Complexity: 130 FETs or 32.5 Equivalent Gates
LOGIC DIAGRAM
A1
A Data
Port
A2
A3
A4
Output
EnableS
3
11
4
10
5
9
6
8
A–TO–B ENABLE
B–TO–A ENABLE
1
13
I = Input; O = Output, O = Inverting Output
Z = High Impedance
B1
B2
B Data
Port
B3
B4
Pin 14 = VCC
Pin 7 = GND
Pins 2, 12 = No Connection
Pinout: 14–Lead Plastic Package (Top View)
B–to–A
VCC Enable NC
14
13
12
1
2
A–to–B NC
Enable
B1
B2
B3
B4
11
10
9
8
3
4
5
6
7
A1
A2
A3
A4
GND
NC = No Connection
10/95
 Motorola, Inc. 1995
Data Port Status
1
REV 6
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MC74HC242
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
VI/O
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
II/O
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air
750
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Plastic DIP†
_C
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP Package
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise/Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
Parameter
–55 to 25°C
≤85°C
≤125°C
Unit
VIH
Minimum High–Level Input Voltage
Vout = 0.1V or VCC –0.1V
|Iout| ≤ 20µA
2.0
4.5
6.0
1.50
3.15
4.20
1.50
3.15
4.20
1.50
3.15
4.20
V
VIL
Maximum Low–Level Input Voltage
Vout = 0.1V or VCC – 0.1V
|Iout| ≤ 20µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout| ≤ 20µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
VOH
Condition
Vin =VIH or VIL
VOL
Maximum Low–Level Output
Voltage
|Iout| ≤ 6.0mA
|Iout| ≤ 7.8mA
Vin = VIH or VIL
|Iout| ≤ 20µA
Vin = VIH or VIL
|Iout| ≤ 6.0mA
|Iout| ≤ 7.8mA
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
±0.1
±1.0
±1.0
µA
IOZ
Maximum Three–State Leakage
Current
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
±0.5
±5.0
±10.0
µA
Vin = VCC or GND
6.0
8
80
160
µA
Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ICC
MOTOROLA
Maximum Quiescent Supply
Current (per Package)
2
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC242
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Guaranteed Limit
VCC
V
–55 to 25°C
≤85°C
≤125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, A to B or B to A
(Figures 2 and 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output A or B
(Figures 3 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output A or B
(Figures 3 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
Maximum Input Capacitance
10
10
10
pF
Maximum Three–State Output Capacitance (Output in High Impedance
State)
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Transceiver)*
pF
31
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
DATA PORTS
CONTROL INPUTS
A1–A4 (Pins 3,4,5,6) and B1–B4 (Pins 11,10,9,8)
A–to–B Enable (Pin 1) and B–to–A Enable (Pin 13)
Data on these pins may be transferred between data
buses. Depending upon the states of the Output Enables,
these pins may be inputs, outputs or open circuits (high–impedance).
Data on these Output Enables determine both the direction of the data flow (from A to B or from B to A) and the
states of the outputs (standard or high impedance), according to the Function Table.
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC74HC242
VCC
One of Four
Transceivers
A (I/O)
VCC
B (I/O)
A–to–B 1
Enable
B–to–A 13
Enable
Figure 1. Expanded Logic Diagram
SWITCHING WAVEFORMS
tf
tr
VCC
90%
Input A or B
Output
Enable
VCC
50%
50%
GND
50%
tPZL tPLZ
10%
High
Impedance
GND
tPHL
Output A or B
tPLH
50%
10%
90%
Output A or B
VOL
tPZH tPHZ
50%
10%
90%
Output A or B
tTLH
tTHL
VOH
50%
High
Impedance
Figure 2.
Figure 3.
TEST CIRCUITS
TEST
POINT
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
CL*
*Includes all probe and jig capacitance
Figure 4.
MOTOROLA
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
1kΩ
Figure 5.
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC242
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
14
8
1
7
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
B
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
5
*MC74HC242/D*
MC74HC242/D
MOTOROLA