SEMICONDUCTOR TECHNICAL DATA & && "!!($&! '$! $($ ! ($ & " #& !#'&% 20 High–Performance Silicon–Gate CMOS 1 The MC74HCT541A is identical in pinout to the LS541. This device may be used as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs. The HCT541A is an octal non–inverting buffer/line driver/line receiver designed to be used with 3–state memory address drivers, clock drivers, and other bus–oriented systems. This device features inputs and outputs on opposite sides of the package and two ANDed active–low output enables. • • • • • • • 1 ORDERING INFORMATION MC74HCTXXXAN MC74HCTXXXADW A2 A3 Data Inputs A4 A5 A6 A7 A8 Output Enables OE1 OE2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 Inputs Output Y Y1 OE2 A L L H X L L X H L H X X L H Z Z Y2 Y3 Y4 Non–Inverting Outputs Y5 Y6 Y7 Pinout: 20–Lead Packages (Top View) Y8 PIN 20 = VCC PIN 10 = GND VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 10/95 Motorola, Inc. 1995 OE1 Z = High Impedance X = Don’t Care 1 19 Plastic SOIC FUNCTION TABLE LOGIC DIAGRAM 2 DW SUFFIX SOIC PACKAGE CASE 751D–04 20 Output Drive Capability: 15 LSTTL Loads TTL/NMOS–Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5V Low Input Current: 1µA In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 134 FETs or 33.5 Equivalent Gates A1 N SUFFIX PLASTIC PACKAGE CASE 738–03 3–1 REV 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC74HCT541A MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit – 0.5 to + 7.0 V V Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 35 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air 750 500 mW Tstg Storage Temperature Range – 65 to + 150 _C Iin TL Plastic DIP† SOIC Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP or SOIC Package 260 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min Max Unit 4.5 5.5 V 0 VCC V – 55 + 125 _C 0 500 ns DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Figure 1) DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Guaranteed Limit VCC V –55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High–Level Input Voltage Vout = 0.1V or VCC – 0.1V |Iout| ≤ 20µA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low–Level Input Voltage Vout = 0.1V or VCC – 0.1V |Iout| ≤ 20µA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V Minimum High–Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20µA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V 4.5 3.98 3.84 3.70 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 4.5 0.26 0.33 0.40 VOH Vin = VIH or VIL VOL Maximum Low–Level Output Voltage |Iout| ≤ 6.0mA Vin = VIH or VIL |Iout| ≤ 20µA Vin = VIH or VIL |Iout| ≤ 6.0mA V Iin Maximum Input Leakage Current Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA IOZ Maximum Three–State Leakage Current Output in High Impedance State Vin = VIL or VIH Vout = VCC or GND 5.5 ±0.5 ±5.0 ±10.0 µA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0µA 5.5 4 40 160 µA Additional Quiescent Supply Current Vin = 2.4V, Any One Input Vin = VCC or GND, Other Inputs Iout = 0µA ∆ICC 5.5 ≥ –55°C 25 to 125°C 2.9 2.4 mA 1. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). 2. Total Supply Current = ICC + Σ∆ICC. MOTOROLA 3–2 High–Speed CMOS Logic Data DL129 — Rev 6 MC74HCT541A AC CHARACTERISTICS (VCC = 5.0V, CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter –55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 3) 23 28 32 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) 30 34 38 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) 30 34 38 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 12 15 18 ns Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum Three–State Output Capacitance (Output in High Impedance State) 15 15 15 pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Buffer)* pF 55 * Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). SWITCHING WAVEFORMS 3.0V tf tr OE1 or OE2 3.0V 90% INPUT A 1.3V 1.3V GND 1.3V tPZL tPLZ 10% HIGH IMPEDANCE GND tPLH tPHL OUTPUT Y 1.3V 10% 90% 1.3V OUTPUT Y VOL tPZH tPHZ 10% 90% OUTPUT Y tTHL tTLH VOH 1.3V HIGH IMPEDANCE Figure 1. Figure 2. TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ and tPZH. *Includes all probe and jig capacitance Figure 3. High–Speed CMOS Logic Data DL129 — Rev 6 1kΩ Figure 4. 3–3 MOTOROLA MC74HCT541A PIN DESCRIPTIONS INPUTS puts are enabled and the device functions as a non–inverting buffer. When a high voltage is applied to either input, the outputs assume the high impedance state. A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9) — Data input pins. Data on these pins appear in non–inverted form on the corresponding Y outputs, when the outputs are enabled. OUTPUTS Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14, 13, 12, 11) — Device outputs. Depending upon the state of the output enable pins, these outputs are either non–inverting outputs or high–impedance outputs. CONTROLS OE1, OE2 (PINS 1, 19) — Output enables (active–low). When a low voltage is applied to both of these pins, the out- LOGIC DETAIL To 7 Other Buffers VCC One of Eight Buffers INPUT A OUTPUT Y OE1 OE2 MOTOROLA 3–4 High–Speed CMOS Logic Data DL129 — Rev 6 MC74HCT541A OUTLINE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE E –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– DIM A B C D E F G J K L M N K SEATING PLANE M N E G F J D 0.25 (0.010) M T A 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S J S F R X 45 _ C –T– 18X G SEATING PLANE K M T B M M DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E –A– 20 20 PL 0.25 (0.010) 20 PL INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 High–Speed CMOS Logic Data DL129 — Rev 6 ◊ CODELINE 3–5 *MC74HCT541A/D* MC74HCT541A/D MOTOROLA