MOTOROLA MC74HC4017N

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC74HC4017 is identical in pinout to the standard CMOS
MC14017B. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC4017 uses a five stage Johnson counter and decoding logic to
provide high–speed operation. This device also has an active–high, as well
as active–low clock input.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 176 FETs or 44 Equivalent Gates
16
1
1
ORDERING INFORMATION
MC74HCXXXXN
MC74HCXXXXD
CLOCK
ENABLE
2
13
4
7
10
1
5
6
9
11
12
RESET
15
Q5
1
16
VCC
Q0
Q1
2
15
RESET
Q1
Q0
3
14
CLOCK
Q2
Q2
4
13
CLOCK ENABLE
Q3
Q6
5
12
CARRY OUT
Q7
6
11
Q9
Q3
7
10
Q4
GND
8
9
Q8
Q4
DECADE
OUTPUTS
Q5
Q6
Q7
Q8
Q9
CARRY OUT
PIN 16 = VCC
PIN 8 = GND
10/95
 Motorola, Inc. 1995
Plastic
SOIC
PIN ASSIGNMENT
3
14
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
LOGIC DIAGRAM
CLOCK
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
REV 6
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MC74HC4017
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Iin
ICC
4.0 mA
5.2 mA
4.0 mA
5.2 mA
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC74HC4017
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 9)
2.0
4.5
6.0
4.0
20
24
3.2
16
19
2.6
13
15
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 9)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock to Carry Out
(Figures 2 and 9)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
ns
tPLH,
tPHL
Maximum Propagation Delay, Reset to Q
(Figures 3 and 9)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
ns
tPLH
Maximum Propagation Delay, Reset to Carry Out
(Figures 3 and 9)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock Enable to Q
(Figures 4 and 9)
2.0
4.5
6.0
250
50
43
315
63
54
375
75
64
ns
tPLH,
tPHL
Maximum Propagation Delay, Clock Enable to Carry Out
(Figures 5 and 9)
2.0
4.5
6.0
250
50
43
315
63
54
375
75
64
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 8 and 9)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Symbol
Cin
Parameter
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
35
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
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MC74HC4017
TIMING REQUIREMENTS (Input tr = tf = 6 ns)t
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tsu
Minimum Setup Time, Clock Enable to Clock
(Figure 6)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
tsu
Minimum Setup Time, Clock Enable to Clock (Inhibit Count)
(Figure 6)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
th
Minimum Hold Time, Clock to Clock Enable
(Figure 6)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
Minimum Recovery Time, Reset to Clock
(Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tw
Minimum Pulse Width, Clock Input
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Reset Input
(Figure 3)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Clock Enable Input
(Figure 4)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
Symbol
trec
tr, tf
Parameter
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
FUNCTION TABLE
Clock
L
X
X
X
H
Clock
Enable
X
H
X
L
X
Reset
Output State*
L
L
H
L
L
L
L
no change
no change
reset counter, Q0 = H, Q1 – Q9 = L, C0 = H
advance to next state
no change
no change
advance to next state
X = Don’t care
* Carry Out = H for Q0, Q1, Q2, Q3, or Q4 = H; Carry Out = L otherwise.
PIN DESCRIPTIONS
INPUTS
negative–edge clock input. using Clock (Pin 14) as an
active–high enable pin.
Clock (Pin 14)
OUTPUTS
Counter clock input. While Clock Enable is low, a low–to–
high transition on this input advances the counter to its next
state.
Q0 – Q9 (Pins 3, 2, 4, 7, 10, 1, 5, 6, 9, 11)
Decoded decade counter outputs. Each of these outputs is
high for one clock period only.
Reset (Pin 15)
Asynchronous counter reset input. A high level at this input
initializes the counter and forces Q0 and Carry Out to a high,
Q1–Q9 are forced to a low level.
Carry Out (Pin 12)
Cascading output pin. This output is used either as a cascading output or a symmetrical divide–by–ten output. This
output goes low when a count of five is reached and high
when the counter advances to zero or when reset. When the
counters are cascaded this output provides a rising–edge
signal for the clock input of the next counter stage.
Clock Enable (Pin 13)
Active–low clock enable input. A low level on this input allows the device to count. A high level on this input inhibits the
counting operation. This input may also be used as a
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC4017
SWITCHING WAVEFORMS
tr
90%
50%
10%
CLOCK
tf
VCC
VCC
50%
CLOCK
GND
GND
tw
tw
1/fmax
tPLH
Q
tPHL
tPLH
tPHL
CARRY
OUT
90%
50%
10%
tTLH
50%
Figure 2.
tTHL
Figure 1.
tw
VCC
50%
RESET
GND
CLOCK
ENABLE
VCC
50%
GND
tPLH
50%
Q
tw
tPHL
tPHL
Figure 4.
Q1–Q9
50%
VCC
tPLH
GND
VALID
50%
Q0, CARRY OUT
CLOCK
ENABLE
VCC
50%
GND
Figure 3.
th
tsu
VCC
50%
CLOCK
GND
VCC
CLOCK
ENABLE
Figure 6.
50%
GND
tPLH
tPHL
CARRY
OUT
tTLH
90%
50%
Q0 – Q9,
CARRY OUT
tTHL
10%
Figure 5.
Figure 8.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
VCC
50%
CLOCK
GND
CL*
trec
RESET
VCC
50%
GND
* Includes all probe and jig capacitance
Figure 7.
High–Speed CMOS Logic Data
DL129 — Rev 6
Figure 9. Test Circuit
5
MOTOROLA
MC74HC4017
TIMIING DIAGRAM
CLOCK
CLOCK
ENABLE
RESET
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
CARRY
OUT
MOTOROLA
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC4017
EXPANDED LOGIC DIAGRAM
D
Q
3
C
Q
R
RESET
2
15
D
Q
C
4
7
10
14
1
5
CLOCK 13
ENABLE
Q1
Q2
Q
R
CLOCK
Q0
D
Q
C
6
Q3
Q4
Q5
Q6
Q7
Q
R
9
D
11
Q
C
Q
Q9
12 CARRY
OUT
R
D
Q8
Q
C
Q
R
High–Speed CMOS Logic Data
DL129 — Rev 6
7
MOTOROLA
MC74HC4017
TYPICAL APPLICATIONS
VCC
÷5
1
2
3
÷2
÷3
4
÷6
5
÷7
6
7
8
HC4017
VCC 16
15
RESET
Q1
14
CLOCK
Q0
CLOCK 13
Q2
ENABLE
12
Q6
CARRY OUT
11
Q7
Q9
10
Q4
Q3
9
Q8
GND
Q5
OSC.
÷ 10
(NO FEEDBACK REQUIRED)
÷9
÷4
÷8
1/6 HC04
OUTPUT
BUFFER
(OPTIONAL TO PREVENT SPURIOUS RESET.)
Figure 10 shows a divide by 2 through 10 circuit using one HC4017. Please note that since Reset is asynchronous, the
output pulse widths are narrow.
Figure 10. ÷2 Through ÷ 10 Circuit
R
C
CE
Q0
R
C
CE
Q0
HC4017
Q1
Q8 Q9
R
HC4017
Q1
9 DECODED
OUTPUTS
Q8 Q9
FIRST STAGE
HC4017
Q8 Q9
8 DECODED
OUTPUTS
8 DECODED
OUTPUTS
HC08
CLOCK
C
CE
Q1
HC08
INTERMEDIATE STAGES
LAST STAGE
Figure 11 shows a technique for cascading the counters to extend the number of decoded output states. Decoded outputs
are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Figure 11. Counter Expansion
MOTOROLA
8
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC4017
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
9
*MC74HC4017/D*
MC74HC4017/D
MOTOROLA