Order this document by MTD1302/D SEMICONDUCTOR TECHNICAL DATA " ! TMOS POWER FET 20 AMPERES 30 VOLTS RDS(on) = 0.022 OHM N–Channel Enhancement Mode Silicon Gate This advanced HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters, and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode Is Characterized for Use In Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Surface Mount Package Available in 16 mm, 13″ / 2500 Unit Tape & Reel, Add “T4” Suffix to Part Number CASE 369A–13, Style 2 MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain–to–Source Voltage Drain–to–Gate Voltage (RGS = 1.0 MΩ) Gate–to–Source Voltage — Continuous — Non–Repetitive (tp ≤ 10 ms) Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Total Power Dissipation @ TC = 25°C (1) Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 Ω) Thermal Resistance Junction to Case Junction–to–Ambient Junction–to–Ambient (1) Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5.0 seconds Symbol Value Unit VDSS VDGR 30 Vdc 30 Vdc VGS VGSM ID ID IDM PD ± 20 ± 20 Vdc Vpk 20 16 60 Adc 74 0.592 1.75 Watts W/°C Watts Apk TJ, Tstg EAS – 55 to 150 °C 200 mJ RθJC RθJA RθJA TL 1.67 100 71.4 °C/W 260 °C (1) When surface mounted to an FR4 board using the minimum recommended pad size. This document contains information on a new product. Specifications and information herein are subject to change without notice. HDTMOS is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company. Motorola, Inc. 1997 Motorola TMOS Power MOSFET Transistor Device Data 1 MTD1302 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max 30 — — — — — — 10 100 — — 100 1.0 1.5 2.0 — — 0.019 0.026 0.022 0.029 — — 0.38 — 0.5 0.33 10 16 — Unit OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS Vdc µAdc nAdc ON CHARACTERISTICS(1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) VGS(th) Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) RDS(on) Drain–to–Source On–Voltage (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150°C) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 10 Adc) Vdc Ohms Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, Vdc VGS = 0 Vdc, Vdc f = 1.0 MHz) Transfer Capacitance Ciss — 755 1162 Coss — 370 518 Crss — 102 204 td(on) — 7.2 15 tr — 52 104 td(off) — 45 90 tf — 73 146 QT — 14.5 21.8 Q1 — 2.2 — Q2 — 8.8 — Q3 — 6.8 — QT — 27 40.5 Q1 — 2.2 — Q2 — 10 — Q3 — 7.2 — — — 0.83 0.79 1.1 — trr — 38 — ta — 19 — tb — 20 — QRR — 36 — pF SWITCHING CHARACTERISTICS(2) Turn–On Delay Time Rise Time Turn–Off Delay Time (VDD = 15 Vdc, Vd ID = 20 Adc, Ad VGS = 10 Vdc Vdc, RG = 9.1 Ω)) Fall Time Gate Charge Vd , ID = 20 Adc, Ad , ((VDS = 24 Vdc, VGS = 5.0 Vdc) Gate Charge ((VDS = 24 Vdc, Vd , ID = 20 Adc, Ad , VGS = 10 Vdc) ns nC nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage VSD (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time ((IS = 20 Adc, Ad , VGS = 0 Vdc, Vd , dIS/dt = 100 A/µs) Reverse Recovery Stored Charge Vdc ns µC (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data MTD1302 TYPICAL ELECTRICAL CHARACTERISTICS 40 30 10 V 5.0 V 4.0 V 25 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 35 30 TJ = 25°C 25 20 15 10 VGS = 3.0 V 5.0 VDS ≥ 10 V 20 15 10 TJ = 125°C – 55°C 0 0 0 0.4 0.2 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.5 1.0 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ = 100°C 25°C – 55°C 0.01 20 15 30 25 35 40 RDS(on), DRAIN–TO–SOURCE ON–RESISTANCE (OHMS) R DS(on), DRAIN–TO–SOURCE ON–RESISTANCE (OHMS) VGS = 10 V 10 2.5 3.0 4.0 3.5 4.5 5.0 Figure 2. Transfer Characteristics 0.03 0.02 2.0 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) Figure 1. On–Region Characteristics 0.04 TJ = 25°C 0.035 0.03 VGS = 4.5 V 0.025 0.02 10 V 0.015 0.01 0.005 0 10 15 20 30 25 35 40 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Drain Current and Temperature Figure 4. On–Resistance versus Drain Current and Gate Voltage 1000 3.0 ID = 10 A IDSS, LEAKAGE (nA) R DS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 25°C 5.0 2.0 VGS = 10 V 1.0 100 TJ = 125°C 100°C 10 25°C 1.0 0 0.1 –50 –25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 5. On–Resistance Variation with Temperature Motorola TMOS Power MOSFET Transistor Device Data 150 5.0 10 15 20 25 30 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 6. Drain–To–Source Leakage Current versus Voltage 3 MTD1302 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) 2500 Ciss C, CAPACITANCE (pF) 2000 1500 Crss 1000 Ciss 500 Coss 0 –10 VDS = 0 V VGS = 0 V –5.0 5.0 0 VGS VDS Crss 10 15 20 25 GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data 12 15 QT 10 12 VGS 8.0 9.0 6.0 Q1 Q2 ID = 20 A TJ = 25°C 4.0 2.0 0 6.0 3.0 Q3 VDS 0 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 22 24 26 28 30 1000 VDD = 15 V ID = 20 A VGS = 10 V TJ = 25°C 100 tf tr td(off) t, TIME (ns) 18 VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) MTD1302 14 10 td(on) 1.0 QG, TOTAL GATE CHARGE (nC) 1.0 10 RG, GATE RESISTANCE (OHMS) Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 DRAIN–TO–SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to Motorola standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 20 I S , SOURCE CURRENT (AMPS) 18 TJ = 25°C 16 14 12 10 8.0 6.0 4.0 2.0 0 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current Motorola TMOS Power MOSFET Transistor Device Data 5 MTD1302 Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta t, TIME Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance – General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reli- able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. Although many E–FETs can withstand the stress of drain– to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 200 VGS = 20 V SINGLE PULSE TC = 25°C EAS , SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) ID , DRAIN CURRENT (AMPS) 100 100 ms 10 1.0 ms 10 ms dc 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 6 1.0 10 100 ID = 20 A 150 100 50 0 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) 150 Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature Motorola TMOS Power MOSFET Transistor Device Data r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) MTD1302 1.0 D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.02 0.01 t1 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 0.01 0.00001 0.0001 0.001 0.01 0.1 1.0 10 t, TIME (s) Figure 14. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 15. Diode Reverse Recovery Waveform Motorola TMOS Power MOSFET Transistor Device Data 7 MTD1302 INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface 0.165 4.191 between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.100 2.54 0.118 3.0 0.063 1.6 0.190 4.826 0.243 6.172 inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. PD = 150°C – 25°C = 1.75 Watts 71.4°C/W The 71.4°C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power 8 dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RθJA versus drain pad area is shown in Figure 16. 100 RθJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (°C/W) The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: Board Material = 0.0625″ G–10/FR–4, 2 oz Copper 1.75 Watts 80 TA = 25°C 60 3.0 Watts 40 5.0 Watts 20 0 2 4 6 A, AREA (SQUARE INCHES) 8 10 Figure 16. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. Motorola TMOS Power MOSFET Transistor Device Data MTD1302 SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or “tombstoning” may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. ÇÇÇ ÇÇÇ ÇÇ ÇÇÇÇÇÇÇÇ ÇÇ ÇÇ ÇÇÇ ÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ SOLDER PASTE OPENINGS STENCIL Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. Motorola TMOS Power MOSFET Transistor Device Data • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. 9 MTD1302 TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 –189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 “SPIKE” “SOAK” 170°C STEP 6 VENT STEP 7 COOLING 205° TO 219°C PEAK AT SOLDER JOINT 160°C 150°C 150°C 100°C 140°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 50°C TMAX TIME (3 TO 7 MINUTES TOTAL) Figure 18. Typical Solder Heating Profile 10 Motorola TMOS Power MOSFET Transistor Device Data MTD1302 PACKAGE DIMENSIONS –T– C B V SEATING PLANE E R 4 Z A S 1 2 3 U K F J L H D G 2 PL 0.13 (0.005) M DIM A B C D E F G H J K L R S U V Z INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.175 0.215 0.020 0.050 0.020 ––– 0.030 0.050 0.138 ––– STYLE 2: PIN 1. 2. 3. 4. T MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.45 5.46 0.51 1.27 0.51 ––– 0.77 1.27 3.51 ––– GATE DRAIN SOURCE DRAIN CASE 369A–13 ISSUE Y Motorola TMOS Power MOSFET Transistor Device Data 11 MTD1302 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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