Order this document by MTB3N120E/D SEMICONDUCTOR TECHNICAL DATA $ # " "! Motorola Preferred Device TMOS POWER FET 3.0 AMPERES 1200 VOLTS RDS(on) = 5.0 OHM N–Channel Enhancement–Mode Silicon Gate The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage–blocking capability without degrading performance over time. In addition, this advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. D G CASE 418B–02, Style 2 D2PAK • Avalanche Energy Capability Specified at Elevated Temperature S • Low Stored Gate Charge for Efficient Switching • Internal Source–to–Drain Diode Designed to Replace External Zener Transient Suppressor Absorbs High Energy in the Avalanche Mode • Source–to–Drain Diode Recovery time Comparable to Discrete Fast Recovery Diode * See App. Note AN1327 – Very Wide Input Voltage Range; Off–line Flyback Switching Power Supply MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol Value Unit Drain–Source Voltage VDSS 1200 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 1200 Vdc Gate–Source Voltage — Continuous Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 40 Vdc Vpk Drain Current — Continuous @ 25°C Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) ID ID IDM 3.0 2.2 11 Adc Total Power Dissipation @ TC = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (1) PD 125 1.0 2.5 Watts W/°C Watts TJ, Tstg – 55 to 150 °C Rating Operating and Storage Temperature Range Apk Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, PEAK IL = 4.5 Apk, L = 10 mH, RG = 25 Ω) EAS Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Thermal Resistance — Junction to Ambient (1) RθJC RθJA RθJA 1.0 62.5 50 °C/W TL 260 °C Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds mJ 101 (1) When surface mounted to an FR4 board using the minimum recommended pad size. E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company. Preferred devices are Motorola recommended choices for future use and best overall value. REV 1 Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1995 1 MTB3N120E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Min Typ Max Unit 1200 — — 1.28 — — Vdc mV/°C — — — — 10 100 — — 100 nAdc 2.0 — 3.0 7.1 4.0 — Vdc mV/°C — 4.0 5.0 Ohm — — — — 18.0 15.8 gFS 2.5 3.1 — mhos Ciss — 2130 2980 pF Coss — 1710 2390 Crss — 932 1860 td(on) — 13.6 30 tr — 12.6 30 td(off) — 35.8 70 tf — 20.7 40 QT — 31 40 Q1 — 8.0 — Q2 — 11 — Q3 — 14 — — — 0.80 0.65 1.0 — trr — 394 — ta — 118 — tb — 276 — QRR — 2.11 — µC Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD — 4.5 — nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS — 7.5 — Characteristic OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 1200 Vdc, VGS = 0 Vdc) (VDS = 1200 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS µAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Temperature Coefficient (Negative) VGS(th) Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 1.5 Adc) RDS(on) Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 3.0 Adc) (ID = 1.5 Adc, TJ = 125°C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn–On Delay Time (VDD = 600 Vdc, ID = 3.0 Adc, VGS = 10 Vdc, RG = 9.1 Ω) Rise Time Turn–Off Delay Time Fall Time Gate Charge (VDS = 600 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) ns nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (1) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 3.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data MTB3N120E TYPICAL ELECTRICAL CHARACTERISTICS 6 6 TJ = 25°C 4 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) VDS ≥ 10 V VGS = 10 V 5 6V 3 5V 2 5 100°C 4 3 2 25°C 1 1 TJ = – 55°C 4V 0 6 12 24 18 30 3.4 3.8 4.2 4.6 5.0 5.4 5.8 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics VGS = 10 V TJ = 100°C 6 4 25°C 2 – 55°C 0 1 2 3 4 5 6 6.2 5.4 TJ = 25°C 5.0 VGS = 10 V 4.6 15 V 4.2 3.8 0 1 2 3 4 5 6 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Drain Current and Temperature Figure 4. On–Resistance versus Drain Current and Gate Voltage 2.5 2.0 10,000 VGS = 0 V VGS = 10 V ID = 1.5 A TJ = 125°C 1,000 I DSS , LEAKAGE (nA) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 3 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 8 0 0 RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) 0 1.5 1.0 0.5 0 – 50 – 25 0 25 50 75 100 125 150 100°C 100 25°C 10 1 0 200 400 600 800 1000 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–To–Source Leakage Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 1200 3 MTB3N120E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) 10,000 2800 Ciss VDS = 0 V VGS = 0 V TJ = 25°C TJ = 25°C Ciss 2000 1600 Crss C, CAPACITANCE (pF) C, CAPACITANCE (pF) 2400 VGS = 0 V Ciss 1200 800 Coss 1,000 Coss 100 400 Crss Crss 0 10 5 0 VGS 5 10 15 20 VDS GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7a. Capacitance Variation 4 25 10 10 100 1000 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7b. High Voltage Capacitance Variation Motorola TMOS Power MOSFET Transistor Device Data MTB3N120E 350 12 300 QT 10 250 8 Q2 Q1 6 150 ID = 3 A TJ = 25°C 4 2 0 200 VGS 0 4 50 VDS Q3 8 12 16 100 20 24 28 0 32 1000 t, TIME (ns) 14 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 400 VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS) 16 VDD = 600 V ID = 3 A VGS = 10 V TJ = 25°C 100 td(off) tf td(on) tr 10 1 Qg, TOTAL GATE CHARGE (nC) 1 10 RG, GATE RESISTANCE (OHMS) Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 DRAIN–TO–SOURCE DIODE CHARACTERISTICS 3.0 VGS = 0 V TJ = 25°C I S , SOURCE CURRENT (AMPS) 2.4 1.8 1.2 0.6 0 0.55 0.59 0.63 0.67 0.71 0.75 0.79 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance–General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A Power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reli- Motorola TMOS Power MOSFET Transistor Device Data able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. Although many E–FETs can withstand the stress of drain– to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 5 MTB3N120E SAFE OPERATING AREA 10 120 VGS = 20 V SINGLE PULSE TC = 25°C EAS, SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 100 10 µs 100 µs 1.0 1 ms 10 ms 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 0.1 1 10 dc 1,000 100 ID = 3 A 100 80 60 40 20 0 10,000 25 50 75 100 125 150 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature r (t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.02 0.01 1.0E–05 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 1.0E–04 1.0E–03 1.0E–02 1.0E–01 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 1.0E+00 1.0E+01 t, TIME (s) Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform 6 Motorola TMOS Power MOSFET Transistor Device Data MTB3N120E L1 H1 90VAC– 600VAC C1 0.1 1 kV D1 – D4 1N4007s C4 0.1 1 kV L1 +Vin H2 C3 0.0047 3 kV C2 0.0047 3 kV EARTH GND C6 100 mF 450 V + C5 100 mF 450 V + R4 470 k 1/2 W R3 470 k 1/2 W R2 470 k 1/2 W R1 470 k 1/2 W INPUT GND Figure 15. The AC Input/Filter Circuit Section T1 C11 D8 100 mF MBR370 10 V +Vin R9 R8 100 mF 20 V D9 MUR430 Vaux 82 k, 1/2 W R7 R6 R5 R16 100 k 1/2 W 10 mF 25 V + D10 + C13 C9 LL MUR1100 6 4 C7 220 pF 1 U2 1/2 MOC8102 2 5 3 R12 10 W R15 680 W U2 MOC8102 D6 D7 R13 1k R20 120 W C15 1.5 nF R19 32.4 k 1.3 mF 7.5 k C17 2.2 nF Q1 C8 1000 pF +5 V C14 MTP3N120E UC3845BN D5 3.3 V C12 Vaux 7 R10 27 k + + MUR130 C10 R11 1.8 k 1 nF 3 kV + +12 V U3 TL431 C16 R17 R21 2.49 k GND R14 1.2 W 1/2 W INPUT GND Figure 16. The DC/DC Converter Circuit Section Motorola TMOS Power MOSFET Transistor Device Data 7 MTB3N120E INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.33 8.38 0.08 2.032 0.42 10.66 0.24 6.096 0.04 1.016 0.12 3.05 0.63 17.02 inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. PD = 150°C – 25°C = 2.5 Watts 50°C/W The 50°C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power 8 dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RθJA versus drain pad area is shown in Figure 16. RθJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (°C/W) The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: 70 Board Material = 0.0625″ G-10/FR-4, 2 oz Copper 60 TA = 25°C 2.5 Watts 50 3.5 Watts 40 5 Watts 30 20 0 2 4 6 8 10 12 14 16 A, AREA (SQUARE INCHES) Figure 17. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. Motorola TMOS Power MOSFET Transistor Device Data MTB3N120E SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or “tombstoning” may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇ ÇÇ ÇÇ ÇÇ SOLDER PASTE OPENINGS STENCIL Figure 18. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. Motorola TMOS Power MOSFET Transistor Device Data • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. 9 MTB3N120E TYPICALSOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 –189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 “SPIKE” “SOAK” 170°C STEP 6 VENT STEP 7 COOLING 205° TO 219°C PEAK AT SOLDER JOINT 160°C 150°C 150°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) 140°C 100°C DESIRED CURVE FOR LOW MASS ASSEMBLIES 50°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile 10 Motorola TMOS Power MOSFET Transistor Device Data MTB3N120E PACKAGE DIMENSIONS C E V B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 4 A 1 2 STYLE 2: PIN 1. 2. 3. 4. S 3 –T– SEATING PLANE K J G D H 3 PL 0.13 (0.005) M GATE DRAIN SOURCE DRAIN DIM A B C D E G H J K S V INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40 T CASE 418B–02 ISSUE B Motorola TMOS Power MOSFET Transistor Device Data 11 MTB3N120E Motorola reserves the right to make changes without further notice to any products herein. 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