MOTOROLA SN74LS173N

SN54/74LS173A
4-BIT D-TYPE REGISTER
WITH 3-STATE OUTPUTS
The SN54 / 74LS173A is a high-speed 4-Bit Register featuring 3-state
outputs for use in bus-organized systems. The clock is fully edge-triggered
allowing either a load from the D inputs or a hold (retain register contents)
depending on the state of the Input Enable Lines (IE1, IE2). A HIGH on either
Output Enable line (OE1, OE2) brings the output to a high impedance state
without affecting the actual register contents. A HIGH on the Master Reset
(MR) input resets the Register regardless of the state of the Clock (CP), the
Output Enable (OE1, OE2) or the Input Enable (IE1, IE2) lines.
• Fully Edge-Triggered
• 3-State Outputs
• Gated Input and Output Enables
• Input Clamp Diodes Limit High-Speed Termination Effects
4-BIT D-TYPE REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
16
1
CONNECTION DIAGRAM DIP (TOP VIEW)
N SUFFIX
PLASTIC
CASE 648-08
16
1
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
D SUFFIX
SOIC
CASE 751B-03
16
1
ORDERING INFORMATION
PIN NAMES
LOADING (Note a)
MR
Q0 – Q3
Data Inputs
Input Enable (Active LOW)
Output Enable (Active LOW) Inputs
Clock Pulse (Active HIGH Going Edge)
Input
Master Reset Input (Active HIGH)
Outputs (Note b)
Ceramic
Plastic
SOIC
LOW
HIGH
D0 – D3
IE1 – IE2
OE1 – OE2
CP
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
65 (25) U.L.
0.25 U.L.
15 (7.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC SYMBOL
FAST AND LS TTL DATA
5-316
SN54/74LS173A
LOGIC DIAGRAM
TRUTH TABLE
MR
CP
IE1
IE2
Dn
Qn
H
L
L
L
L
L
x
L
x
x
H
x
L
L
x
x
x
H
L
L
x
x
x
x
L
H
L
Qn
Qn
Qn
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
When either OE1, or OE2 are HIGH, the output is in the off state (High Impedance);
however this does not affect the contents or sequential operation of the register.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
– 55
0
25
25
125
70
°C
IOH
Output Current — High
54
74
– 1.0
– 2.6
mA
IOL
Output Current — Low
54
74
12
24
mA
FAST AND LS TTL DATA
5-317
SN54/74LS173A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Min
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOZH
IOZL
Typ
Max
Unit
2.0
54
0.7
74
0.8
– 0.65
– 1.5
Test Conditions
V
Guaranteed Input HIGH Voltage for
All Inputs
V
Guaranteed Input LOW Voltage for
All Inputs
V
VCC = MIN, IIN = – 18 mA
54
2.4
3.4
V
74
2.4
3.1
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
54, 74
0.25
0.4
V
IOL = 12 mA
74
0.35
0.5
V
IOL = 24 mA
Output Off Current HIGH
20
µA
VCC = MAX, VO = 2.7 V
Output Off Current LOW
– 20
µA
VCC = MAX, VO = 0.4 V
20
µA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
– 0.4
mA
VCC = MAX, VIN = 0.4 V
– 130
mA
VCC = MAX
30
mA
VCC = MAX
IIH
Input HIGH Current
IIL
Input LOW Current
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
– 30
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Limits
Symbol
Parameter
Min
Typ
30
50
Max
Unit
Test Conditions
fMAX
Maximum Input Clock Frequency
MHz
tPLH
tPHL
Propagation Delay,
Clock to Output
17
22
25
30
ns
tPHL
Propagation Delay, MR to Output
26
35
ns
tPZH
tPZL
Output Enable Time
15
18
23
27
ns
tPLZ
tPHZ
Output Disable Time
11
11
17
17
ns
CL = 5.0 pF,
RL = 667 Ω
Max
Unit
Test Conditions
VCC = 5.0 V
CL = 45 pF,
RL = 667 Ω
AC SETUP REQUIREMENTS (TA = 25°C)
Limits
Symbol
Parameter
Min
Typ
tW
Clock or MR Pulse Width
20
ns
ts
Data Enable Setup Time
35
ns
ts
Data Setup Time
17
ns
th
Hold Time, Any Input
0
ns
trec
Recovery Time
10
ns
FAST AND LS TTL DATA
5-318
VCC = 5.0 V
SN54/74LS173A
AC WAVEFORMS
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Figure 4
AC LOAD CIRCUIT
SWITCH POSITIONS
SYMBOL
SW1
SW2
tPZH
Open
Closed
tPZL
Closed
Open
tPLZ
Closed
Closed
tPHZ
Closed
Closed
"
Ω
* Includes Jig and Probe Capacitance.
Figure 5
FAST AND LS TTL DATA
5-319
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FAST AND LS TTL DATA
5-320
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FAST AND LS TTL DATA
5-321