MC10EP139, MC100EP139 3.3V / 5VECL ÷2/4, ÷4/5/6 Clock Generation Chip The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single−ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single−ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 F capacitor. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip−flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start−up, the internal flip−flops will attain a random state; therefore, for systems which utilize multiple EP139s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one EP139, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2/4 and the ÷4/5/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100 Series contains temperature compensation. • Maximum Frequency > 1.0 GHz Typical • 50 ps Output−to−Output Skew • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V • • • • • • with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State http://onsemi.com MARKING DIAGRAMS* 20 20 HEP or KEP 139 ALYW 1 TSSOP−20 DT SUFFIX CASE 948E 1 20 20 MCXXXEP139 AWLYYWW 1 SOIC−20 DW SUFFIX CASE 751D HEP KEP XXX A L,WL Y, YY W, WW 1 = MC10EP = MC100EP = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week *For additional marking information, refer to Application Note AND8002/D. Safety Clamp on Inputs ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips VBB Output Semiconductor Components Industries, LLC, 2005 February, 2005 − Rev. 6 1 Publication Order Number: MC10EP139/D MC10EP139, MC100EP139 VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 20 19 18 17 16 15 14 13 12 11 Table 1. PIN DESCRIPTION PIN FUNCTION ECL Differential 4/5/6 Outputs Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. DIVSELa* ECL Frequency Select Input 2/4 DIVSELb0* ECL Frequency Select Input 4/5/6 Figure 1. 20−Lead Pinout (Top View) DIVSELb1 ECL Frequency Select Input 4/5/6 VCC ECL Positive Supply VEE ECL Negative Supply 7 8 9 10 DIVSELa ECL Differential 2/4 Outputs Q2, Q3, Q2, Q3 6 DIVSELb1 Q0, Q1, Q0, Q1 5 VCC ECL Reference Output 4 MR VBB 3 VBB ECL Master Reset 2 CLK MR* 1 CLK ECL Sync Enable DIVSELb0 EN* EN ECL Differential Clock Inputs VCC CLK*, CLK* *Pins will default low when left open. DIVSELa Q0 CLK ÷2/4 CLK R Q0 Q1 Q1 Q2 EN ÷4/5/6 R Q2 Q3 MR DIVSELb0 DIVSELb1 Q3 VEE Figure 2. Logic Diagram Table 2. FUNCTION TABLES CLK EN MR Function Z ZZ X L H X L L H Divide Hold Q0:3 Reset Q0:3 Z = Low−to−High Transition ZZ = High−to−Low Transition DIVSELa Q0:1 Outputs L H Divide by 2 Divide by 4 DIVSELb0 DIVSELb1 Q2:3 Outputs L H L H L L H H Divide by 4 Divide by 6 Divide by 5 Divide by 5 http://onsemi.com 2 MC10EP139, MC100EP139 CLK Q (÷2) Q (÷4) Q (÷5) Q (÷6) Figure 3. CLK and OUTPUT Timing Diagram CLK tRR RESET Q (÷n) Figure 4. Timing Diagram http://onsemi.com 3 MC10EP139, MC100EP139 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charged Device Model > 2 kV > 100 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 758 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−20 TSSOP−20 140 100 °C/W °C/W JC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−20 23 to 41 °C/W JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−20 SOIC−20 90 60 °C/W °C/W JC Thermal Resistance (Junction−to−Case) Standard Board SOIC−20 33 to 35 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C VI VCC VI VEE Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 4 MC10EP139, MC100EP139 Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 65 82 105 65 83 105 65 84 105 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 3) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single−Ended) 1365 1690 1460 1755 1490 1815 mV VBB Output Voltage Reference 1790 1990 1855 2055 1915 2115 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 A IIL Input LOW Current 1890 2.0 1955 150 0.5 2015 150 0.5 A 0.5 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 3. All loading with 50 to VCC − 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 65 82 105 65 83 105 65 84 105 mA Output HIGH Voltage (Note 6) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 6) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV VBB Output Voltage Reference 3490 3690 3555 3755 3615 3815 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 A IIL Input LOW Current IEE Power Supply Current VOH 3590 2.0 150 0.5 3655 150 0.5 0.5 3715 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 6. All loading with 50 to VCC − 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 MC10EP139, MC100EP139 Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 8) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 65 82 105 65 83 105 65 84 105 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 9) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 9) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV VIH Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV VBB Output Voltage Reference −1510 −1310 −1445 −1245 −1385 −1185 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) 0.0 V IIH Input HIGH Current 150 A IIL Input LOW Current −1410 VEE+2.0 0.0 −1345 VEE+2.0 0.0 150 0.5 −1285 VEE+2.0 150 0.5 A 0.5 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. 9. All loading with 50 to VCC − 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 70 83 100 70 87 105 75 90 110 mA Output HIGH Voltage (Note 12) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 12) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV VBB Output Voltage Reference 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 A IIL Input LOW Current IEE Power Supply Current VOH 1875 2.0 150 0.5 1875 150 0.5 0.5 1875 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 12. All loading with 50 to VCC − 2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 6 MC10EP139, MC100EP139 Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 70 85 100 70 90 105 75 95 110 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 15) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 15) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV VBB Output Voltage Reference 3475 3675 3475 3675 3475 3675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 16) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 A IIL Input LOW Current 3575 2.0 3575 150 3575 150 0.5 0.5 A 0.5 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 15. All loading with 50 to VCC − 2.0 V. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 17) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 70 85 100 70 90 105 75 95 110 mA Output HIGH Voltage (Note 18) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 18) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV VBB Output Voltage Reference −1525 −1325 −1525 −1325 −1525 −1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) 0.0 V IIH Input HIGH Current 150 A IIL Input LOW Current IEE Power Supply Current VOH −1425 VEE+2.0 0.0 150 0.5 −1425 VEE+2.0 0.0 150 0.5 −1425 VEE+2.0 0.5 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17. Input and output parameters vary 1:1 with VCC. 18. All loading with 50 to VCC − 2.0 V. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 7 MC10EP139, MC100EP139 Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20) −40°C Symbol Characteristic Min Typ 25°C Max Min >1 Typ 85°C Max Min Max Maximum Frequency (See Figure 5 Fmax/JITTER) tPLH, tPHL Propagation Delay tRR Reset Recovery ts Setup Time th Hold Time tPW Minimum Pulse Width tSKEW Within Device Skew Q, Q Device−to−Device Skew (Note 21) 50 200 100 300 50 200 100 300 50 200 100 300 ps tJITTER Random Clock Jitter (RMS) (See Figure 5 Fmax/JITTER) 0.2 < 1.0 0.2 < 1.0 0.2 < 1.5 ps VPP Input Voltage Swing (Differential Configuration) 150 800 1200 150 800 1200 150 800 1200 mV tr tf Output Rise/Fall Times (20% − 80%) 110 180 250 125 190 275 150 215 300 ps 550 700 700 800 200 EN, CLK DIVSEL, CLK 600 700 750 850 100 200 200 400 120 180 CLK, EN CLK, DIVSEL 100 200 50 140 MR 550 450 Q, Q 800 900 >1 Unit fmax CLK, Q (Diff) MR, Q >1 Typ 900 1000 GHz 675 800 825 950 975 1100 ps 100 165 100 ps 200 400 120 180 200 400 120 180 ps 100 200 50 140 100 200 50 140 ps 550 450 550 450 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC − 2.0 V. 21. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. http://onsemi.com 8 900 8 800 7 700 6 600 5 500 4 JITTEROUT ps (RMS) VOUTpp (mV) MC10EP139, MC100EP139 ÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 400 3 300 2 200 (JITTER) 1 100 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) 900 8 800 7 700 6 600 5 500 JITTEROUT ps (RMS) VOUTpp (mV) Figure 5. 2, Fmax/Jitter ÉÉ ÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 4 400 3 300 2 200 (JITTER) 1 100 0 0 200 400 600 800 1000 1200 1400 FREQUENCY (MHz) Figure 6. 5, Fmax/Jitter http://onsemi.com 9 1600 1800 2000 900 8 800 7 700 6 600 5 500 4 JITTEROUT ps (RMS) VOUTpp (mV) MC10EP139, MC100EP139 ÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 400 3 300 2 200 (JITTER) 1 100 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) 900 8 800 7 700 6 600 5 500 JITTEROUT ps (RMS) VOUTpp (mV) Figure 7. 4, Fmax/Jitter ÉÉ ÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 4 400 3 300 2 200 (JITTER) 1 100 0 0 200 400 600 800 1000 1200 1400 FREQUENCY (MHz) Figure 8. 6, Fmax/Jitter http://onsemi.com 10 1600 1800 2000 MC10EP139, MC100EP139 Zo = 50 Q D Receiver Device Driver Device Zo = 50 Q D 50 50 VTT VTT = VCC − 2.0 V Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device Shipping† Package MC10EP139DT TSSOP−20 75 Units / Rail MC10EP139DTR2 TSSOP−20 2500 / Tape & Reel MC10EP139DW SOIC−20 38 Units / Rail MC10EP139DWR2 SOIC−20 1000 / Tape & Reel MC100EP139DT TSSOP−20 75 Units / Rail MC100EP139DTR2 TSSOP−20 2500 / Tape & Reel MC100EP139DW SOIC−20 38 Units / Rail MC100EP139DWR2 SOIC−20 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 11 MC10EP139, MC100EP139 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPS I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1642/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 12 MC10EP139, MC100EP139 PACKAGE DIMENSIONS SOIC−20 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D−05 ISSUE G A 20 X 45 h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE C T http://onsemi.com 13 DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0 7 MC10EP139, MC100EP139 PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E−02 ISSUE B 20X 0.15 (0.006) T U 2X S L/2 20 M T U S V S K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ 11 B L J J1 −U− PIN 1 IDENT SECTION N−N 1 10 0.25 (0.010) N 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. ICONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. K REF 0.10 (0.004) S M A −V− N F DETAIL E −W− C D G H DETAIL E 0.100 (0.004) −T− SEATING DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 PLANE ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 14 For additional information, please contact your local Sales Representative. MC10EP139/D