VISHAY SI3552DV-T1-E3

SPICE Device Model Si3552DV
Vishay Siliconix
N- and P-Channel 30-V (D-S) MOSFET
CHARACTERISTICS
• N- and P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n- and p-channel vertical DMOS. The
subcircuit model is extracted and optimized over the
−55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate
drive. The saturated output impedance is best fit at the gate bias
near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 71514
S-52634Rev. C, 02-Jan-06
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SPICE Device Model Si3552DV
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Typical
Unit
Static
Gate Threshold Voltage
VGS(th)
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
rDS(on)
Forward Transconductancea
gfs
Diode Forward Voltagea
VSD
VDS = V, VGS, ID = 250 µA
N-Ch
1.9
VDS = V, VGS, ID = −250 µA
P-Ch
2.13
VDS = 5 V, VGS = 10 V
N-Ch
51
VDS = −5 V, VGS = −10 V
P-Ch
24
VGS = 10 V, ID = 2.5 A
N-Ch
0.090
VGS = −10 V, ID = −1.8 A
P-Ch
0.177
VGS = 4.5 V, ID = 2.0 A
N-Ch
0.134
VGS = −4.5 V, ID = −1.2 A
P-Ch
0.281
VDS = 10 V, ID = 2.5 A
N-Ch
4.3
VDS = −15 V, ID = −1.2 A
P-Ch
2.5
IS = 1.05 A, VGS = 0 V
N-Ch
0.81
IS = −1.05 V, VGS = 0 V
P-Ch
−0.81
N-Ch
2
V
A
Ω
S
V
Dynamicb
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
N-Channel
VDS = 15 V, VGS = 5 V, ID = 1.8 A
P-Channel
VDS = −15 V, VGS = −5 V, ID = −1.8 A
td(on)
N-Channel
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
tr
td(off)
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω
P-Channel
VDD = −15 V, RL = 15 Ω
ID ≅ −1 A, VGEN = −10 V, RG = 6 Ω
tf
trr
P-Ch
2.4
N-Ch
0.7
P-Ch
0.9
N-Ch
0.7
P-Ch
0.8
N-Ch
7
P-Ch
8
N-Ch
9
P-Ch
8
N-Ch
12
P-Ch
11
N-Ch
14
P-Ch
12
IF = A, IS = 1.05A, di/dt = 100 A/µs
N-Ch
35
IF = A, IS = −1.05A, di/dt = 100 A/µs
P-Ch
31
nC
ns
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
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Document Number: 71514
S-52634Rev. C, 02-Jan-06
SPICE Device Model Si3552DV
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
N-Channel MOSFET
Document Number: 71514
S-52634Rev. C, 02-Jan-06
www.vishay.com
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SPICE Device Model Si3552DV
Vishay Siliconix
P-Channel MOSFET
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Document Number: 71514
S-52634Rev. C, 02-Jan-06
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Document Number: 91000
Revision: 18-Jul-08
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