VISHAY SI1907DL

SPICE Device Model Si1907DL
Vishay Siliconix
Dual P-Channel 1.8-V (G-S) MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 5-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 71526
S-50232Rev. B, 28-Feb-05
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SPICE Device Model Si1907DL
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
VGS(th)
VDS = VGS, ID = −250 µA
0.78
Measured
Data
Unit
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistance a
Forward Transconductance a
Diode Forward Voltage
Dynamic
a
ID(on)
rDS(on)
V
VDS = −5 V, VGS = −4.5 V
5.8
VGS = −4.5 V, ID = −0.53 A
0.54
0.57
VGS = −2.5 V, ID = −0.44 A
0.77
0.80
A
Ω
VGS = −1.8 V, ID = −0.20 A
1.05
1.25
gfs
VDS = −10 V, ID = −0.53 A
1.19
1.1
S
VSD
IS = −0.23 A, VGS = 0 V
−0.76
−0.80
V
0.72
1.5
0.14
0.40
b
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VDS = −6 V, VGS = −4.5 V, ID = −0.53 A
Gate-Drain Charge
Qgd
0.12
0.25
Turn-On Delay Time
td(on)
6
6
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Source-Drain Reverse Recovery Time
trr
VDD = −6 V, RL = 12 Ω
ID ≅ −0.50 A, VGEN = −4.5 V, RG = 6 Ω
IF = −0.23 A, di/dt = 100 µs
7
20
23
10
7
10
15
20
nC
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
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Document Number: 71526
S-50232Rev. B, 28-Feb-05
SPICE Device Model Si1907DL
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 71526
S-50232Rev. B, 28-Feb-05
www.vishay.com
3