Preliminary CMOS SRAM K6F8016U6C Family Document Title 512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 Initial draft Draft Date Remark May 1, 2003 Preliminary The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 0.0 May 2003 Preliminary CMOS SRAM K6F8016U6C Family 512K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology: Full CMOS • Organization: 512K x16 • Power Supply Voltage: 2.7~3.3V • Low Data Retention Voltage: 1.5V(Min) • Three State Outputs • Package Type: 48-FBGA-6.00x7.00 The K6F8016U6C families are fabricated by SAMSUNG′s advanced full CMOS process technology. The families support industrial operating temperature ranges and have chip scale package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed K6F8016U6C-F Industrial(-40~85°C) 2.7~3.3V 551)/70ns Standby (ISB1, Typ.) Operating (ICC1, Max) 4µA2) 4mA PKG Type 48-FBGA-6.00x7.00 1. The parameter is measured with 30pF test load. 2. Typical values are measured at VCC=3.0V, TA=25°C and not 100% tested FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION 1 2 3 4 5 6 LB OE A0 A1 A2 CS2 Clk gen. A Precharge circuit. Vcc Vss B I/O9 UB A3 A4 CS1 I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D Vss I/O12 A17 A7 I/O4 Vcc E Vcc I/O13 Vss A16 I/O5 Vss F I/O15 I/O14 A14 A15 I/O6 I/O7 Row Addresses I/O1~I/O8 Row select Data cont Memory array 1024 rows 512×16 columns I/O Circuit Column select Data cont I/O9~I/O16 Data cont G I/O16 DNU A12 A13 WE I/O8 Column Addresses H A18 A8 A9 A10 A11 DNU CS1 48 ball FBGA - Top View(Ball Down) CS2 OE Name CS1, CS2 Function Name Function Chip Select Inputs Vcc Power OE Output Enable Input Vss Ground WE Write Enable Input UB Upper Byte(I/O9~16) Address Inputs LB Lower Byte(I/O1~8) A0~A18 I/O1~I/O16 Data Inputs/Outputs DNU WE Control Logic UB LB Do Not Use SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 0.0 May 2003 Preliminary CMOS SRAM K6F8016U6C Family PRODUCT LIST Industrial Temperature Products(-40~85°C) Part Name Function K6F8016U6C-FF55 K6F8016U6C-FF70 48-FBGA, 55ns, 3.0V 48-FBGA, 70ns, 3.0V FUNCTIONAL DESCRIPTION CS1 CS2 OE WE LB UB 1) 1) I/O1~8 I/O9~16 Mode Power H X X X X X High-Z High-Z Deselected Standby X1) L X1) X1) X1) X1) High-Z High-Z Deselected Standby X1) X1) X1) X1) H H L H H H L L H H H L H L H L L H L H H L H L H L H X1) L L H 1) X L H X1) 1) 1) 1) High-Z High-Z Deselected Standby X High-Z High-Z Output Disabled Active L High-Z High-Z Output Disabled Active H Dout High-Z Lower Byte Read Active L High-Z Dout Upper Byte Read Active L L Dout Dout Word Read Active L H Din High-Z Lower Byte Write Active L H L High-Z Din Upper Byte Write Active L L L Din Din Word Write Active X 1) 1) 1. X means don′t care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol Ratings Unit VIN, VOUT -0.5 to VCC+0.3V(Max. 3.6V) V VCC -0.3 to 3.6 V PD 1.0 W TSTG -65 to 150 °C TA -40 to 85 °C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions over 1 second may affect reliability. 3 Revision 0.0 May 2003 Preliminary CMOS SRAM K6F8016U6C Family RECOMMENDED DC OPERATING CONDITIONS1) Symbol Min Typ Max Unit Supply voltage Item Vcc 2.7 3.0 3.3 V Ground Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.32) V Input low voltage VIL -0.33) - 0.6 V Note: 1. TA=-40 to 85°C, otherwise specified. 2. Overshoot: VCC+2.0V in case of pulse width ≤20ns. 3. Undershoot: -2.0V in case of pulse width ≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTIC Item Input leakage current Output leakage current Symbol Test Conditions Min Typ1) Max Unit ILI VIN=Vss to Vcc -1 - 1 µA ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH, VIO=Vss to Vcc -1 - 1 µA ICC1 Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V, LB≤0.2V or/and UB≤0.2V, CS2≥Vcc-0.2V, VIN≤0.2V or VIN≥VCC-0.2V - - 4 mA Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL or VIH 70ns - - 22 ICC2 55ns - - 28 Average operating current mA Output low voltage VOL IOL = 2.1mA - - 0.4 V Output high voltage VOH IOH = -1.0mA 2.4 - - V Standby Current(CMOS) ISB1 Other input =0~Vcc 1) CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or 2) 0V≤CS2≤0.2V(CS2 controlled) - 4 15 µA 1. Typical values are measured at VCC=3.0V, TA=25°C and not 100% tested. 4 Revision 0.0 May 2003 Preliminary CMOS SRAM K6F8016U6C Family VTM3) AC OPERATING CONDITIONS R12) TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL CL1) R22) 1. Including scope and jig capacitance 2. R1=3070Ω, R2=3150Ω 3. VTM =2.8V AC CHARACTERISTICS (Vcc=2.7~3.3V, Industrial product: TA=-40 to 85°C) Speed Bins Parameter List Symbol 55ns Min Read Write Units 70ns Max Min Max Read Cycle Time tRC 55 - 70 - ns Address Access Time tAA - 55 - 70 ns Chip Select to Output tCO - 55 - 70 ns Output Enable to Valid Output tOE - 25 - 35 ns UB, LB Access Time tBA - 55 - 70 ns Chip Select to Low-Z Output tLZ 10 - 10 - ns UB, LB Enable to Low-Z Output tBLZ 10 - 10 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - ns Chip Disable to High-Z Output tHZ 0 20 0 25 ns UB, LB Disable to High-Z Output tBHZ 0 20 0 25 ns Output Disable to High-Z Output tOHZ 0 20 0 25 ns Output Hold from Address Change tOH 10 - 10 - ns Write Cycle Time tWC 55 - 70 - ns Chip Select to End of Write tCW 45 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 45 - 60 - ns UB, LB Valid to End of Write tBW 45 - 60 - ns Write Pulse Width tWP 40 - 50 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 20 0 20 ns Data to Write Time Overlap tDW 25 - 30 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS1≥Vcc-0.2V Data retention current IDR Vcc=1.5V, CS1≥Vcc-0.2V Data retention set-up time tSDR Recovery time tRDR 1) 1) See data retention waveform Min Typ2) Max Unit 1.5 - 3.3 V - 1.0 6 µA 0 - - tRC - - ns 1. 1) CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or 2) 0≤CS2≤0.2V(CS2 controlled) 2. Typical values are measured at TA=25°C and not 100% tested. 5 Revision 0.0 May 2003 Preliminary CMOS SRAM K6F8016U6C Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS1 CS2 tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ Data out High-Z tOHZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 0.0 May 2003 Preliminary CMOS SRAM K6F8016U6C Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS1 CS2 tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS1 tAW CS2 tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z 7 Revision 0.0 May 2003 Preliminary CMOS SRAM K6F8016U6C Family TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS1 tAW CS2 tBW UB, LB tAS(3) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high. DATA RETENTION WAVE FORM CS1 controlled VCC tSDR Data Retention Mode tRDR 2.7V 2.2V VDR CS1≥VCC - 0.2V CS1 GND CS2 controlled Data Retention Mode VCC 2.7V CS2 tSDR tRDR VDR CS2≤0.2V 0.4V GND 8 Revision 0.0 May 2003 Preliminary CMOS SRAM K6F8016U6C Family PACKAGE DIMENSION Unit: millimeters 48 BALL FINE PITCH BALL GRID ARRAY(0.75mm ball pitch) Top View Bottom View B B1 B 6 5 4 3 2 1 A B #A1 C C C C1 D E C1/2 F G H B/2 Detail A Side View A Y 0.58/Typ. E1 E 0.32/Typ. E2 D C Min Typ Max A - 0.75 - B 5.90 6.00 6.10 1. Ball counts: 48(8 row x 6 column) B1 - 3.75 - 2. Ball pitch: (x,y)=(0.75 x 0.75)(typ.) C 6.90 7.00 7.10 C1 - 5.25 - D 0.40 0.45 0.50 E 0.80 0.90 1.00 E1 - 0.58 - E2 0.27 0.32 0.37 Y - - 0.08 Notes. 3. All tolerence are ±0.050 unless specified beside figure. 4. Typ: Typical 5. Y is coplanarity: 0.08(Max) 9 Revision 0.0 May 2003