K6F8016V3A Family CMOS SRAM Document Title 512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial draft -Design Target July 4, 2001 Preliminary 1.0 Finalize September 26, 2001 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.0 September 2001 K6F8016V3A Family CMOS SRAM 512K x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology: Full CMOS • Organization: 512K x16 • Power Supply Voltage: 3.0~3.6V • Low Data Retention Voltage: 1.5V(Min) • Three State Outputs • Package Type: 44-TSOP2-400F/R The K6F8016V3A families are fabricated by SAMSUNG′s advanced full CMOS process technology. The families support various operating temperature ranges. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed K6F8016V3A-F Industrial(-40~85°C) 3.0~3.6V 551)/70ns Standby (ISB1, Typ.) Operating (ICC1, Max) 0.5µA2) 4mA PKG Type 44-TSOP2-400F/R 1. The parameter is measured with 30pF test load. 2. Typical values are measured at VCC=3.3V, TA=25°C and not 100% tested. PIN DESCRIPTION A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-TSOP2 Forward 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 A8 A9 A10 A11 A12 A13 FUNCTIONAL BLOCK DIAGRAM A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 A8 A9 A10 A11 A12 A13 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-TSOP2 Reverse 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A18 A17 A16 A15 A14 Clk gen. Precharge circuit. Vcc Vss Row Addresses I/O1~I/O8 Row select Data cont Memory array 1024 rows 512×16 columns I/O Circuit Column select Data cont I/O9~I/O16 Data cont Name Function Name Function Column Addresses CS Chip Select Input Vcc Power OE Output Enable Input Vss Ground WE Write Enable Input UB Upper Byte(I/O9~16) CS1 Address Inputs LB Lower Byte(I/O1~8) OE A0~A18 I/O1~I/O16 Data Inputs/Outputs CS2 WE Control Logic UB LB SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 September 2001 K6F8016V3A Family CMOS SRAM PRODUCT LIST Industrial Temperature Products(-40~85°C) Part Name Function K6F8016V3A-TF55 K6F8016V3A-TF70 44-TSOP2-F, 55ns, 3.3V 44-TSOP2-F, 70ns, 3.3V K6F8016V3A-RF55 K6F8016V3A-RF70 44-TSOP2-R, 55ns, 3.3V 44-TSOP2-R, 70ns, 3.3V FUNCTIONAL DESCRIPTION CS OE WE LB UB I/O1~8 I/O9~16 Mode Power H X X X X High-Z High-Z Deselected Standby L H H X X High-Z High-Z Output Disabled Active H High-Z High-Z Output Disabled Active H Dout High-Z Lower Byte Read Active L X X H L L H L L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active L X L L H Din High-Z Lower Byte Write Active L X L H L High-Z Din Upper Byte Write Active L X L L L Din Din Word Write Active Note : X means don′t care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Symbol Ratings Unit VIN,VOUT -0.2 to VCC+0.3V(max.4.0V) V Voltage on Vcc supply relative to Vss VCC -0.2 to 4.0 V Power Dissipation PD 1.0 W TSTG -65 to 150 °C TA -40 to 85 °C Storage temperature Operating Temperature 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.0 September 2001 K6F8016V3A Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Symbol Min Typ Max Unit Supply voltage Item Vcc 3.0 3.3 3.6 V 0 Ground Vss 0 0 Input high voltage VIH 2.2 - Input low voltage VIL -0.33) - V Vcc+0.3 V 2) 0.6 V Note: 1. Industrial products: TA=-40 to 85°C, otherwise specified. 2. Overshoot: VCC+2.0V in case of pulse width ≤20ns. 3. Undershoot: -2.0V in case of pulse width ≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Symbol Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH, or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS1=VIL, WE=VIH, VIN=VIH or VIL - - 2 mA ICC1 Cycle time=1µs, 100%duty, IIO=0mA, CS≤0.2V, VIN≤0.2V or VIN≥VCC-0.2V - - 4 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, VIN=VIL or VIH - - 45 mA Output low voltage VOL IOL = 2.1mA - - 0.4 V Output high voltage VOH IOH = -1.0mA 2.4 - - V Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - 0.5 30 µA Average operating current Test Conditions Min Typ1) 1. Typical values are measured at VCC=3.3V, TA=25°C and not 100% tested. 4 Revision 1.0 September 2001 K6F8016V3A Family CMOS SRAM AC OPERATING CONDITIONS VTM3) TEST CONDITIONS(Test Load and Input/Output Reference) R12) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL CL1) R22) 1. Including scope and jig capacitance 2. R1 =3070Ω, R2 =3150Ω 3. VTM =2.8V AC CHARACTERISTICS (Vcc=3.0~3.6V) Speed Bins Parameter List Symbol Write Units 70ns Min Max Min Max tRC 55 - 70 - ns Address Access Time tAA - 55 - 70 ns Chip Select to Output tCO - 55 - 70 ns Output Enable to Valid Output tOE - 25 - 35 ns UB, LB Access Time tBA - 25 - 35 ns Read Cycle Time Read 55ns Chip Select to Low-Z Output tLZ 10 - 10 - ns UB, LB Enable to Low-Z Output tBLZ 5 - 5 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - ns Chip Disable to High-Z Output tHZ 0 20 0 25 ns UB, LB Disable to High-Z Output tBHZ 0 20 0 25 ns Output Disable to High-Z Output tOHZ 0 20 0 25 ns Output Hold from Address Change tOH 10 - 10 - ns Write Cycle Time tWC 55 - 70 - ns Chip Select to End of Write tCW 45 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 45 - 60 - ns UB, LB Valid to End of Write tBW 45 - 60 - ns Write Pulse Width tWP 40 - 50 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 20 0 20 ns Data to Write Time Overlap tDW 25 - 30 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS1≥Vcc-0.2V Data retention current IDR Vcc=1.5V, CS1≥Vcc-0.2V Data retention set-up time tSDR Recovery time tRDR 1) 1) See data retention waveform Min Typ2) Max 1.5 - 3.6 V - 0.5 6 µA 0 - - tRC - - Unit ns 1. CS1 ≥Vcc-0.2V,CS2≥ Vcc-0.2V(CS1 controlled) or CS2 ≥Vcc-0.2V(CS2 controlled). 2. Typical value are measured at TA=25°C and not 100% tested. 5 Revision 1.0 September 2001 K6F8016V3A Family CMOS SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tBA UB, LB tBHZ tOE OE Data out High-Z tOLZ tBLZ tLZ tOHZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 September 2001 K6F8016V3A Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tWR(4) tCW(2) CS tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z 7 Revision 1.0 September 2001 K6F8016V3A Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(t WP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0V 2.2V VDR CS≥VCC - 0.2V CS GND 8 Revision 1.0 September 2001 K6F8016V3A Family CMOS SRAM PACKAGE DIMENSION Unit: millimeters 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0~8° 0.25 ( ) 0.010 #44 #23 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.76±0.20 0.463±0.008 ( 0.50 ) 0.020 #1 #22 1.00±0.10 0.039±0.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.35± 0.10 0.014±0.004 0.80 0.0315 0.0 0.10 MAX 0.004 0.05 MIN. 0.002 18.81 MAX. 0.741 18.41±0.10 0.725±0.004 0 + 0.1 5 - 0.0 04 .0 +0 06 - 0.002 0.15 0~8° 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) ( #1 0.25 ) 0.010 #22 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.76±0.20 0.463±0.008 ( 0.50 ) 0.020 #44 #23 1.00±0.10 0.039±0.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.35±0.10 0.014±0.004 0.80 0.0315 0.05 MIN. 0.002 18.81 MAX. 0.741 18.41± 0.10 0.725±0.004 9 0 + 0.1 5 - 0.0 04 .0 +0 02 .006 - 0.0 0.15 0 0.10 0.004 MAX Revision 1.0 September 2001