SAMSUNG K1S161611A

Preliminary
K1S161611A
UtRAM
Document Title
1Mx16 bit Uni-Transistor Random Access Memory
Revision History
Revision No. History
Draft Date
Remark
Preliminary
0.0
Initial Draft
October 6, 2003
0.1
Revised
- Added Lead Free 48-FBGA-6.00x7.00 Product
November 25, 2003 Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
-1-
Revision 0.1
November 2003
Preliminary
K1S161611A
UtRAM
1M x 16 bit Uni-Transistor CMOS RAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The K1S161611A is fabricated by SAMSUNG′s advanced
CMOS technology using one transistor memory cell. The device
supports Industrial temperature range and 48 ball Chip Scale
Package for user flexibility of system design. The device also
supports dual chip selection for user interface.
Process Technology: CMOS
Organization: 1M x16 bit
Power Supply Voltage: 2.7V~3.1V
Three State Outputs
Compatible with Low Power SRAM
Dual Chip selection support
• Package Type: 48-FBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temp.
Vcc Range
Speed
Standby
(ISB1, Max.)
Operating
(ICC2, Max.)
PKG Type
K1S161611A-I
Industrial(-40~85°C)
2.7V~3.1V
70ns
80µA
30mA
48-FBGA-6.00x7.00
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
1
2
3
4
5
6
Clk gen.
A
LB
OE
A0
A1
A2
CS2
B
I/O9
UB
A3
A4
CS1
I/O1
Vcc
Vss
Row
Addresses
C
I/O10
I/O11
A5
A6
I/O2
I/O3
D
Vss
I/O12
A17
A7
I/O4
Vcc
E
Vcc
I/O13
NC
A16
I/O5
Vss
F
I/O15
I/O14
A14
A15
I/O6
I/O7
G
I/O16
A19
A12
A13
WE
I/O8
H
A18
A8
A9
A10
A11
NC
Precharge circuit.
I/O1~I/O8
Row
select
Data
cont
Memory array
I/O Circuit
Column select
Data
cont
I/O9~I/O16
Data
cont
Column Addresses
CS1
CS2
48-FBGA: Top View(Ball Down)
OE
Control Logic
WE
UB
LB
Name
CS1,CS2
Function
Name
Function
Chip Select Inputs
Vcc
Power
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
UB
Upper Byte(I/O9~16)
LB
Lower Byte(I/O1~8)
NC
No Connection
A0~A19
Address Inputs
I/O1~I/O16 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
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Revision 0.1
November 2003
Preliminary
K1S161611A
UtRAM
POWER UP SEQUENCE
1. Apply power.
2. Maintain stable power(Vcc min.=2.7V) for a minimum 200µs with CS1=high or CS2=low.
TIMING WAVEFORM OF POWER UP(1) (CS1 controlled)
VCC
≈ ≈
CS2
≈
CS1
Min. 200µs
≈
VCC(Min)
Power Up Mode
Normal Operation
POWER UP(1)
1. After VCC reaches VCC(Min.), wait 200µs with CS1 high. Then the device gest into the normal operation.
TIMING WAVEFORM OF POWER UP(2) (CS2 controlled)
VCC
≈
CS2
≈ ≈
CS1
Min. 200µs
≈
VCC(Min)
Power Up Mode
Normal Operation
POWER UP(2)
1. After VCC reaches VCC(Min.), wait 200µs with CS2 low. Then the device gets into the normal operation.
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Revision 0.1
November 2003
Preliminary
K1S161611A
UtRAM
FUNCTIONAL DESCRIPTION
CS1
H
CS2
OE
WE
UB
1)
X
1)
High-Z
High-Z
Deselected
Standby
1)
High-Z
High-Z
Deselected
Standby
High-Z
High-Z
Deselected
Standby
X
X
L
X
1)
X
X
X
X1)
X1)
X1)
X1)
H
H
L
H
H
H
L
X
L
H
H
H
X1)
L
1)
X1)
1)
LB
1)
X
1)
X
1)
1)
I/O1~8
I/O9~16
Mode
Power
High-Z
High-Z
Output Disabled
Active
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
H
L
H
L
L
Dout
Dout
Word Read
Active
L
H
X1)
L
L
H
Din
High-Z
Lower Byte Write
Active
L
H
X
1)
L
H
L
High-Z
Din
Upper Byte Write
Active
L
H
X1)
L
L
L
Din
Din
Word Write
Active
1. X means don′t care.(Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
Ratings
Unit
VIN, VOUT
-0.2 to VCC+0.3V
V
VCC
-0.2 to 3.6V
V
PD
1.0
W
TSTG
-65 to 150
°C
TA
-40 to 85
°C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
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Revision 0.1
November 2003
Preliminary
K1S161611A
UtRAM
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
K1S161611A-FI70
48-FBGA-6.00x7.00, 70ns
48-FBGA-6.00x7.00, 70ns
K1S161611A-BI701)
1. Lead Free Product
RECOMMENDED DC OPERATING CONDITIONS1)
Symbol
Min
Typ
Max
Unit
Supply voltage
Item
Vcc
2.7
2.9
3.1
V
Ground
Vss
0
0
0
Input high voltage
VIH
2.2
-
VCC+0.3
Input low voltage
VIL
-0.33)
-
0.6
V
V
V
2)
1. TA=-40 to 85°C, otherwise specified.
2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns.
3. Undershoot: -1.0V in case of pulse width ≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Symbol
Test Condition
Min
Max
Unit
Input capacitance
Item
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max Unit
ILI
VIN=Vss to Vcc
-1
-
1
µA
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH,
VIO=Vss to Vcc
-1
-
1
µA
ICC1
Cycle time=1µs, 100% duty, IIO=0mA, CS1≤0.2V, LB≤0.2V
or/and UB≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V
-
-
7
mA
ICC2
Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH
LB=VIL or/and UB=VIL, VIN=VIH or VIL
-
-
30
mA
Output low voltage
VOL
IOL = 2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH = -0.1mA
2.4
-
-
V
Standby Current(CMOS)
ISB1
Other inputs=0~Vcc
1) CS1≥VCC-0.2V, CS2≥VCC-0.2V(CS1 controlled) or
2) 0V ≤ CS2 ≤ 0.2V(CS2 controlled)
-
-
80
µA
Input leakage current
Output leakage current
Average operating current
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Revision 0.1
November 2003
Preliminary
K1S161611A
UtRAM
AC OPERATING CONDITIONS
Dout
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL=50pF
CL
1. Including scope and jig capacitance
AC CHARACTERISTICS(Vcc=2.7~3.1V, TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read
Write
Units
70ns
Max
Read Cycle Time
tRC
70
-
ns
Address Access Time
tAA
-
70
ns
Chip Select to Output
tCO
-
70
ns
Output Enable to Valid Output
tOE
-
35
ns
UB, LB Access Time
tBA
-
70
ns
Chip Select to Low-Z Output
tLZ
10
-
ns
UB, LB Enable to Low-Z Output
tBLZ
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
ns
Chip Disable to High-Z Output
tHZ
0
25
ns
UB, LB Disable to High-Z Output
tBHZ
0
25
ns
Output Disable to High-Z Output
tOHZ
0
25
ns
Output Hold from Address Change
tOH
5
-
ns
Write Cycle Time
tWC
70
-
ns
Chip Select to End of Write
tCW
60
-
ns
Address Set-up Time
tAS
0
-
ns
Address Valid to End of Write
tAW
60
-
ns
UB, LB Valid to End of Write
tBW
60
-
ns
Write Pulse Width
tWP
551)
-
ns
Write Recovery Time
tWR
0
-
ns
Write to Output High-Z
tWHZ
0
25
ns
Data to Write Time Overlap
tDW
30
-
ns
Data Hold from Write Time
tDH
0
-
ns
End Write to Output Low-Z
tOW
5
-
ns
1. tWP(min)=70ns for continuous write operation over 50 times.
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Revision 0.1
November 2003
Preliminary
K1S161611A
UtRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Out
Data Valid
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS1
CS2
tHZ
tBA
UB, LB
tBHZ
tOE
OE
tOLZ
tBLZ
Data out
High-Z
tOHZ
tLZ
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. tOE(max) is met only when OE becomes enabled after tAA(max).
4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or
needs to sustain standby state for min. tRC at least once in every 4us.
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Revision 0.1
November 2003
Preliminary
K1S161611A
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
tCW(2)
tWR(4)
CS1
CS2
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
Data in
High-Z
tDH
tWHZ
Data out
High-Z
Data Valid
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tAS(3)
tWR(4)
tCW(2)
CS1
tAW
CS2
tBW
UB, LB
tWP(1)
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
High-Z
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Revision 0.1
November 2003
Preliminary
K1S161611A
UtRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
tWC
Address
tAS(3)
tWR(4)
tCW(2)
CS1
tAW
CS2
tBW
UB, LB
tWP(1)
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
Address
tWR(4)
tCW(2)
CS1
tAW
CS2
UB, LB
tBW
tAS(3)
tWP(1)
WE
tDW
Data Valid
Data in
Data out
tDH
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
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Revision 0.1
November 2003
Preliminary
K1S161611A
UtRAM
PACKAGE DIMENSION
Unit: millimeters
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)
Top View
Bottom View
B
B1
B
6
5
4
3
2
1
A
#A1
B
C
C
C
C1
D
C1/2
E
F
G
H
B/2
Detail A
Side View
A
Y
0.55/Typ.
E1
E
0.35/Typ.
E2
D
C
Min
Typ
Max
A
-
0.75
-
B
5.90
6.00
6.10
1. Bump counts: 48(8 row x 6 column)
B1
-
3.75
-
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
C
6.90
7.00
7.10
C1
-
5.25
-
D
0.40
0.45
0.50
E
-
0.90
1.00
E1
-
0.55
-
E2
0.30
0.35
0.40
Y
-
-
0.10
Notes.
3. All tolerence are ±0.050 unless
specified beside figures.
4. Typ : Typical
5. Y is coplanarity: 0.10(Max)
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Revision 0.1
November 2003