K6T8016C3M Family CMOS SRAM Document Title 512Kx16 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial draft June 18, 1999 Advance 1.0 Finalize - Adopt New Code system. - Improve VIN, VOUT max. on A ’ BSOLUTE MAXIMUM RATINGS’from 7.0V to VCC+0.5V. February 29, 2000 Final Errata correction April 17, 2000 Final 1.01 The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.01 April 2000 K6T8016C3M Family CMOS SRAM 512Kx16 bit Low Power CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology: TFT • Organization: 512K x16 • Power Supply Voltage: 4.5~5.5V • Low Data Retention Voltage: 2.0V(Min) • Three state output and TTL Compatible • Package Type: 44-TSOP2-400F/R The K6T8016C3M families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support industrial operating temperature ranges for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRO DUCT FAMILY Power Dissipation Product Family Operating Temperature K6T8016C3M-B Commercial(0~70°C) K6T8016C3M-F Industrial(-40~85°C) Vcc Range Speed 4.5~5.5V 551)/70ns Standby (ISB1, Max) Operating (ICC2, Max) 50µA 90mA PKG Type 44-TSOP2-400F/R 80µA 1. The parameter is measured with 50pF test load. FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-TSOP2 Forward 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 A8 A9 A10 A11 A12 A13 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 A8 A9 A10 A11 A12 A13 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-TSOP2 Reverse 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A18 A17 A16 A15 A14 Clk gen. Precharge circuit. Vcc Vss Row Addresses I/O1~I/O8 Row select Data cont Memory array 1024 rows 512×16 columns I/O Circuit Column select Data cont I/O9~I/O16 Data cont Name Function Name Function Column Addresses CS Chip Select Input Vcc Power OE Output Enable Input Vss Ground WE Write Enable Input UB Upper Byte(I/O9~16) Address Inputs LB Lower Byte(I/O1~8) A0~A18 I/O1~I/O16 Data Inputs/Outputs CS OE WE Control Logic UB LB SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.01 April 2000 K6T8016C3M Family CMOS SRAM PRODUCT LIST Commercial Temperature Products(0~70°C) Part Name Industrial Temperature Products(-40~85°C) Function Part Name Function K6T8016C3M-TB55 K6T8016C3M-TB70 44-TSOP2-F, 55ns, Low Low Power 44-TSOP2-F, 70ns, Low Low Power K6T8016C3M-TF55 K6T8016C3M-TF70 44-TSOP2-F, 55ns, Low Low Power 44-TSOP2-F, 70ns, Low Low Power K6T8016C3M-RB55 K6T8016C3M-RB70 44-TSOP2-R, 55ns, Low Low Power 44-TSOP2-R, 70ns, Low Low Power K6T8016C3M-RF55 K6T8016C3M-RF70 44-TSOP2-R, 55ns, Low Low Power 44-TSOP2-R, 70ns, Low Low Power FUNCTIONAL DESCRIPTION CS OE WE LB UB I/O1~8 I/O9~16 Mode Power H X X X X High-Z High-Z Deselected Standby L H H X X High-Z High-Z Output Disabled Active L X X H H High-Z High-Z Output Disabled Active L L H L H Dout High-Z Lower Byte Read Active L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active L X L L H Din High-Z Lower Byte Write Active L X L H L High-Z Din Upper Byte Write Active L X L L L Din Din Word Write Active Note: X means don′t care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol Ratings Unit Remark VIN,VOUT VCC -0.5 to VCC+0.5V V - -0.3 to 7.0 V - PD 1.0 W - TSTG -65 to 150 °C - 0 to 70 °C K6T8016C3M-B -40 to 85 °C K6T8016C3M-F TA 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.01 April 2000 K6T8016C3M Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Symbol Min Typ Max Unit Supply voltage Item Vcc 4.5 5.0 5.5 V 0 Ground Vss 0 0 Input high voltage VIH 2.2 - Input low voltage VIL -0.5 3) V Vcc+0.5 - V 2) 0.8 V Note: 1. Commercial Product: T A=0 to 70°C, otherwise specified. Industrial Product: TA=-40 to 85°C, otherwise specified. 2. Overshoot: VCC+3.0V in case of pulse width ≤30ns. 3. Undershoot: -3.0V in case of pulse width ≤30ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f=1MHz, TA=25°C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH, OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS=VIL, WE=VIH, VIN=VIH or VIL - - 12 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS≤0.2V, VIN≤0.2V or VIN≥VCC-0.2V - - 15 mA ICC2 Cycle time=Min, I IO=0mA, 100% duty, CS=VIL, VIN=VIL or VIH - - 90 mA Output low voltage VOL IOL = 2.1mA - - 0.4 V Output high voltage VOH IOH = -1.0mA 2.4 - - V Standby Current(TTL) ISB CS=VIH, Other inputs=VIH or VIL Average operating current Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc 4 - - 3 mA K6T8016C3M-B - - 50 µA K6T8016C3M-F - - 80 Revision 1.01 April 2000 K6T8016C3M Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=50pF+1TTL CL1) 1.Including scope and jig capacitance AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial product:TA=0 to 70°C, Industrial product:TA=-40 to 85°C) Speed Bins Parameter List Symbol 55ns Min Write Max Min Max Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO - 55 - 70 ns Output enable to valid output tOE - 25 - 35 ns Chip select to low-Z output Read Units 70ns tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns LB, UB enable to low-Z output tBLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 25 ns Output Disable to High-Z Output tOHZ 0 20 0 25 ns Output hold from address change tOH 10 - 10 - ns LB, UB valid to data output tBA - 25 - 35 ns UB, LB disable to high-Z output tBHZ 0 20 0 25 ns Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 55 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 20 - 30 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns LB, UB valid to end of write tBW 45 - 60 - ns DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Symbol Test Condition VDR CS≥Vcc-0.2V IDR Vcc=3.0V, CS≥Vcc-0.2V CS≥Vcc-0.2V Data retention set-up time tSDR Recovery time tRDR See data retention waveform 5 Min Typ Max Unit 2.0 - 5.5 V K6T8016C3M-B - - 20 µA K6T8016C3M-F - - 30 0 - - 5 - - ms Revision 1.01 April 2000 K6T8016C3M Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tBA UB, LB tBHZ tOE OE Data out High-Z tOLZ tBLZ tLZ tOHZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.01 April 2000 K6T8016C3M Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z 7 Revision 1.01 April 2000 K6T8016C3M Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(t WP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 4.5V 2.2V VDR CS≥VCC - 0.2V CS GND 8 Revision 1.01 April 2000 K6T8016C3M Family CMOS SRAM PACKAGE DIMENSIONS Unit: millimeters(inches) 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0~8° 0.25 ( ) 0.010 #44 #23 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.76±0.20 0.463±0.008 ( 0.50 ) 0.020 #1 #22 1.00±0.10 0.039±0.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.35± 0.10 0.014±0.004 0.80 0.0315 0.0 0.10 MAX 0.004 0.05 MIN. 0.002 18.81 MAX. 0.741 18.41±0.10 0.725±0.004 0 + 0.1 5 - 0.0 04 .0 +0 06 - 0.002 0.15 0~8° 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) ( #1 0.25 ) 0.010 #22 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.76±0.20 0.463±0.008 ( 0.50 ) 0.020 #44 #23 1.00±0.10 0.039±0.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.35±0.10 0.014±0.004 0.80 0.0315 0.05 MIN. 0.002 18.81 MAX. 0.741 18.41± 0.10 0.725±0.004 9 0 + 0.1 5 - 0.0 04 .0 +0 02 .006 - 0.0 0.15 0 0.10 0.004 MAX Revision 1.01 April 2000