K1S3216BCD UtRAM Document Title 2Mx16 bit Page Mode Uni-Transistor Random Access Memory Revision History Revision No. History Draft Date Remark 0.0 Initial Draft November 02, 2004 Preliminary 1.0 Finalize Apri 06, 2005 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. -1- Revision 1.0 April 2005 K1S3216BCD UtRAM 2M x 16 bit Page Mode Uni-Transistor CMOS RAM FEATURES GENERAL DESCRIPTION • • • • • The K1S3216BCD is fabricated by SAMSUNG′s advanced CMOS technology using one transistor memory cell. The device support 4 page mode operation, Industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The device also supports deep power down mode for low standby current. Process Technology: CMOS Organization: 2M x16 bit Power Supply Voltage: 1.7~2.0V Three State Outputs Compatible with Low Power SRAM • Support 4 page read mode • Package Type: 48-FBGA-6.00x8.00 PRODUCT FAMILY Product Family Operating Temp. Vcc Range Speed (tRC) K1S3216BCD-I Industrial(-40~85°C) 1.7~2.0V 70/85ns 2 Standby (ISB1, Max.) Operating (ICC2, Max.) PKG Type 100µA 35mA 48-FBGA-6.00x8.00 FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION 1 Power Dissipation 3 4 5 6 Clk gen. A LB OE A0 A1 A2 CS2 B I/O9 UB A3 A4 CS1 I/O1 Vcc Vss Row Addresses C I/O10 I/O11 A5 A6 I/O2 I/O3 D Vss I/O12 A17 A7 I/O4 Vcc E Vcc I/O13 DNU A16 I/O5 Vss I/O1~I/O8 I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 A19 A12 A13 WE I/O8 H A18 A8 A9 A10 A11 A20 Row select Data cont Memory array I/O Circuit Column select Data cont I/O9~I/O16 F Precharge circuit. Data cont Column Addresses CS1 CS2 48-FBGA: Top View(Ball Down) OE Control Logic WE UB Name Function CS1,CS2 Chip Select Inputs Name Vcc Power OE Output Enable Input Vss Ground WE Write Enable Input UB Upper Byte(I/O9~16) Address Inputs LB Lower Byte(I/O1~8) A0~A20 I/O1~I/O16 Data Inputs/Outputs DNU LB Function Do Not Use1) 1) Reserved for future use SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2- Revision 1.0 April 2005 K1S3216BCD UtRAM POWER UP SEQUENCE 1. Apply power. 2. Maintain stable power(Vcc min.=1.7V) for a minimum 200µs with CS1=high.or CS2=low. TIMING WAVEFORM OF POWER UP(1) (CS1 controlled) VCC Min. 200µs ≈ VCC(Min) ≈ CS1 ≈ ≈ CS2 Power Up Mode Normal Operation POWER UP(1) 1. After VCC reaches VCC(Min.), wait 200µs with CS1 high. Then the device gets into the normal operation. TIMING WAVEFORM OF POWER UP(2) (CS2 controlled) VCC ≈ CS2 ≈ ≈ CS1 Min. 200µs ≈ VCC(Min) Power Up Mode Normal Operation POWER UP(2) 1. After VCC reaches VCC(Min.), wait 200µs with CS2 low. Then the device gets into the normal operation. -3- Revision 1.0 April 2005 K1S3216BCD UtRAM FUNCTIONAL DESCRIPTION CS1 CS2 H X X1) L 1) OE 1) WE LB UB I/O1~8 I/O9~16 Mode Power 1) 1) X X High-Z High-Z Deselected Standby X1) X1) X1) X1) High-Z High-Z Deselected Standby 1) 1) X H H High-Z High-Z Deselected Standby X 1) 1) X X X1) X L H H H L X L H H H X1) L L H L H L L H L H H L H L H L H X1) L L H X1) L L H X1) L High-Z High-Z Output Disabled Active High-Z High-Z Output Disabled Active H Dout High-Z Lower Byte Read Active L High-Z Dout Upper Byte Read Active L L Dout Dout Word Read Active L H Din High-Z Lower Byte Write Active H L High-Z Din Upper Byte Write Active L L Din Din Word Write Active 1) 1. X means don′t care.(Must beVIL or VIH state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol Ratings Unit VIN, VOUT -0.2 to VCC+0.3V V VCC -0.2 to 2.5V V PD 1.0 W TSTG -65 to 150 °C TA -40 to 85 °C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability. -4- Revision 1.0 April 2005 K1S3216BCD UtRAM PRODUCT LIST Industrial Temperature Product(-40~85°C) Part Name Function K1S3216BCD-FI70 K1S3216BCD-FI85 48-FBGA, 70ns, 1.8V 48-FBGA, 85ns, 1.8V RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Min Typ Max Unit Supply voltage Vcc 1.7 1.85 2.0 V Ground Vss 0 0 0 V Input high voltage VIH 1.4 - Vcc+0.32) V Input low voltage VIL -0.23) - 0.4 V Min Max Unit 1. TA=-40 to 85°C, otherwise specified. 2. Overshoot: Vcc+1.0V in case of pulse width ≤3ns. 3. Undershoot: -1.0V in case of pulse width ≤3ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1)(f=1MHz, TA=25°C) Item Symbol Test Condition Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Item Test Conditions Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH ,VIO=Vss to Vcc -1 - 1 µA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS1≤0.2V, LB≤0.2V or/and UB≤0.2V, CS2≥Vcc-0.2V, VIN≤0.2V or VIN≥VCC-0.2V - - 5 mA ICC2 Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL,VIN=VIL or VIH - 35 mA Output low voltage VOL IOL=0.1mA - - 0.2 V Output high voltage VOH IOH=-0.1mA 1.4 - - V Standby Current(CMOS) ISB12) Other inputs = 0~Vcc 1) CS1≥Vcc-0.2V, CS2≤Vcc-0.2V (CS1 controlled) or 2) 0V≤CS2≤0.2V(CS2 controlled) - - 100 µA Symbol Average operating current Min Typ1) 1. Typical values are tested at VCC=1.8V, TA=25°C and not guaranteed. 2. ISB1 is measured after 60ms from the time when standby mode is set up. -5- Revision 1.0 April 2005 K1S3216BCD UtRAM AC OPERATING CONDITIONS Dout TEST CONDITIONS(Test Load and Test Input/Output Reference) Input pulse level: 0.2 to Vcc-0.2V Input rising and falling time: 5ns Input and output reference voltage: 0.5 x VCC Output load (See right): CL=50pF CL 1. Including scope and jig capacitance AC CHARACTERISTICS (Vcc=1.7~2.0V, TA=-40 to 85°C) Speed Bins Parameter List Common Read Write Symbol 70ns Units 85ns Min Max Min Max tCSHP 10 - 10 - ns Read Cycle Time tRC 70 - 85 - ns Address Access Time tAA - 70 - 85 ns Chip Select to Output tCO - 70 - 85 ns Output Enable to Valid Output tOE - 35 - 40 ns UB, LB Access Time tBA - 70 - 85 ns Chip Select to Low-Z Output tLZ 10 - 10 - ns UB, LB Enable to Low-Z Output tBLZ 10 - 10 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - ns Chip Disable to High-Z Output tHZ 0 25 0 25 ns UB, LB Disable to High-Z Output tBHZ 0 25 0 25 ns Output Disable to High-Z Output tOHZ 0 25 0 25 ns Output Hold from Address Change tOH 3 - 3 - ns Page Cycle tPC 25 - 25 - ns CS High Pulse Width Page Access Time tPA - 20 - 20 ns Write Cycle Time tWC 70 - 85 - ns Chip Select to End of Write tCW 60 - 70 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 60 - 70 - ns UB, LB Valid to End of Write tBW 60 - 70 - ns Write Pulse Width tWP 55 - ns 1) - 60 1) Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 25 0 25 ns Data to Write Time Overlap tDW 30 - 35 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns 1. tWP(min)=70ns or tWC(min)=90ns for continuous write operation over 50 times. -6- Revision 1.0 April 2005 K1S3216BCD UtRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2)(WE=VIH) tRC Address tCSHP tOH tAA tCO CS1 CS2 tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ Data out tOHZ tLZ High-Z Data Valid TIMING WAVEFORM OF PAGE CYCLE(READ ONLY) A20~A2 Valid Address A1~A0 Valid Address Valid Address tAA Valid Address Valid Address tPC CS1 CS2 tCO OE tPA tOE DQ15~DQ0 High Z Data Valid tOHZ Data Valid Data Valid Data Valid (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. tOE(max) is met only when OE becomes enabled after tAA(max). 4. If invalid address signals shorter than min. tRC are continuously repeated for over 4us, the device needs a normal read timing(tRC) or needs to sustain standby state for min. tRC at least once in every 4us. -7- Revision 1.0 April 2005 K1S3216BCD UtRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC tWC Address tAW tCW tCSHP tWR tWR tAW tCW CS tBW tBW UB, LB tWHP tWP WE tAS tAS tDH tDW Data Valid tDH tDW Data Valid Data in tWHZ Data out tWP tWHZ tOW Data Undefined tOW Data Undefined Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS tWR tCW CS1 tAW CS2 tBW UB, LB tWP WE tDW Data Valid Data in Data out tDH High-Z -8- Revision 1.0 April 2005 K1S3216BCD UtRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS tWR tCW CS1 tAW CS2 tBW UB, LB tWP(1) WE tDW tDH Data Valid Data in Data out High-Z TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled) tWC Address tWR tCW CS1 tAW CS2 tBW UB, LB tAS tWP WE tDW Data Valid Data in Data out tDH High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high. -9- Revision 1.0 April 2005 K1S3216BCD UtRAM PACKAGE DIMENSION Unit: millimeters 48 BALL FINE PITCH BGA(0.75mm ball pitch) Top View Bottom View B B1 B 6 5 4 3 2 1 A #A1 B C C C C1 D E F G H Detail A Side View A E1 D E1 E Y C Min Typ Max A - 0.75 - B 5.90 6.00 6.10 1. Bump counts: 48(8 row x 6 column) B1 - 3.75 - 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) C 7.90 8.00 8.10 C1 - 5.25 - D 0.40 0.45 0.50 E - E1 0.25 Y - Notes. 3. All tolerence are ±0.050 unless specified beside figures. 4. Typ : Typical 5. Y is coplanarity 1.00 - 0.10 - 10 - Revision 1.0 April 2005