DG221B New Product Vishay Siliconix Quad SPST CMOS Analog Switch with Latches FEATURES D D D D BENEFITS APPLICATIONS Accepts 150-ns Write Pulse Width D Compatible with Most mP Buses 5-V On-Chip Regulator D Allows Wide Power Supply Tolerance Without Affecting TTL Compatibility Latches Are Transparent with WR Low D Reduced Power Consumption Low On-Resistance: 60 W D Allows Flexibility of Design D D D D D D mP Based Systems Automatic Test Equipment Communication Systems Data Acquisition Systems Medical Instrumentation Factory Automation DESCRIPTION The DG221B is a monolithic quad single-pole, single-throw analog switch designed for precision switching applications in communication, instrumentation and process control systems. Featuring independent onboard latches and a common WR pin, each DG221B can be memory mapped, and addressed as a single data byte for simultaneous switching. The DG221B combines low power and low on-resistance (60 W typical) while handling continuous currents up to 20 mA. An epitaxial layer prevents latchup. The device features true bidirectional performance in the on condition. FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION Four Latchable SPST Switches per Package Dual-In-Line and SOIC TRUTH TABLE IN1 1 16 IN2 D1 2 15 D2 3 14 S2 V– 4 13 V+ GND 5 12 WR S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 Input Latch S1 INX WR 0 0 ON 1 0 OFF Control data latched-in, switches on or off as selected by last INX X X 1 Document Number: 71616 S-03627—Rev. A, 23-Apr-01 Maintains previous state Logic “0” v 0.8 V Logic “1” w 2.4 V ORDERING INFORMATION Temp Range Top View Switch –40_C _ to 85_C _ Package Part Number 16-Pin Plastic DIP DG221BDJ 16-Pin Narrow SOIC DG221BDY www.vishay.com 1 DG221B New Product Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Storage Temperature: Voltages Referenced to V– V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 V (DJ and DY Suffix) . . . . . . . . . . . –65 to 125_C Power Dissipation (Package)b 16-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 16-Pin SOICd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Inputsa, VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –2 V to (V+) +2 V Notes: a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 6.5 mW/_C above 25_C d. Derate 7.7 mW/_C above 75_C or 20 mA, whichever occurs first Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D (Pulsed 1 ms, 10% duty cycle) . . . . . . . . . . . . . . 70 mA SCHEMATIC DIAGRAM (TYPICAL CHANNEL) V+ 5V Reg S GND INX V– – + Latch V– V+ WR Level Shift/ Drive V+ – + D V– FIGURE 1. www.vishay.com 2 Document Number: 71616 S-03627—Rev. A, 23-Apr-01 DG221B New Product Vishay Siliconix SPECIFICATIONSa Limits Test Conditions Unless Otherwise Specified Parameter –40 to 85_C V+ = 15 V, V– = –15 V VIN = 2.4 V, 0.8f V, WR = 0 Tempb Mind VANALOG Full –15 rDS(on) IS = –10 mA, VD = "10 V Room Full Symbol Typc Maxd Unit Analog Switch Analog Signal Rangee Drain-Source On-Resistance Source Off Leakage Current IS(off) Drain Off Leakage Current ID(off) Drain On Leakage Current ID(on) IINL , IINH 15 V 60 90 135 W Room Full –5 –100 "0.01 5 100 Room Full –5 –100 "0.02 5 100 VS = VD = "14 V Room Full –5 –200 "0.01 5 200 VIN = 0 V or = 2.4 V Room Full –1 –10 –0.0004 1 10 VS = "14 " V, VD = #14 # V nA Digital Control Input Current mA Dynamic Characteristics Turn-On Time Turn-Off Time Turn-On Time Write Turn-Off Time Write tON tOFF tON, WR tOFF, WR Write Pulse Width tW Input Setup Time tS Input Hold Time tH Charge Injection See Figure 2 Q Source-Off Capacitance CS(off) Drain-Off Capacitance CD(off) Channel-On Capacitance CD(on) Off Isolation OIRR Interchannel Crosstalk XTALK See Figure 3 See Figure 4 CL = 1000 pF VGEN = 0 V, RGEN = 0 W f = 1 MHz, VS, VD = 0 V VS = 1 Vp-p, f = 100 kHz CL = 15 pF, RL = 1 kW Room 550 Room 340 Room 550 Room 340 Room 150 120 Room 180 130 Room 20 18 Room 20 Room 8 Room 9 Room 29 Room 70 Room 90 ns pC pF dB Power Supplies Positive Supply Current I+ Negative Supply Current I– All Channels On or Off VIN = 0 V or 2.4 V Full Room 0.8 –1 –0.4 1.5 mA Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. Document Number: 71616 S-03627—Rev. A, 23-Apr-01 www.vishay.com 3 DG221B New Product Vishay Siliconix TEST CIRCUITS +15 V V+ 2V S Logic Input D VO IN GND WR V– Switch Input CL 35 pF RL 1 kW 3V 50% tr < 10 ns tf < 10 ns 0V VS 90% Switch Output VO tOFF tON –15 V CL (includes fixture and stray capacitance) RL VO = VS RL + rDS(on) FIGURE 2. Switching Time +15 V 3V 0V WR 2V WR S 50% 0V V+ D IN VO 3V tr < 10 ns tf < 10 ns 0V IN GND V– RL 1 kW CL 35 pF VS VOUT 90% VO –15 V tOFF , WR tON, WR CL (includes fixture and stray capacitance) VO = VS RL RL + rDS(on) FIGURE 3. WR Switching Time 3V 50% IN tS tH tS tH 3V 50% WR tW tH = Hold Time tS = Setup Time tW = WR Pulse Width VOUT The latches are level sensitive. When WR is held low the latches are transparent and the switches respond to the digital inputs. The digital inputs are latched on the rising edge of WR. FIGURE 4. www.vishay.com 4 WR Setup Conditions Document Number: 71616 S-03627—Rev. A, 23-Apr-01 DG221B New Product Vishay Siliconix TEST CIRCUITS +15 V DVO V+ Rg S Vg VO D VO CL 1000 pF IN 3V WR OFF INX V– ON OFF DVO = measured voltage error due to charge injection The charge injection in coulombs is Q = CL x DVO –15 V FIGURE 5. Charge Injection +15 V +15 V C C V+ S VS S1 VS V+ VO D Rg = 50 W Rg = 50 W NC GND WR V– 50 W IN1 0V RL IN 2.4 V D1 C 0V S2 D2 VO RL IN2 GND WR V– C –15 V Off Isolation = 20 log –15 V VS VO C = RF bypass XTALK Isolation = 20 log VS VO C = RF bypass FIGURE 7. Channel-to-Channel Crosstalk FIGURE 6. Off Isolation APPLICATION HINTSa V+ Positive Supply Voltage (V) V– Negative Supply Voltage (V) GND (V) WR (V) VIN Logic Input Voltage VINH(min)/VINL(max) (V) VS or VD Analog Voltage Range (V) 15 –15 0 2.4/0.8 2.4/0.8 –15 to 15 10 –10 0 2.4/0.8 2.4/0.8 –10 to 10 10 –5 0 2.4/0.8 2.4/0.8 –5 to 10 Notes: a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing. Document Number: 71616 S-03627—Rev. A, 23-Apr-01 www.vishay.com 5 DG221B New Product Vishay Siliconix APPLICATIONS VIN +15 V V+ 9 MW S1 DG221B IN1 D 900 kW Q C D1 S2 IN2 D 90 kW Q C D2 Data Bus S3 IN3 D 9 kW Q C D3 S4 IN4 D 1 kW Q C WR D4 WR V– GND CS Address Decoder Address Bus + TL081 – –15 V The TL081 is used as an output buffer while the voltage divider provides attenuation. VO FIGURE 8. mP-Controlled Analog Signal Attenuator TRUTH TABLE OUTPUT ATTENUATION FOR FIGURE 8 IN1 IN2 IN3 IN4 WRA ON SWITCH WR IN1 IN2 IN3 IN4 0 0 0 0 0 All 0 0 1 1 1 0.1 1 1 1 1 0 None 0 1 0 1 1 0.01 0 1 1 1 0 1 0 1 1 0 1 0.001 1 0 1 1 0 2 0 1 1 1 0 0.0001 1 1 0 1 0 3 1 1 1 0 0 4 Gain Notes: a. WR may be held at “0” for temporary operation similar to DG201A/DG201B. With WR at “0” SW1 will remain on as long as IN1 is held at “0”. www.vishay.com 6 Document Number: 71616 S-03627—Rev. A, 23-Apr-01