K4S511632D CMOS SDRAM DDP 512Mbit SDRAM 8M x 16bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 July. 2002 This is to advise Samsung customers that in accordance with certain terms of an agreement, Samsung is prohibited from selling any DRAM products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as mainframes, servers, work stations or desk top personal computers (hereinafter "Prohibited Computer Use"). Applications such as mobile, including cell phones, telecom, including televisions and display monitors, or non-desktop computer systems, including laptops, notebook computers, are , however, permissible. "Multi-Die Plastic" is defined as two or more Dram die encapsulated within a single plastic leaded package * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 July. 2002 K4S511632D CMOS SDRAM Revision 0.0 (July, 2002) Rev. 0.0 July. 2002 K4S511632D CMOS SDRAM 8M x 16Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply The K4S511632D is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,392,608words by 16bits, fabri- • LVTTL compatible with multiplexed address cated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION • DQM for masking Part No. • Auto & self refresh • 64ms refresh period (8K Cycle) Max Freq. Interface Package K4S511632D-KC/L7C 133MHz(CL=2) K4S511632D-KC/L75 133MHz(CL=3) K4S511632D-KC/L1H 100MHz(CL=2) K4S511632D-KC/L1L 100MHz(CL=3) LVTTL 54pin TSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 2 x 4M x 16 2 x 4M x 16 Output Buffer 2 x 4M x 16 Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS A ddress Register CLK 2 x 4M x 16 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE DQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 July. 2002 K4S511632D CMOS SDRAM PIN CONFIGURATION (Top view) V DD DQ0 V DDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 V DD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 V SS N.C/RFU UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 V SS 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System cock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A 0 ~ A 12 Address Row/column addresses are multiplexed on the same pins. Row address : RA 0 ~ RA12 , Column address : CA 0 ~ CA 9 BA 0 ~ BA 1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. L(U)DQM Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when L(U)DQM active. D Q0 ~ Data input/output Data inputs/outputs are multiplexed on the same pins. V DD /VSS Power supply/ground Power and ground for the input buffers and the core logic. V DDQ /VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No connection /reserved for future use This pin is recommended to be left No Connection on the device. 15 Rev. 0.0 July. 2002 K4S511632D CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Voltage on any pin relative to Vss Parameter V I N, VOUT -1.0 ~ 4.6 V Voltage on V DD supply relative to Vss V DD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 2 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, T A = 0 to 70°C) Parameter Symbol Min Typ Max Unit V DD, VDDQ 3.0 3.3 3.6 V Input logic high voltage V IH 2.0 3.0 V DD +0.3 V 1 Input logic low voltage V IL -0.3 0 0.8 V 2 Output logic high voltage V OH 2.4 - - V IOH = -2mA Output logic low voltage V OL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. V I H (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ V IN ≤ V DDQ . Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. (V DD = 3.3V, T A = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) CAPACITANCE Pin Clock RAS, CAS , WE, DQM Symbol Min Max Unit C CLK 5.0 9.0 pF C IN 5.0 10.0 pF Address, CS,CKE CADD 5.0 10.0 pF D Q0 ~ DQ 8 COUT 4.0 6.5 pF Note Rev. 0.0 July. 2002 K4S511632D CMOS SDRAM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T A = 0 to 70°C) Parameter Symbol Active standby current in non power-down mode (One bank active) -75 -1H -1L 200 180 180 180 Unit Note mA 1 Burst length = 1 tR C ≥ tRC(min) IO = 0 mA ICC2P CKE ≤ V IL(max), tCC = 10ns 4 ICC2 PS CKE & CLK ≤ V IL (max), tCC = ∞ 4 ICC2 N CKE ≥ V I H(min), CS ≥ V I H(min), tCC = 10ns Input signals are changed one time during 20ns 40 ICC2NS CKE ≥ V I H(min), CLK ≤ V IL (max), t CC = ∞ Input signals are stable 20 CKE ≤ V IL(max), tCC = 10ns 12 ICC3 PS CKE & CLK ≤ V IL (max), tCC = ∞ 12 ICC3 N CKE ≥ V I H(min), CS ≥ V I H(min), tCC = 10ns Input signals are changed one time during 20ns 60 mA ICC3NS CKE ≥ V I H(min), CLK ≤ V IL (max), t CC = ∞ Input signals are stable 50 mA Precharge standby current in non power-down mode Active Standby current in power-down mode -7C ICC1 Operating current (One bank active) Precharge standby current in power-down mode Version Test Condition ICC3P mA mA mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4banks activated. tCCD = 2CLKs 220 220 240 240 mA 1 Refresh current ICC5 tR C ≥ tRC(min) 440 400 380 380 mA 2 Self refresh current ICC6 CKE ≤ 0.2V C 6 mA 3 L 3 mA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S511632D-KC** 4. K4S511632D-KL** 5. Unless otherwise noticed, input swing level is CMOS(V IH/VIL =V DDQ/V SSQ). Rev. 0.0 July. 2002 K4S511632D CMOS SDRAM AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter AC input levels (Vih/Vil) Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω V OH (DC) = 2.4V, I O H = -2mA V OL (DC) = 0.4V, I OL = 2mA Output 870Ω Output Z0 = 50Ω 50pF 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -7C -75 -1H -1L Unit Note Row active to row active delay tRRD (min) 15 15 20 20 ns 1 RAS to CAS delay tRCD (min) 15 20 20 20 ns 1 Row precharge time tRP(min) 15 20 20 20 ns 1 Row active time tRAS (min) 45 45 50 50 ns 1 tRAS (max) Row cycle time tRC (min) Last data in to row precharge tRDL (min) Last data in to Active delay 100 ns 1 2 CLK 2, 5 tDAL (min) 2 CLK + tRP - 5 Last data in to new col. address delay tCDL (min) 1 CLK 2 Last data in to burst stop tBDL (min) 1 CLK 2 Col. address to col. address delay tCCD (min) 1 CLK 3 CAS latency=3 2 ea 4 CAS latency=2 1 Number of valid output data 60 65 us 70 70 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Rev. 0.0 July. 2002 K4S511632D CMOS SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter -7C Symbol Min CLK cycle time CAS latency=3 tCC CAS latency=2 CLK to valid output delay CAS latency=3 Output data hold time CAS latency=3 7.5 -75 Max 1000 7.5 tSAC CAS latency=2 tO H CAS latency=2 Min 7.5 -1H Max 1000 10 Min 10 -1L Max 1000 10 Min 10 Unit Note ns 1 ns 1,2 ns 2 Max 1000 12 5.4 5.4 6 6 5.4 6 6 7 3 3 3 3 3 3 3 3 CLK high pulse width tCH 2.5 2.5 3 3 ns 3 CLK low pulse width tCL 2.5 2.5 3 3 ns 3 Input setup time tSS 1.5 1.5 2 2 ns 3 Input hold time tSH 0.8 0.8 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 tSHZ CAS latency=2 5.4 5.4 6 6 5.4 6 6 7 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. DQ BUFFER OUTPUT DRIVE CHARACTERISTICS Parameter Symbol Condition Min Output rise time trh Measure in linear region : 1.2V ~1.8V Output fall time tfh Output rise time Output fall time Typ Max Unit Notes 1.37 4.37 Volts/ns 3 Measure in linear region : 1.2V ~1.8V 1.30 3.8 Volts/ns 3 trh Measure in linear region : 1.2V ~1.8V 2.8 3.9 5.6 Volts/ns 1,2 tfh Measure in linear region : 1.2V ~1.8V 2.0 2.9 5.0 Volts/ns 1,2 Notes : 1. Rise time specification based on 0pF + 50 Ohms to V SS, use these values to design to. 2. Fall time specification based on 0pF + 50 Ohms to V DD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to V SS . Rev. 0.0 July. 2002 K4S511632D CMOS SDRAM SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H H Bank active & row addr. H X Read & column address Auto precharge disable H X Write & column address Auto precharge disable L H H H H X X X L L H H X V L H L H X V X X L H L L H X X L L H L H H L L X Exit Entry H L H L H L Precharge power down mode Exit L V Column address (A0 ~ A9 ) L X X All banks Entry L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 3 Column address (A0 ~ A9 ) H H Clock suspend or active power down 3 Row address H H Note 1,2 X Auto precharge enable Bank selection A 11,A 12, A9 ~ A 0 3 Auto precharge enable Burst Stop A 10/AP L L Precharge BA 0,1 X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A 0 ~ A12 & BA 0 ~ BA 1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA 0 ~ BA1 : Bank select addresses. If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A10 /AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 0.0 July. 2002