KM48S8030C Preliminary PC133 CMOS SDRAM Revision History Revision 0.0 (Oct., 1998) • PC133 first published. REV. 0 Oct. '98 Preliminary PC133 CMOS SDRAM KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The KM48S8030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. • • • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency 3 only -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle) ORDERING INFORMATION Part No. Max Freq. KM48S8030CT-G/FA 133MHz (CL 3) Interface Package LVTTL 54 TSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 2M x 8 2M x 8 2M x 8 Output Buffer Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 2M x 8 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE DQM * Samsung Electronics reserves the right to change products or specification without notice. REV. 0 Oct. '98 Preliminary PC133 CMOS SDRAM KM48S8030C PIN CONFIGURATION (Top view) VDD DQ0 VDDQ N.C DQ1 VSSQ N.C DQ2 VDDQ N.C DQ3 VSSQ N.C VDD N.C WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin CLK Name Input Function System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. DQ0 ~ 7 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No connection /reserved for future use This pin is recommended to be left No Connection on the device. REV. 0 Oct. '98 Preliminary PC133 CMOS SDRAM KM48S8030C ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V VIH 2.0 3.0 VDDQ+0.3 V Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA Input leakage current (Inputs) IIL -1 - 1 uA 3 Input leakage current (I/O pins) IIL -1.5 - 1.5 uA 3,4 Supply voltage Input logic high voltage Note 1 Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Symbol Min Max Unit CCLK 2.5 4.0 pF CIN 2.5 5.0 pF Address CADD 2.5 5.0 pF DQ0 ~ DQ7 COUT 4.0 6.5 pF Clock RAS, CAS, WE, CS, CKE, DQM REV. 0 Oct. '98 Preliminary PC133 CMOS SDRAM KM48S8030C DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Symbol ICC1 ICC2P Active standby current in power-down mode Active standby current in non power-down mode (One bank active) CAS Latency CKE ≤ VIL(max), tCC = 15ns 1 ICC3NS Note mA 1 mA 1 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns 12 mA 6 CKE ≤ VIL(max), tCC = 15ns 2 ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC3N Unit -A 75 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ ICC2NS Input signals are stable ICC3P Version Burst length = 1 tRC ≥ tRC(min) IOL = 0 mA ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N Precharge standby current in non power-down mode Test Condition mA 2 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns 20 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 10 mA IOL = 0 mA Page burst 2Banks activated tCCD = 2CLKs Operating current (Burst mode) ICC4 Refresh current ICC5 tRC ≥ tRC(min) Self refresh current ICC6 CKE ≤ 0.2V 3 110 - - mA 1 125 mA 2 1 mA 3 450 uA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. KM48S8030CT-G** 4. KM48S8030CT-F** REV. 0 Oct. '98 Preliminary PC133 CMOS SDRAM KM48S8030C AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output 870Ω Output Z0 = 50Ω 50pF 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note CLK 1 -A Row active to row active delay tRRD(min) RAS to CAS delay tRCD(min) 3 CLK 1 tRP(min) 3 CLK 1 tRAS(min) 6 CLK 1 tRAS(max) 100 us Row cycle time tRC(min) 9 CLK 1 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to new col. address Delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 Row precharge time Row active time Number of valid output data 2 CAS latency=3 2 - - Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. REV. 0 Oct. '98 Preliminary PC133 CMOS SDRAM KM48S8030C AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter -A Symbol Min CLK cycle time CAS latency=3 tCC CLK to valid output delay CAS latency=3 Output data hold time CAS latency=3 7.5 Note 1000 ns 1 ns 1,2 ns 2 5.4 tSAC - 2.7 tOH - CLK high pulse width Unit Max tCH 2.5 ns 3 CLK low pulse width tCL 2.5 ns 3 Input setup time tSS 1.5 ns 3 Input hold time tSH 0.8 ns 3 CLK to output in Low-Z tSLZ 1 ns 2 CLK to output in Hi-Z CAS latency=3 5.4 tSHZ - ns - Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. REV. 0 Oct. '98 Preliminary PC133 CMOS SDRAM KM48S8030C SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H BA0,1 L H L H H H H X X X X L H H X V Read & column address Auto precharge disable H X L H L H X V Write & Column Address Auto precharge disable Auto precharge enable X L H L L X H X X L L H L H H L V H L Exit L H Entry H L Precharge power down mode Exit Column address (A0 ~ A8) L L X X All banks Entry L Column address (A0 ~ A8) H H L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row address H Auto precharge enable Clock suspend or active power down 3 3 L Precharge 1,2 X X H Note 3 H Bank selection A11, A9 ~ A0 L Bank active & row addr. Burst stop A10/AP X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) REV. 0 Oct. '98