SAMSUNG KC73125UBA

KC73125UBA
1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
INTRODUCTION
16Pin Cer DIP
The KC73125UBA is an interline transfer CCD area image
sensor developed for EIA 1/3 inch optical format video cameras,
surveillance cameras, object detectors and image pattern
recognizers. High sensitivity is achieved through the on-chip
micro lenses and HAD (Hole Accumulated Diode) photosensors.
This chip features a field integration read out system and an
electronic shutter with variable charge storage time.
FEATURES
ORDERING INFORMATION
•
High Sensitivity
•
Optical Size 1/3 inch Format
•
Variable Speed Electronic Shutter
(1/60, 1/100 ~ 1/10,000sec)
•
Low Dark Current
•
Horizontal Register 5V Drive
•
16pin Ceramic DIP Package
•
Field Integration Read Out System
•
No DC Bias on Reset Gate
Device
Package
Operating
KC73125UBA
16Pin Cer DIP
-10 °C ~ +60 °C
STRUCTURE
•
Number of Total Pixels:
537(H) × 505(V)
•
Number of Effective Pixels:
510(H) × 492(V)
•
Chip Size:
6.00mm(H) × 4.95mm(V)
•
Unit Pixel Size:
9.60µm(H) × 7.50µm(V)
•
Optical Blacks & Dummies:
Refer to Figure Below
Vertical 1 Line (Even Field Only)
16 2
510
25
1
492
V-CCD
Effective
Imaging
Area
Dummy Pixels
Optical Black Pixels
Effective Pixels
12
OUTPUT
H-CCD
1
1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
KC73125UBA
BLOCK DIAGRAM
(Top View)
8
VOUT
7
VSS
6
VGG
5
GND
4
ΦV1
3
ΦV2
2
1
ΦV3
ΦV4
Vertical Shift Register CCD
Vertical Shift Register CCD
Vertical Shift Register CCD
Vertical Shift Register CCD
Horizontal Shift Register CCD
9
VDD
10
GND
11
SUB
12
VL
13
ΦRS
14
NC
15
ΦH1
16
ΦH2
Figure 1. Block Diagram
PIN DESCRIPTION
Table 1. Pin Description
2
Pin
Symbol
1
ΦV4
2
Description
Pin
Symbol
Description
Vertical CCD transfer clock 4
9
VDD
Output stage drain bias
ΦV3
Vertical CCD transfer clock 3
10
GND
Ground
3
ΦV2
Vertical CCD transfer clock 2
11
SUB
Substrate bias
4
ΦV1
Vertical CCD transfer clock 1
12
VL
5
GND
Ground
13
ΦRS
Charge reset clock
6
VGG
Output stage gate bias
14
NC
No connection
7
VSS
Output stage source bias
15
ΦH1
Horizontal CCD transfer clock 1
8
VOUT
Signal output
16
ΦH2
Horizontal CCD transfer clock 2
Protection circuit bias
KC73125UBA
1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
ABSOLUTE MAXIMUM RATINGS (NOTE)
Table 2. Absolute Maximum Ratings
Characteristics
Symbols
Min.
Max.
Unit
Substrate voltage
SUB - GND
-0.3
55
V
Supply voltage
VDD, VOUT, VSS - GND
-0.3
18
V
VDD, VOUT, VSS - SUB
-55
10
V
ΦV1,ΦV2, ΦV3, ΦV4 - GND
-10
20
V
ΦV1, ΦV2, ΦV3, ΦV4 - V L
-0.3
30
V
ΦV1, ΦV2, ΦV3, ΦV4 - SUB
-55
10
V
ΦH1, ΦH2 - GND
-0.3
10
V
ΦH1, ΦH2 - SUB
-55
17
V
15
V
27
V
17
V
Vertical clock input voltage
Horizontal clock input voltage
Voltage difference between vertical and
horizontal clock input pins
ΦV1, ΦV2, ΦV3, ΦV4
ΦH1, ΦH2
ΦH1, ΦH2 - ΦV4
-17
17
V
ΦRS, VGG - GND
-0.3
15
V
ΦRS, VGG - SUB
-55
10
V
Protection circuit bias voltage
VL - SUB
-55
10
V
Operating temperature
TOP
-10
60
°C
Storage temperature
TSTG
-30
80
°C
Output clock input voltage
NOTE: The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage
or temperature.
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1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
KC73125UBA
DC CHARACTERISTICS
Table 3. DC Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
Output stage drain bias
VDD
14.55
15.0
15.45
V
Output stage gate voltage
VGG
1.75
2.0
2.25
V
Output stage source voltage
VSS
Ground through 680Ω
V
Substrate voltage adjustment range
VSUB
7.0
14.5
V
∆VSUB
-3
3
%
Fluctuation voltage range after substrate
voltage adjusted
Protection circuit bias voltage
VL
Output stage drain current
IDD
Remark
±5%
The lowest vertical clock level
2.5
mA
CLOCK VOLTAGE CONDITIONS
Table 4. Clock Voltage Conditions
Item
Read-out clock voltage
Vertical transfer clock voltage
Horizontal transfer clock voltage
Charge reset clock voltage
Substrate clock voltage
4
Symbol
Min.
Typ.
Max.
Unit
Remark
VVH1, VVH3
14.55
15.0
15.45
V
High level
VVM1 ~ V VM4
-0.2
0.0
0.2
V
Middle
VVL1 ~ V VL4
-9.5
-9.0
-8.5
V
Low
VHH1, VHH2
4.75
5.0
5.25
V
High
VHL1, VHL2
-0.2
0.0
0.2
V
Low
VRSH
4.75
5.0
5.25
V
High
VRSL
-0.2
0.0
0.2
V
Low
VΦSUB
20
23.0
25
V
Shutter
KC73125UBA
1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
100%
90%
VVH 1, VVH3
10%
0%
tr
twh
0V
tf
Vertical Transfer Clock Waveform
¥Õ V 1
¥Õ V 3
V VH
V VH
V V HL
VVHL
VVHH
V VH H
V VHH
VVHH
VVH1
V VH L
VVHL
V VH3
V VL H
V VL 1
V VL 3
V VL
¥Õ V 2
V VH H
V VL H
V VL L
V VHH
V VL L
V VL
¥Õ V 4
V VH
V V HH
V VH
V VH H
V VHL
V VH2
V VHL
V VHL
V VL 2
V VL L
V VL 4
= ( V V H 1 + V V H 2)/ 2
V V L = (V V L 3 + V V L 4)/ 2
V ¥Õ V = V V H n - V V L n
V VHL
V VL H
V VL H
V VL
V VH
V VH 4
(n =1~4)
V VH H
V VL L
V VL
= V V H + 0. 3V
V V H L = V V H - 0. 3 V
V V L H = V V L + 0. 3V
V V L L = V V L - 0. 3 V
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1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
KC73125UBA
Horizontal Transfer Clock Waveform Diagram
tr
twh
tf
90%
V¥ÕH
twl
10%
VH L
Reset Gate Clock Waveform Diagram
tr
twh
tf
VR GH
twl
V¥ÕRG
Point A
RG waveform
VRGL + 0.5V
VRGLH
VRGLL
VRGL
¥ÕH1 waveform
10%
VRGLH is the maximum value and VRGLL the minimum value of the coupling waveform in the period from Point A in
the diagram about to RG rise
VRGL = (VRGLH + VRGLL)/2, VFRG = VRGH - VRGL
Substrate Clock Waveform
100%
90%
V¥ÕSU B
10%
VSU B
6
0%
tr
twh
tf
KC73125UBA
1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
CLOCK EQUIVALENT CIRCUIT CONSTANT
Table 5. Clock Equivalent Circuit Constant
twh
Item
Vertical clock
tr
tf
Unit
Min.
Read-out clock
twl
Symbol
ΦVH
Typ.
Max.
Min.
Typ.
2.5
Max.
Min.
Typ.
Max.
Min.
0.5
Typ.
Max.
µs
0.5
ΦV1, ΦV2
ΦV3, ΦV4
15
250
ns
ΦH1
37
41
38
42
12
15
10
15
ns
ΦH2
37
41
38
42
12
15
10
15
ns
Reset clock
ΦRG
11
15
75
79
6.5
Substrate clock
ΦSUB
1.5
2.0
Horizontal clock
4.5
0.5
ns
0.5
µs
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1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
KC73125UBA
EQUIVALENT CIRCUIT PARAMETERS
Table 6. Equivalent Circuit Parameters
Item
Symbol
Typ.
Unit
C ΦV1, CΦV3
1,300
pF
C ΦV2, CΦV4
1,300
pF
CΦV12, CΦV34
600
pF
CΦV23, CΦV41
230
pF
CΦV13
120
pF
CΦV24
90
pF
CΦH1, CΦH2
38
pF
Capacitance between horizontal transfer clocks
CΦH12
38
pF
Capacitance between substrate clock and GND
CΦSUB
1120
pF
RΦV1 ~ RΦV4
40
Ω
Vertical transfer clock ground resistor
RΦVGND
15
Ω
Horizontal transfer clock serial resistor
RΦH1, RΦH2
10
Ω
RΦRS
100
Ω
Capacitance between vertical transfer clock and GND
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock and GND
Vertical transfer clock serial resistor
Reset gate clock serial resistor
¥ÕV1
¥ÕV2
R ¥ÕV1
R ¥ÕV2
C ¥ÕV12
C ¥ÕV1
C ¥ÕV2
R ¥ÕH1
C ¥ÕH12
¥ÕH1
C ¥ÕV41
C ¥ÕV24
C ¥ÕV13
C ¥ÕV23
R ¥ÕVGND
C ¥ÕV4
C ¥ÕV34
R ¥ÕV4
¥ÕV4
8
C ¥ÕV3
R ¥ÕV3
¥ÕV3
C ¥ÕH1
R ¥ÕH2
¥ÕH2
C ¥ÕH2
Remark
KC73125UBA
1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
OPERATING CHARACTERISTICS
Device Temperature = 25 °C
Table 7. Operating Characteristics
Item
Sensitivity
Saturation signal
Symbol
Min.
Typ.
S
95
105
YSAT
600
Smear
SM
Blooming margin
BM
0.007
Max.
0.015
1,000
Unit
Remark
mV/lux
1
mV
2
%
3
times
4
Uniformity
U
20
%
5
Dark signal (NOTE)
D
2
mV
6
∆D
2
mV
7
YLAG
0.5
%
8
FY
1
%
9
Dark shading (NOTE)
Image lag
Flicker
NOTE: Test Temperature = 60 °C
TEST CONDITION
1. Use a light source with color temperature of 3,200K hallogen lamp and CM-500S for IR cut filter.
The light source is adjusted in accordance with the average value of Y signals indicated in each item.
2. Through the following tests the substrate voltage should be set to the value while the device condition
should be kept within the range of the bias and clock conditions.
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1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
KC73125UBA
TEST METHODS
1. Measure the light intensities (L) when the averaged illuminance output value (Y) is the standard illuminance
output value, 150mV (YA) and when half of 150mV (1/2 YA).
1
Y A – --- Y A
2
S = -------------------------L YA – L 1
-- Y A
2
2. Adjust the light intensity to 15 times of the value with which Y is YA, then measure the averaged illuminance
output value (Y = YSAT).
3. Adjust the light intensity to 500 times of the value with which Y is YA, then remove the read-out clock and drain
the signal in photosensors by the electronic shutter operation in all the respective horizontal blanking times with
the other clocks unchanged. Measure the maximum illuminance output value (YSM).
Y SM
1 - ----1
- × -------× - × 100 ( % )
SM = --------Y A 500 10
4. Adjust the light intensity to 1,000 times of the value with which Y is YA, then inspect whether there is blooming
phenomenon or not.
5. Measure the maximum and minimum illuminance output value (YMAX, YMIN) when the light intensity is adjusted
to make Y to be YA.
Y MAX – Y MIN
× 100 ( % )
U = -------------------------------YA
6. Measure YD with the horizontal idling time transfer level as reference, when the device ambient temperature is
60 °C and all of the light sources are shielded.
7. Follow test method 6, measure the maximum (DMAX) and minimum illuminance output (DMIN).
∆ D = D MAX – D MIN
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KC73125UBA
1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
8. Adjust the light intensity of Y signal output value by strobe light to 150mV (YA), calculate by below formula with
measuring the image lag signal which is qenerated by below timing diagram.
Y LAG = ( Y lag ⁄ 150 ) × 100 ( % )
FLD
SG1
Light
Strobe
Timing
Y Signal
Output 150mV
YLag
Output
9. Adjust the light intensity of Y signal average value to 150mV (YA), calculate by below formula with measuring
the signal differences (∆Yf [mV]) between fields.
F Y = ( ∆ Y f ⁄ Y A ) × 100 ( % )
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1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
KC73125UBA
SPECTRAL RESPONSE CHARACTERISTICS
Excluding Light Source Characteristics
1
0.9
Spectral Response
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
425
450
475
500
525
550
575
600
Wave Length (nm)
Figure 2. Spectral Response Characteristics
12
625
650
675
700
KC73125UBA
1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
APPLICATION CIRCUITS
5V
ΦH2 ΦH1 ΦRS
XSUB XV2 XV1 SG1 XV3 SG2 XV4
50K
1
3
2
4
6
5
7
8
9
10
14
13
12
11
104
KS7221D
20
19
18
17
16
15
100K
MA110
- +
10µ/25V
22µ
+ -
-
+
47µ/16V
1µ/10V
680
27K
15V
ΦH2 16
2 ΦV3
ΦH1 15
3
ΦV2
4
ΦV1
5
GND
6
VGG
KC73125UBA
103
1 ΦV4
NC 14
ΦRS 13
10
VL 12
SUB 11
7 VSS
GND 10
8 VOUT
VDD 9
180K
KSC2757
103
+
100
103
-
+
10µ/25V
+
1µ/50V
3.9K
-
10µ/25V
-9V
15V
CCD
Output
Figure 3. Application Circuits
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1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
KC73125UBA
READ-OUT CLOCK TIMING CHART
Unit: [µs]
HD
V1
2.5
Odd
Field V2
V3
V4
38.1
1.2
1.5
2.5 2.0
0.3
V1
V2
Even
Field
V3
V4
Figure 4. Read-out Clock Timing Chart
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KC73125UBA
1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
CLOCK TIMING CHART (VERTICAL SYNC.)
FLD
VD
BLK
280
275
270
265
260
20
15
10
525
1
2
3
4
5
520
HD
SG1
SG2
V1
V2
V3
V4
CCD
OUT
492
491
246
135
246
135
492
491
246
135
2468
1357
CLP1
Figure 5. Clock Timing Chart (Vertical Sync.)
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1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
KC73125UBA
CLOCK TIMING CHART (HORIZONTAL SYNC.)
10
5
3
2
1
2
1
16
15
10
5
3
2
1
25
20
15
10
5
3
2
1
510
505
Figure 6. Clock Timing Chart (Horizontal Sync.)
16
SUB
CLP1
V4
V3
V2
V1
XSHD
XSHP
RS
H2
H1
BLK
HD
500
KC73125UBA
1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
PACKAGE DIMENSIONS
Unit: mm
t = 0.25¡¾0.02
8.20¡¾0.10
10.00¡¾0.10
11.40¡¾0.10
2.50
2-R0.50
7.20¡¾0.10
Package Material
Ceramic
9.20¡¾0.10
Lead Material
42 Alloy
12.20¡¾0.12
1.10¡¾0.08
2.80¡¾0.30
1.27¡¾0.25
3.50¡¾0.50
0.30¡¾0.10
1.27¡¾0.05
1.27¡¿7 = 8.89¡¾0.10
11.60¡¾0.12
Figure 7. Package Dimensions
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1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
KC73125UBA
HANDLING INSTRUCTIONS
•
Static Charge Prevention
CCD image sensors can be easily damaged by static discharge. Before handling, be sure to take the following
protective measures.
— Use non chargeable gloves, clothes or material. Also use conductive shoes.
— When handling directly, use an earth band.
— Install a conductive mat on the floor or working table to prevent generation of static electricity.
— Ionized air is recommended for discharging when handling CCD image sensor.
— For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
•
Soldering
— Make sure the package temperature does not exceed 80 °C.
— Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and and remount, cool sufficiently.
— To dismount an imaging device, do not use a solder suction equipment. When using an electronic
disoldering tool, use a thermal controller of the zero cross on/off type and connect to ground.
•
Dust and Dirt Protection
— Operate in the clean environments (around class 1000 will be appropriate).
— Do not either touch glass plates by hand or have object come in contact with glass surface. Should dirt
stick to a glass surface blow it off with an air blow(for dirt stuck through static electricity ionized air is
recommended).
— Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be caerful not to scratch
the glass.
— Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving
to a room with great temperature differences.
— When a protective tape is applied before shipping, just before use remove the tape applied electrostatic
protection. Do not reuse the tape.
•
Do not expose to strong light (sun rays) for long period, color filter are discolored.
•
Exposure to high temperature or humidity will affect the characteristics. accordingly avoid storage or usage in
such conditions.
•
CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
18